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Change subject: drivers/intel/fsp2_0: Remove unused save_mrc_data implementation
......................................................................
Patch Set 11:
(1 comment)
Patchset:
PS11:
This patch has nothing in common with what it started as. Because the comments on the original are irrelevant now, I'd recommend abandoning this patch and starting with a new Change-ID.
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Change subject: util/amdfwtool: Deal with psp position in flash offset directly
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Patch Set 28: Code-Review+2
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Change subject: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config
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Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/77557/comment/54e410b8_6e7ddaa1 :
PS3, Line 19:
This block is really hard to read because of wrapping. Can we use this instead?
```
w/o this patch:
| | Save MRC Cache | Finalize Cache | Lock Boot Medium |
+------------+----------------+----------------+------------------+
| MRC_STASH | BS_DEV | BS_DEV | BS_DEV |
| TO_CBMEM | ENUMERATE_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY |
+------------+----------------+----------------+------------------+
| SAVE_MRC | BS_DEV_INIT | BS_DEV | BS_DEV |
| AFTER_FSPS | CHIPS_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY |
w/ this patch:
| | Save MRC Cache | Finalize Cache | Lock Boot Medium |
+------------+----------------+----------------+------------------+
| MRC_STASH | BS_DEV | BS_DEV | BS_DEV |
| TO_CBMEM | ENUMERATE_EXIT | ENUMERATE_EXIT | RESOURCES_ENTRY |
```
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Change subject: soc/amd/genoa: Add minimal viable code for compilation
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Patch Set 8: Code-Review+2
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Change subject: drivers/mrc_cache: Fix extra space at the beginning of line
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Patch Set 2: Code-Review+2
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Change subject: mb/google/rex/var/screebo: remove SD_ABSENT
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/rex/variants/screebo/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/77596/comment/192e4561_fd095979 :
PS2, Line 21: 11 12
> do we need 2 bits for SD DB now ?
IMHO, we can keep using 2 bits for more options.
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