coreboot-gerrit August 2023

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[S] Change in coreboot[master]: mb/google/rex/var/screebo: sync fw_config with build matrix
by YH Lin (Code Review) 31 Aug '23

31 Aug '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun. YH Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77596?usp=email ) Change subject: mb/google/rex/var/screebo: sync fw_config with build matrix ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Please help to split into 3 cls (if possible) […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/77596?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfa472ff5570ac728038ec67a762289407760812 Gerrit-Change-Number: 77596 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 31 Aug 2023 16:31:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex/var/screebo: sync fw_config with build matrix
by Subrata Banik (Code Review) 31 Aug '23

31 Aug '23

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun, YH Lin. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77596?usp=email ) Change subject: mb/google/rex/var/screebo: sync fw_config with build matrix ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Please help to split into 3 cls (if possible) 1. SD card 2. FP 3. WIFI -- To view, visit https://review.coreboot.org/c/coreboot/+/77596?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfa472ff5570ac728038ec67a762289407760812 Gerrit-Change-Number: 77596 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Thu, 31 Aug 2023 16:23:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex/var/screebo: sync fw_config with build matrix
by YH Lin (Code Review) 31 Aug '23

31 Aug '23

YH Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77596?usp=email ) Change subject: mb/google/rex/var/screebo: sync fw_config with build matrix ...................................................................... mb/google/rex/var/screebo: sync fw_config with build matrix In addition, 1. Remove SD_ABSENT since it's not being used. 2. Hook up WiFi SAR table once it's defined BUG=b:291155207 TEST=emerge-rex coreboot Change-Id: Icfa472ff5570ac728038ec67a762289407760812 Signed-off-by: YH Lin <yueherngl(a)google.com> --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/variants/screebo/overridetree.cb M src/mainboard/google/rex/variants/screebo/variant.c 3 files changed, 17 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/77596/1 diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index cc15b7b..d991028 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -59,6 +59,7 @@ config BOARD_GOOGLE_MODEL_SCREEBO def_bool n select BOARD_GOOGLE_BASEBOARD_REX + select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_GENERIC_ALC1015 select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_GENESYSLOGIC_GL9750_INVERT_WP diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 63c753e..ae4e5a3 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -18,10 +18,17 @@ option TOUCHSCREEN_ILITEK 1 option TOUCHSCREEN_ELAN 2 end + field FP_MCU 10 10 + option FP_MCU_STM 0 + option FP_MCU_NPCX 1 + end field DB_SD 11 12 - option SD_ABSENT 0 - option SD_GL9750 1 - option SD_RTS5227S 2 + option SD_GL9750 0 + option SD_RTS5227S 1 + end + field WIFI_SAR_ID 13 13 + option WIFI_SAR_ID_0 0 + option WIFI_SAR_ID_1 1 end end diff --git a/src/mainboard/google/rex/variants/screebo/variant.c b/src/mainboard/google/rex/variants/screebo/variant.c index 4044fd4..4ea6598 100644 --- a/src/mainboard/google/rex/variants/screebo/variant.c +++ b/src/mainboard/google/rex/variants/screebo/variant.c @@ -3,6 +3,12 @@ #include <chip.h> #include <fw_config.h> #include <baseboard/variants.h> +#include <sar.h> + +const char *get_wifi_sar_cbfs_filename(void) +{ + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_SAR_ID)); +} void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config) { -- To view, visit https://review.coreboot.org/c/coreboot/+/77596?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfa472ff5570ac728038ec67a762289407760812 Gerrit-Change-Number: 77596 Gerrit-PatchSet: 1 Gerrit-Owner: YH Lin <yueherngl(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: crossgcc: Upgrade MPFR from 4.2.0 to 4.2.1
by Elyes Haouas (Code Review) 31 Aug '23

31 Aug '23

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/77375?usp=email ) Change subject: crossgcc: Upgrade MPFR from 4.2.0 to 4.2.1 ...................................................................... crossgcc: Upgrade MPFR from 4.2.0 to 4.2.1 Change-Id: I1fb3630bf5e8a56ddcf6102faffde568134accc9 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77375 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/releases/coreboot-4.22-relnotes.md M util/crossgcc/buildgcc D util/crossgcc/sum/mpfr-4.2.0.tar.xz.cksum A util/crossgcc/sum/mpfr-4.2.1.tar.xz.cksum 4 files changed, 3 insertions(+), 2 deletions(-) Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified diff --git a/Documentation/releases/coreboot-4.22-relnotes.md b/Documentation/releases/coreboot-4.22-relnotes.md index d4da9bf..a6beccc 100644 --- a/Documentation/releases/coreboot-4.22-relnotes.md +++ b/Documentation/releases/coreboot-4.22-relnotes.md @@ -23,6 +23,7 @@ * Upgrade GMP from 6.2.1 to 6.3.0 * Upgrade binutils from 2.40 to 2.41 +* Upgrade MPFR from 4.2.0 to 4.2.1 ### Additional coreboot changes diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 56c839f..ebc9fcb 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -36,7 +36,7 @@ # GCC toolchain version numbers GMP_VERSION=6.3.0 -MPFR_VERSION=4.2.0 +MPFR_VERSION=4.2.1 MPC_VERSION=1.3.1 GCC_VERSION=11.4.0 BINUTILS_VERSION=2.41 diff --git a/util/crossgcc/sum/mpfr-4.2.0.tar.xz.cksum b/util/crossgcc/sum/mpfr-4.2.0.tar.xz.cksum deleted file mode 100644 index 4a67091..0000000 --- a/util/crossgcc/sum/mpfr-4.2.0.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -4f734ca3ebceac28e2f944b131a47133b19e2c5e tarballs/mpfr-4.2.0.tar.xz diff --git a/util/crossgcc/sum/mpfr-4.2.1.tar.xz.cksum b/util/crossgcc/sum/mpfr-4.2.1.tar.xz.cksum new file mode 100644 index 0000000..b74dc62 --- /dev/null +++ b/util/crossgcc/sum/mpfr-4.2.1.tar.xz.cksum @@ -0,0 +1 @@ +31ffb4244cb469e2b4937cce1f50150300971dfb tarballs/mpfr-4.2.1.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/77375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fb3630bf5e8a56ddcf6102faffde568134accc9 Gerrit-Change-Number: 77375 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: util/crossgcc: Update binutils from 2.40 to 2.41
by Elyes Haouas (Code Review) 31 Aug '23

31 Aug '23

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76852?usp=email ) Change subject: util/crossgcc: Update binutils from 2.40 to 2.41 ...................................................................... util/crossgcc: Update binutils from 2.40 to 2.41 Change-Id: I6c985974e2eeea1329b2dbb232711c72b0bd99bc Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76852 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M Documentation/releases/coreboot-4.22-relnotes.md M util/crossgcc/buildgcc D util/crossgcc/patches/binutils-2.40_stop_losing_entry_point_when_LTO_enabled.patch R util/crossgcc/patches/binutils-2.41_as-ipxe.patch R util/crossgcc/patches/binutils-2.41_no-makeinfo.patch D util/crossgcc/sum/binutils-2.40.tar.xz.cksum A util/crossgcc/sum/binutils-2.41.tar.xz.cksum 7 files changed, 47 insertions(+), 90 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/Documentation/releases/coreboot-4.22-relnotes.md b/Documentation/releases/coreboot-4.22-relnotes.md index d7013b2..d4da9bf 100644 --- a/Documentation/releases/coreboot-4.22-relnotes.md +++ b/Documentation/releases/coreboot-4.22-relnotes.md @@ -22,6 +22,7 @@ ### Toolchain updates * Upgrade GMP from 6.2.1 to 6.3.0 +* Upgrade binutils from 2.40 to 2.41 ### Additional coreboot changes diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 033aac0..56c839f 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -39,7 +39,7 @@ MPFR_VERSION=4.2.0 MPC_VERSION=1.3.1 GCC_VERSION=11.4.0 -BINUTILS_VERSION=2.40 +BINUTILS_VERSION=2.41 IASL_VERSION="R06_28_23" # CLANG version number CLANG_VERSION=16.0.6 diff --git a/util/crossgcc/patches/binutils-2.40_stop_losing_entry_point_when_LTO_enabled.patch b/util/crossgcc/patches/binutils-2.40_stop_losing_entry_point_when_LTO_enabled.patch deleted file mode 100644 index 548540c..0000000 --- a/util/crossgcc/patches/binutils-2.40_stop_losing_entry_point_when_LTO_enabled.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 3539414584be0094b0a4fe56dfd64ea79d802edc Mon Sep 17 00:00:00 2001 -From: Nick Clifton <nickc(a)redhat.com> -Date: Thu, 4 May 2023 14:24:16 +0100 -Subject: [PATCH] Stop the linker from loosing the entry point for COFF/PE code - when compiling with LTO enabled. - - PR 30300 - * emultempl/pep.em (set_entry_point): Add an undefined reference to the entry point if it has been constructed heuristically. - * emultempl/pe.em (set_entry_point): Likewise. ---- - -diff --git a/ld/emultempl/pe.em b/ld/emultempl/pe.em -index 55412d6ef9e..1f2a5f310be 100644 ---- a/ld/emultempl/pe.em -+++ b/ld/emultempl/pe.em -@@ -659,6 +659,9 @@ set_entry_point (void) - } - - lang_default_entry (entry); -+ -+ if (bfd_link_executable (&link_info) && ! entry_from_cmdline) -+ ldlang_add_undef (entry, false); - } - - static void -diff --git a/ld/emultempl/pep.em b/ld/emultempl/pep.em -index 2a3fd0e6ea8..ca4acaea148 100644 ---- a/ld/emultempl/pep.em -+++ b/ld/emultempl/pep.em -@@ -631,6 +631,9 @@ set_entry_point (void) - } - - lang_default_entry (entry); -+ -+ if (bfd_link_executable (&link_info) && ! entry_from_cmdline) -+ ldlang_add_undef (entry, false); - } - - static void --- -2.31.1 - diff --git a/util/crossgcc/patches/binutils-2.40_as-ipxe.patch b/util/crossgcc/patches/binutils-2.41_as-ipxe.patch similarity index 77% rename from util/crossgcc/patches/binutils-2.40_as-ipxe.patch rename to util/crossgcc/patches/binutils-2.41_as-ipxe.patch index 4d2c00a..fb15cce 100644 --- a/util/crossgcc/patches/binutils-2.40_as-ipxe.patch +++ b/util/crossgcc/patches/binutils-2.41_as-ipxe.patch @@ -13,17 +13,15 @@ index 728811bc..78b4802c 100644 --- a/gas/as.c +++ b/gas/as.c -@@ -1203,7 +1203,7 @@ main (int argc, char ** argv) - { +@@ -1364,13 +1364,14 @@ main (int argc, char ** argv) char ** argv_orig = argv; struct stat sob; -- -+ const char *dev_null_file="/dev/null"; - int macro_strip_at; - start_time = get_run_time (); -@@ -1252,7 +1252,7 @@ main (int argc, char ** argv) - so that switches like --hash-size can be honored. */ ++ const char *dev_null_file="/dev/null"; + gas_early_init (&argc, &argv); + + /* Call parse_args before gas_init so that switches like + --hash-size can be honored. */ parse_args (&argc, &argv); - if (argc > 1 && stat (out_file_name, &sob) == 0) diff --git a/util/crossgcc/patches/binutils-2.40_no-makeinfo.patch b/util/crossgcc/patches/binutils-2.41_no-makeinfo.patch similarity index 71% rename from util/crossgcc/patches/binutils-2.40_no-makeinfo.patch rename to util/crossgcc/patches/binutils-2.41_no-makeinfo.patch index e37073f..c43ab0e 100644 --- a/util/crossgcc/patches/binutils-2.40_no-makeinfo.patch +++ b/util/crossgcc/patches/binutils-2.41_no-makeinfo.patch @@ -11,8 +11,8 @@ <http://www.gnu.org/software/make/> make[4]: *** [Makefile:507: as.info] Error 127 Current patch will change that to "MAKEINFO = true" -diff -ur binutils-2.40.orig/bfd/Makefile.in binutils-2.40/bfd/Makefile.in ---- binutils-2.40.orig/bfd/Makefile.in 2022-08-05 11:53:59.000000000 +0200 +diff -ur binutils-2.41.orig/bfd/Makefile.in binutils-2.40/bfd/Makefile.in +--- binutils-2.41.orig/bfd/Makefile.in 2022-08-05 11:53:59.000000000 +0200 +++ binutils-2.40/bfd/Makefile.in 2022-08-20 05:46:39.960039957 +0200 @@ -379,7 +379,7 @@ LN_S = @LN_S@ @@ -23,8 +23,8 @@ MKDIR_P = @MKDIR_P@ MKINSTALLDIRS = @MKINSTALLDIRS@ MSGFMT = @MSGFMT@ -diff -ur binutils-2.40.orig/binutils/Makefile.in binutils-2.40/binutils/Makefile.in ---- binutils-2.40.orig/binutils/Makefile.in 2022-08-05 11:56:21.000000000 +0200 +diff -ur binutils-2.41.orig/binutils/Makefile.in binutils-2.40/binutils/Makefile.in +--- binutils-2.41.orig/binutils/Makefile.in 2022-08-05 11:56:21.000000000 +0200 +++ binutils-2.40/binutils/Makefile.in 2022-08-20 05:46:38.563035937 +0200 @@ -532,7 +532,7 @@ LTLIBICONV = @LTLIBICONV@ @@ -35,8 +35,8 @@ MKDIR_P = @MKDIR_P@ MKINSTALLDIRS = @MKINSTALLDIRS@ MSGFMT = @MSGFMT@ -diff -ur binutils-2.40.orig/etc/Makefile.in binutils-2.40/etc/Makefile.in ---- binutils-2.40.orig/etc/Makefile.in 2022-07-08 11:46:47.000000000 +0200 +diff -ur binutils-2.41.orig/etc/Makefile.in binutils-2.40/etc/Makefile.in +--- binutils-2.41.orig/etc/Makefile.in 2022-07-08 11:46:47.000000000 +0200 +++ binutils-2.40/etc/Makefile.in 2022-08-20 05:46:38.525035827 +0200 @@ -154,7 +154,7 @@ LIBS = @LIBS@ @@ -47,8 +47,8 @@ MKDIR_P = @MKDIR_P@ PACKAGE = @PACKAGE@ PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ -diff -ur binutils-2.40.orig/gas/Makefile.in binutils-2.40/gas/Makefile.in ---- binutils-2.40.orig/gas/Makefile.in 2022-08-05 11:55:17.000000000 +0200 +diff -ur binutils-2.41.orig/gas/Makefile.in binutils-2.40/gas/Makefile.in +--- binutils-2.41.orig/gas/Makefile.in 2022-08-05 11:55:17.000000000 +0200 +++ binutils-2.40/gas/Makefile.in 2022-08-20 05:46:38.535035856 +0200 @@ -408,7 +408,7 @@ LN_S = @LN_S@ @@ -59,8 +59,8 @@ MKDIR_P = @MKDIR_P@ MKINSTALLDIRS = @MKINSTALLDIRS@ MSGFMT = @MSGFMT@ -diff -ur binutils-2.40.orig/gold/Makefile.in binutils-2.40/gold/Makefile.in ---- binutils-2.40.orig/gold/Makefile.in 2022-07-08 11:58:08.000000000 +0200 +diff -ur binutils-2.41.orig/gold/Makefile.in binutils-2.40/gold/Makefile.in +--- binutils-2.41.orig/gold/Makefile.in 2022-07-08 11:58:08.000000000 +0200 +++ binutils-2.40/gold/Makefile.in 2022-08-20 05:46:38.522035819 +0200 @@ -558,7 +558,7 @@ LN_S = @LN_S@ @@ -71,8 +71,8 @@ MERGE_CONSTANTS_FLAG = @MERGE_CONSTANTS_FLAG@ MKDIR_P = @MKDIR_P@ MKINSTALLDIRS = @MKINSTALLDIRS@ -diff -ur binutils-2.40.orig/gold/testsuite/Makefile.in binutils-2.40/gold/testsuite/Makefile.in ---- binutils-2.40.orig/gold/testsuite/Makefile.in 2022-07-08 11:58:08.000000000 +0200 +diff -ur binutils-2.41.orig/gold/testsuite/Makefile.in binutils-2.40/gold/testsuite/Makefile.in +--- binutils-2.41.orig/gold/testsuite/Makefile.in 2022-07-08 11:58:08.000000000 +0200 +++ binutils-2.40/gold/testsuite/Makefile.in 2022-08-20 05:46:38.524035824 +0200 @@ -2644,7 +2644,7 @@ LN_S = @LN_S@ @@ -83,8 +83,8 @@ MERGE_CONSTANTS_FLAG = @MERGE_CONSTANTS_FLAG@ MKDIR_P = @MKDIR_P@ MKINSTALLDIRS = @MKINSTALLDIRS@ -diff -ur binutils-2.40.orig/gprof/Makefile.in binutils-2.40/gprof/Makefile.in ---- binutils-2.40.orig/gprof/Makefile.in 2022-08-05 11:59:11.000000000 +0200 +diff -ur binutils-2.41.orig/gprof/Makefile.in binutils-2.40/gprof/Makefile.in +--- binutils-2.41.orig/gprof/Makefile.in 2022-08-05 11:59:11.000000000 +0200 +++ binutils-2.40/gprof/Makefile.in 2022-08-20 05:46:39.964039969 +0200 @@ -351,7 +351,7 @@ LN_S = @LN_S@ @@ -95,8 +95,8 @@ MKDIR_P = @MKDIR_P@ MKINSTALLDIRS = @MKINSTALLDIRS@ MSGFMT = @MSGFMT@ -diff -ur binutils-2.40.orig/gprofng/doc/Makefile.in binutils-2.40/gprofng/doc/Makefile.in ---- binutils-2.40.orig/gprofng/doc/Makefile.in 2022-08-05 11:59:31.000000000 +0200 +diff -ur binutils-2.41.orig/gprofng/doc/Makefile.in binutils-2.40/gprofng/doc/Makefile.in +--- binutils-2.41.orig/gprofng/doc/Makefile.in 2022-08-05 11:59:31.000000000 +0200 +++ binutils-2.40/gprofng/doc/Makefile.in 2022-08-20 05:46:39.252037920 +0200 @@ -271,7 +271,7 @@ LN_S = @LN_S@ @@ -107,8 +107,8 @@ MKDIR_P = @MKDIR_P@ NM = @NM@ NMEDIT = @NMEDIT@ -diff -ur binutils-2.40.orig/gprofng/gp-display-html/Makefile.in binutils-2.40/gprofng/gp-display-html/Makefile.in ---- binutils-2.40.orig/gprofng/gp-display-html/Makefile.in 2022-08-05 11:59:33.000000000 +0200 +diff -ur binutils-2.41.orig/gprofng/gp-display-html/Makefile.in binutils-2.40/gprofng/gp-display-html/Makefile.in +--- binutils-2.41.orig/gprofng/gp-display-html/Makefile.in 2022-08-05 11:59:33.000000000 +0200 +++ binutils-2.40/gprofng/gp-display-html/Makefile.in 2022-08-20 05:46:39.479038573 +0200 @@ -234,7 +234,7 @@ LN_S = @LN_S@ @@ -119,8 +119,8 @@ MKDIR_P = @MKDIR_P@ NM = @NM@ NMEDIT = @NMEDIT@ -diff -ur binutils-2.40.orig/gprofng/libcollector/Makefile.in binutils-2.40/gprofng/libcollector/Makefile.in ---- binutils-2.40.orig/gprofng/libcollector/Makefile.in 2022-08-05 11:59:38.000000000 +0200 +diff -ur binutils-2.41.orig/gprofng/libcollector/Makefile.in binutils-2.40/gprofng/libcollector/Makefile.in +--- binutils-2.41.orig/gprofng/libcollector/Makefile.in 2022-08-05 11:59:38.000000000 +0200 +++ binutils-2.40/gprofng/libcollector/Makefile.in 2022-08-20 05:46:38.965037094 +0200 @@ -341,7 +341,7 @@ LN_S = @LN_S@ @@ -131,8 +131,8 @@ MKDIR_P = @MKDIR_P@ NM = @NM@ NMEDIT = @NMEDIT@ -diff -ur binutils-2.40.orig/gprofng/Makefile.in binutils-2.40/gprofng/Makefile.in ---- binutils-2.40.orig/gprofng/Makefile.in 2022-08-05 11:59:30.000000000 +0200 +diff -ur binutils-2.41.orig/gprofng/Makefile.in binutils-2.40/gprofng/Makefile.in +--- binutils-2.41.orig/gprofng/Makefile.in 2022-08-05 11:59:30.000000000 +0200 +++ binutils-2.40/gprofng/Makefile.in 2022-08-20 05:46:38.574035968 +0200 @@ -289,7 +289,7 @@ LN_S = @LN_S@ @@ -143,8 +143,8 @@ MKDIR_P = @MKDIR_P@ NM = @NM@ NMEDIT = @NMEDIT@ -diff -ur binutils-2.40.orig/gprofng/src/Makefile.in binutils-2.40/gprofng/src/Makefile.in ---- binutils-2.40.orig/gprofng/src/Makefile.in 2022-08-05 11:59:34.000000000 +0200 +diff -ur binutils-2.41.orig/gprofng/src/Makefile.in binutils-2.40/gprofng/src/Makefile.in +--- binutils-2.41.orig/gprofng/src/Makefile.in 2022-08-05 11:59:34.000000000 +0200 +++ binutils-2.40/gprofng/src/Makefile.in 2022-08-20 05:46:38.573035965 +0200 @@ -358,7 +358,7 @@ LN_S = @LN_S@ @@ -155,8 +155,8 @@ MKDIR_P = @MKDIR_P@ NM = @NM@ NMEDIT = @NMEDIT@ -diff -ur binutils-2.40.orig/ld/Makefile.in binutils-2.40/ld/Makefile.in ---- binutils-2.40.orig/ld/Makefile.in 2022-08-05 11:56:53.000000000 +0200 +diff -ur binutils-2.41.orig/ld/Makefile.in binutils-2.40/ld/Makefile.in +--- binutils-2.41.orig/ld/Makefile.in 2022-08-05 11:56:53.000000000 +0200 +++ binutils-2.40/ld/Makefile.in 2022-08-20 05:46:38.536035859 +0200 @@ -432,7 +432,7 @@ LN_S = @LN_S@ @@ -167,8 +167,8 @@ MKDIR_P = @MKDIR_P@ MKINSTALLDIRS = @MKINSTALLDIRS@ MSGFMT = @MSGFMT@ -diff -ur binutils-2.40.orig/libctf/Makefile.in binutils-2.40/libctf/Makefile.in ---- binutils-2.40.orig/libctf/Makefile.in 2022-07-08 12:02:15.000000000 +0200 +diff -ur binutils-2.41.orig/libctf/Makefile.in binutils-2.40/libctf/Makefile.in +--- binutils-2.41.orig/libctf/Makefile.in 2022-07-08 12:02:15.000000000 +0200 +++ binutils-2.40/libctf/Makefile.in 2022-08-20 05:46:39.771039414 +0200 @@ -425,7 +425,7 @@ LN_S = @LN_S@ @@ -179,8 +179,8 @@ MKDIR_P = @MKDIR_P@ NM = @NM@ NMEDIT = @NMEDIT@ -diff -ur binutils-2.40.orig/libiberty/Makefile.in binutils-2.40/libiberty/Makefile.in ---- binutils-2.40.orig/libiberty/Makefile.in 2022-07-08 11:46:48.000000000 +0200 +diff -ur binutils-2.41.orig/libiberty/Makefile.in binutils-2.40/libiberty/Makefile.in +--- binutils-2.41.orig/libiberty/Makefile.in 2022-07-08 11:46:48.000000000 +0200 +++ binutils-2.40/libiberty/Makefile.in 2022-08-20 05:46:39.961039960 +0200 @@ -57,7 +57,7 @@ CFLAGS = @CFLAGS@ @@ -191,8 +191,8 @@ PERL = @PERL@ PICFLAG = @PICFLAG@ -diff -ur binutils-2.40.orig/Makefile.in binutils-2.40/Makefile.in ---- binutils-2.40.orig/Makefile.in 2022-08-05 13:00:56.000000000 +0200 +diff -ur binutils-2.41.orig/Makefile.in binutils-2.40/Makefile.in +--- binutils-2.41.orig/Makefile.in 2022-08-05 13:00:56.000000000 +0200 +++ binutils-2.40/Makefile.in 2022-08-20 05:46:38.549035896 +0200 @@ -399,7 +399,7 @@ FLEX = @FLEX@ @@ -203,8 +203,8 @@ EXPECT = @EXPECT@ RUNTEST = @RUNTEST@ -diff -ur binutils-2.40.orig/Makefile.tpl binutils-2.40/Makefile.tpl ---- binutils-2.40.orig/Makefile.tpl 2022-07-08 11:46:47.000000000 +0200 +diff -ur binutils-2.41.orig/Makefile.tpl binutils-2.40/Makefile.tpl +--- binutils-2.41.orig/Makefile.tpl 2022-07-08 11:46:47.000000000 +0200 +++ binutils-2.40/Makefile.tpl 2022-08-20 05:46:38.535035856 +0200 @@ -402,7 +402,7 @@ FLEX = @FLEX@ @@ -215,8 +215,8 @@ EXPECT = @EXPECT@ RUNTEST = @RUNTEST@ -diff -ur binutils-2.40.orig/opcodes/Makefile.in binutils-2.40/opcodes/Makefile.in ---- binutils-2.40.orig/opcodes/Makefile.in 2022-08-05 11:54:59.000000000 +0200 +diff -ur binutils-2.41.orig/opcodes/Makefile.in binutils-2.40/opcodes/Makefile.in +--- binutils-2.41.orig/opcodes/Makefile.in 2022-08-05 11:54:59.000000000 +0200 +++ binutils-2.40/opcodes/Makefile.in 2022-08-20 05:46:38.522035819 +0200 @@ -324,7 +324,7 @@ LN_S = @LN_S@ @@ -227,8 +227,8 @@ MKDIR_P = @MKDIR_P@ MKINSTALLDIRS = @MKINSTALLDIRS@ MSGFMT = @MSGFMT@ -diff -ur binutils-2.40.orig/zlib/Makefile.in binutils-2.40/zlib/Makefile.in ---- binutils-2.40.orig/zlib/Makefile.in 2022-07-08 11:56:28.000000000 +0200 +diff -ur binutils-2.41.orig/zlib/Makefile.in binutils-2.40/zlib/Makefile.in +--- binutils-2.41.orig/zlib/Makefile.in 2022-07-08 11:56:28.000000000 +0200 +++ binutils-2.40/zlib/Makefile.in 2022-08-20 05:46:38.571035960 +0200 @@ -321,7 +321,7 @@ LN_S = @LN_S@ diff --git a/util/crossgcc/sum/binutils-2.40.tar.xz.cksum b/util/crossgcc/sum/binutils-2.40.tar.xz.cksum deleted file mode 100644 index 4597a72..0000000 --- a/util/crossgcc/sum/binutils-2.40.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -fee4fbef9d632afc1988dd631d7f75d4394b7f8d tarballs/binutils-2.40.tar.xz diff --git a/util/crossgcc/sum/binutils-2.41.tar.xz.cksum b/util/crossgcc/sum/binutils-2.41.tar.xz.cksum new file mode 100644 index 0000000..84bb8fa --- /dev/null +++ b/util/crossgcc/sum/binutils-2.41.tar.xz.cksum @@ -0,0 +1 @@ +0e008260a958bbd10182ee3384672ae0a310eece tarballs/binutils-2.41.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/76852?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c985974e2eeea1329b2dbb232711c72b0bd99bc Gerrit-Change-Number: 76852 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: util/crossgcc: Update GMP from 6.2.1 to 6.3.0
by Elyes Haouas (Code Review) 31 Aug '23

31 Aug '23

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76865?usp=email ) Change subject: util/crossgcc: Update GMP from 6.2.1 to 6.3.0 ...................................................................... util/crossgcc: Update GMP from 6.2.1 to 6.3.0 Change-Id: I67d443cb15d89482b20b01f4068502b16ac8fc8e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76865 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M Documentation/releases/coreboot-4.22-relnotes.md M util/crossgcc/buildgcc R util/crossgcc/patches/gmp-6.3.0_generic-build.patch D util/crossgcc/sum/gmp-6.2.1.tar.xz.cksum A util/crossgcc/sum/gmp-6.3.0.tar.xz.cksum 5 files changed, 3 insertions(+), 3 deletions(-) Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified diff --git a/Documentation/releases/coreboot-4.22-relnotes.md b/Documentation/releases/coreboot-4.22-relnotes.md index 025eaf8..d7013b2 100644 --- a/Documentation/releases/coreboot-4.22-relnotes.md +++ b/Documentation/releases/coreboot-4.22-relnotes.md @@ -21,7 +21,7 @@ ### Toolchain updates -* To be filled in immediately before the release by the release team +* Upgrade GMP from 6.2.1 to 6.3.0 ### Additional coreboot changes diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 1abb4a9..033aac0 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -35,7 +35,7 @@ COREBOOT_MIRROR_URL="https://www.coreboot.org/releases/crossgcc-sources" # GCC toolchain version numbers -GMP_VERSION=6.2.1 +GMP_VERSION=6.3.0 MPFR_VERSION=4.2.0 MPC_VERSION=1.3.1 GCC_VERSION=11.4.0 diff --git a/util/crossgcc/patches/gmp-6.2.1_generic-build.patch b/util/crossgcc/patches/gmp-6.3.0_generic-build.patch similarity index 100% rename from util/crossgcc/patches/gmp-6.2.1_generic-build.patch rename to util/crossgcc/patches/gmp-6.3.0_generic-build.patch diff --git a/util/crossgcc/sum/gmp-6.2.1.tar.xz.cksum b/util/crossgcc/sum/gmp-6.2.1.tar.xz.cksum deleted file mode 100644 index 3ea4232..0000000 --- a/util/crossgcc/sum/gmp-6.2.1.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -0578d48607ec0e272177d175fd1807c30b00fdf2 tarballs/gmp-6.2.1.tar.xz diff --git a/util/crossgcc/sum/gmp-6.3.0.tar.xz.cksum b/util/crossgcc/sum/gmp-6.3.0.tar.xz.cksum new file mode 100644 index 0000000..56abf27 --- /dev/null +++ b/util/crossgcc/sum/gmp-6.3.0.tar.xz.cksum @@ -0,0 +1 @@ +b4043dd2964ab1a858109da85c44de224384f352 tarballs/gmp-6.3.0.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/76865?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67d443cb15d89482b20b01f4068502b16ac8fc8e Gerrit-Change-Number: 76865 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: Update amd_blobs submodule to upstream main
by Karthik Ramasubramanian (Code Review) 31 Aug '23

31 Aug '23

Attention is currently required from: Felix Singer, Martin L Roth. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77541?usp=email ) Change subject: Update amd_blobs submodule to upstream main ...................................................................... Patch Set 3: (1 comment) File 3rdparty/amd_blobs: https://review.coreboot.org/c/coreboot/+/77541/comment/b7c470d0_c71e60a3 : PS3, Line 1: 1cd6ea5cc5c22d3f4e439652ede85d21488232e4 This is not matching "to commit id 591d5fb:" in the commit message. Actually it is matching the "from commit id". -- To view, visit https://review.coreboot.org/c/coreboot/+/77541?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebb8334a4ca89745dfbeedf6d3e72a1b9d74d708 Gerrit-Change-Number: 77541 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 31 Aug 2023 16:03:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: drivers/intel/fsp2_0: Introduce early MRC cache store
by Subrata Banik (Code Review) 31 Aug '23

31 Aug '23

Attention is currently required from: Andrey Petrov, Felix Held, Fred Reitberger, Jason Glenesk, Kapil Porwal, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nico Huber, Paul Menzel, Raul Rangel. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77556?usp=email ) Change subject: drivers/intel/fsp2_0: Introduce early MRC cache store ...................................................................... Patch Set 3: (3 comments) File src/drivers/mrc_cache/Kconfig: https://review.coreboot.org/c/coreboot/+/77556/comment/dbbb6812_3ea6cdbe : PS2, Line 24: MRC_STASH_TO_CBMEM > > are you suggesting to keep MRC_WRITE_NV_LATE and MRC_STASH_TO_CBMEM ? or saying rename MRC_STASH_T […] Acknowledged https://review.coreboot.org/c/coreboot/+/77556/comment/40ee41d6_8dbf7612 : PS2, Line 35: boot : states > seems a bit unclear as written, so I was suggesting to drop "boot states" so it reads: ... […] Acknowledged File src/drivers/mrc_cache/mrc_cache.c: https://review.coreboot.org/c/coreboot/+/77556/comment/123dd2a2_a4c2c7fb : PS1, Line 742: BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_ENTRY, finalize_mrc_cache, NULL); > > > > This changes the order for devices with MRC_STASH_TO_CBMEM but without > > > > MRC_WRITE_NV_LATE, e.g. those with BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES. > > > > > > > > It's theoretically possible that this breaks. For instance, when the SPI > > > > flash is locked between enumerate/on_exit and resume_check/on_entry. So > > > > that would need extensive review or testing. > > > > > > > > > So far we have three different ways to store the MRC cache below and different SoC vendors select the applicable config as per the platform need. > > > > > > w/o this CL: > > > ``` > > > 1. NV Write late (AMD)- > > > > > > save_mrc_data - BS_PRE_DEVICE_ENTRY > > > finalize_mrc_cache - BS_OS_RESUME_CHECK_ENTRY > > > lock - BS_OS_RESUME_CHECK_EXIT > > > > > > > > > 2. MRC_STASH_TO_CBMEM aka w/ BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES (BSW, BYT) > > > > > > save_mrc_data - BS_PRE_DEVICE_ENTRY > > > finalize_mrc_cache - BS_DEV_ENUMERATE_EXIT > > > lock - BS_DEV_RESOURCES_ENTRY > > > > > > 3. SAVE_MRC_AFTER_FSPS (XEON-SP) > > > > > > save_mrc_data - BS_DEV_INIT_CHIPS_EXIT > > > finalize_mrc_cache - BS_DEV_ENUMERATE_EXIT > > > lock - BS_DEV_RESOURCES_ENTRY > > > ``` > > > > These are just three special cases that defer the writing into > > ramstage. Currently also FSP 2.0 platforms do it in ramstage and > > there are many more that currently do it in romstage. > > > > > > > > w/ this cl: > > > > > > > > > simplified using 2-ways to store the MRC cache below and how it can meet all the needs. > > > > > > ``` > > > 1. NV Write late/SAVE_MRC_AFTER_FSPS -> MRC_STASH_TO_CBMEM (also for BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES) (AMD, XEON_SP, BSW and BYT) > > > > > > save_mrc_data - BS_DEV_INIT_CHIPS_EXIT > > > finalize_mrc_cache - BS_OS_RESUME_CHECK_ENTRY > > > lock - BS_OS_RESUME_CHECK_EXIT > > > > > > > > > 2. MRC cache early (INTEL) > > > > > > save_mrc_data - post FSP-M > > > finalize_mrc_cache - BS_DEV_ENUMERATE_EXIT > > > lock - BS_DEV_RESOURCES_ENTRY > > > > > > In summary, > > > - the order of the execution still remains the same (w/ and w/o this CL) between saving_mrc_cache later finalizes the mrc cache and finally locking the boot media. > > > > > > - I don't see any scenario where the we are attempting to write into the SPI but it's getting locked as you have highlighted (when the SPI flash is locked between enumerate/on_exit and resume_check/on_entry) > > > ``` > > > > I agree to have only two paths. 1. that defers the write to ramstage, > > and 2. that does it directly in romstage. However, changing the > > boot-state hooks in ramstage--when the write is exactly done--requires > > more careful evaluation. > > > > So how about we don't change the boot-state hooks too much right now, > > and focus on the code paths? > > > > This could roughly happen in the following order: > > * Make the changes of CB:67669 optional (adding an interim Kconfig for this) > > * Could happen in parallel: > > - Let SAVE_MRC_AFTER_FSPS use MRC_STASH_TO_CBMEM instead of the `save_mrc_data.c` path > > - Let other FSP2.0 platforms directly write in romstage > > You beat me on this. I'm about to propose this. Lets SAVE_MRC_AFTER_FSPS and MRC_STASH_TO_CBMEM use the same boot states except I need to save mrc_cache a little late (after FSP-S exit) to unify both paths. > > > > * Remove `save_mrc_data.c` path > > I'm sure if we can remove this file otherwise i need to copy the save_mrc_cache API into memory_init.c file. And call it from there. may be keep this file as is bt include if MRC_CACHE_EARLY ? > > > > > Then only two major code paths would be left (if I didn't miss any): > > One with and one without MRC_STASH_TO_CBMEM. Then we could still look > > into unifying the boot-state hooks. > > > > > Btw. I don't see the Intel/AMD distinction that you seem to imply. > > Most AMD platforms seem to simply follow the default FSP2.0 code path. > > Agree but I don't know why AMD platform would like to finalize_mrc_cache that late like BS_OS_RESUME_CHECK_ENTRY. hence, we ended up keeping both MRC_STASH_TO_CBMEM and MRC_CACHE_LATE Please take a look at the latest patchset -- To view, visit https://review.coreboot.org/c/coreboot/+/77556?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1e91d25916594f59d1e467a142f5042c6138b51 Gerrit-Change-Number: 77556 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 31 Aug 2023 16:02:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config
by Subrata Banik (Code Review) 31 Aug '23

31 Aug '23

Attention is currently required from: Andrey Petrov, Arthur Heymans, Christian Walter, Johnny Lin, Kapil Porwal, Lean Sheng Tan, Martin L Roth, Nill Ge, Reka Norman, Shuo Liu, TangYiwei, Tim Chu. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77557?usp=email ) Change subject: soc/intel/xeon_sp: Use MRC_STASH_TO_CBMEM config ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > > > The problem of seeing "SPI Transaction Timeout" at BS_DEV_RESOURCES is not related to your cls, but with your cls because it's moved to a later stage after BS_DEV_RESOURCES, then it cannot write MRC data. > > > > > > I still resolve this comment, just providing some test results for thoughts. > > > > @Johnny, can you please help me to debug this issue on AC by commenting below code and share if u r still seeing the timeout issue. I'm suspecting the SPI is getting locked is the reason for this problem > > > > ``` > > BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config, > > NULL); > > > > BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, lock, NULL); > > ``` > > As per my understanding the issue is coming because of applying the BIOS Decode lock so early in the boot > > ``` > void spi_lockdown_config(int chipset_lockdown) > { > if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { > fast_spi_set_bde(); > fast_spi_set_vcl(); > } > } > ``` > > can you please check by commenting on this function ? alternatively we shall call BDE and VCL from soc_finalize() ? @Jonny, can you please pick the updated patch train and share your feedback? -- To view, visit https://review.coreboot.org/c/coreboot/+/77557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6275fbc0546468f36baee73691a285092e857e0a Gerrit-Change-Number: 77557 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 31 Aug 2023 16:01:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/amd/onyx: Add FMD file and update romsize
by Felix Held (Code Review) 31 Aug '23

31 Aug '23

Attention is currently required from: Arthur Heymans, Martin L Roth, Varshit Pandya. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76497?usp=email ) Change subject: mb/amd/onyx: Add FMD file and update romsize ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: adding this part of the next patch to this patch will likely solve the build failure: ifeq ($(call int-gt, $(CONFIG_ROM_SIZE) 0x1000000), 1) CBFSTOOL_ADD_CMD_OPTIONS+= --mmap 0:0xff000000:0x1000000 endif -- To view, visit https://review.coreboot.org/c/coreboot/+/76497?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd6f711f5ca5c8a421c0c38edd404b1900bb29b4 Gerrit-Change-Number: 76497 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 31 Aug 2023 16:00:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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