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Change subject: mb/inventec: Add Intel SPR server board Inventec Transformers
......................................................................
Patch Set 8: Code-Review+2
(8 comments)
Patchset:
PS5:
> Hi Felix, […]
I'm sorry for coming back to this late. I just wanted to say here that I am absolutely fine with having this as a separate mainboard. I didn't mean to kick off a huge discussion. Not at all.
I proposed the idea for two reasons:
* I am not really into OCP, so I don't know how much the mainboards under the OCP users differ. I just saw this mainboard code and many parts are similar to the CRB one. So I thought other OCP mainbaords might be similar as well and you all could take advantage of a common base / common mainboard, which wasn't even meant to be done now. However, it was just an idea how you could take much more advantage of open source.
* Sometimes it happens that we do treewide changes to unify or clean up things. The more mainboards we have in the tree, the more work someone needs to put into it. With the variant concept, it might be possible to reduce the work for the upstream developers. Though, as I said before, it's a case-by-case thing and it's totally fine to separate mainboards.
However, thanks a lot for your contribution and for putting in the effort!
Patchset:
PS8:
Just a couple of nits and a question about some methods, which are confusing to me. Otherwise it looks good to me!
File src/mainboard/inventec/transformers/Kconfig:
https://review.coreboot.org/c/coreboot/+/75598/comment/b5130645_c9f225de :
PS8, Line 24: string
Please remove, no need to to redefine the type
https://review.coreboot.org/c/coreboot/+/75598/comment/82c2c9bc_a09e6bff :
PS8, Line 28: string
same here
https://review.coreboot.org/c/coreboot/+/75598/comment/ec185198_e8a7000c :
PS8, Line 32: string
same
https://review.coreboot.org/c/coreboot/+/75598/comment/65455655_fab5e7c5 :
PS8, Line 36: int
same
File src/mainboard/inventec/transformers/devicetree.cb:
PS8:
Please use tabs instead of spaces in lines 9-11 and 25-39. Also, if a device does not have config options in its scope, then please move the end keyword into the same line.
File src/mainboard/inventec/transformers/ramstage.c:
https://review.coreboot.org/c/coreboot/+/75598/comment/b2abc913_52f99eca :
PS8, Line 10: #define SLOT_ID_LEN 2
: static char slot_id_str[SLOT_ID_LEN];
: extern uint32_t heci_fw_sts(void);
: extern uint32_t heci_cse_normal(void);
: extern uint32_t heci_cse_done(void);
:
: //extern void cse_init(uintptr_t tempbar);
:
I just noticed these declarations. Are they needed? As far as I can see, only Apollo Lake uses these.
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Change subject: mb/inventec: Add Intel SPR server board Inventec Transformers
......................................................................
Patch Set 8:
(4 comments)
File src/mainboard/inventec/transformers/bootblock.c:
https://review.coreboot.org/c/coreboot/+/75598/comment/21e1879c_c328ffc1 :
PS5, Line 23: * For ArcherCity CRB, only SUART1 is used.
> This seems copy-pasted.
Yeah, parts will be factored out (same with CB:75722).
File src/mainboard/inventec/transformers/romstage.c:
https://review.coreboot.org/c/coreboot/+/75598/comment/61cd28f1_18e4d14f :
PS5, Line 102: selftest result first */
> Please align the line correctly.
Done
https://review.coreboot.org/c/coreboot/+/75598/comment/587e0557_bfab73cc :
PS5, Line 118: /* Enable - Portions of memory reference code will be skipped */
: /* when possible to increase boot speed on warm boots.*/
: /* Disable - Disables this feature. */
: /* Auto - Sets it to the MRC default setting. */
> Please use the multi-line commenting style listed in the coding style.
Done
https://review.coreboot.org/c/coreboot/+/75598/comment/b94ec765_46eabf7a :
PS5, Line 142: /* Disable FSP memory train results*/
> Please add a space at the end.
Done
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Change subject: mb/inventec: Add Intel SPR server board Inventec Transformers
......................................................................
mb/inventec: Add Intel SPR server board Inventec Transformers
CPU:
- 2 SPR sockets
- 64 total PCIe 5.0 lanes with up to 64 lanes of Flex Bus/CXL per CPU
- Up to 32 DDR5 DIMM
- 1 Gbase-T NIC port
- 1 USB3.0 type A, 1 USB2.0 connector
- 1 VGA connector
BMC:
- ASPEED AST2600 BMC
- 1 DDR4 8Gb memory
- 1 8GB eMMC
Test:
The board boots to Linux 4.19.6 with all 192 cores available.
Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684
Signed-off-by: Annie Chen <Chen.AnnieET(a)inventec.com>
---
A configs/builder/config.transformers
A src/mainboard/inventec/Kconfig
A src/mainboard/inventec/Kconfig.name
A src/mainboard/inventec/transformers/Kconfig
A src/mainboard/inventec/transformers/Kconfig.name
A src/mainboard/inventec/transformers/Makefile.inc
A src/mainboard/inventec/transformers/acpi/platform.asl
A src/mainboard/inventec/transformers/board.fmd
A src/mainboard/inventec/transformers/board_info.txt
A src/mainboard/inventec/transformers/bootblock.c
A src/mainboard/inventec/transformers/devicetree.cb
A src/mainboard/inventec/transformers/dsdt.asl
A src/mainboard/inventec/transformers/include/mainboard_ras.h
A src/mainboard/inventec/transformers/include/sprsp_ac_iio.h
A src/mainboard/inventec/transformers/include/sprsp_gpio.h
A src/mainboard/inventec/transformers/ipmi.c
A src/mainboard/inventec/transformers/ipmi.h
A src/mainboard/inventec/transformers/ramstage.c
A src/mainboard/inventec/transformers/romstage.c
19 files changed, 944 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/75598/8
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Change subject: mb/google/rex/var/rex0: Change touch over spi interrupt trigger to edge
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Set Ready For Review
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Change subject: sb/intel/lynxpoint: Don't generate second SSDT
......................................................................
Patch Set 7: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76129/comment/6970cb6e_57a31966 :
PS7, Line 9: is need
missing word: **no** need
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Change subject: acpi: Move HPET generation to a common location
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76128/comment/6f4647f0_20933f31 :
PS6, Line 9: to
that "to" sounds not right here.
https://review.coreboot.org/c/coreboot/+/76128/comment/271a8ed9_746e1604 :
PS6, Line 12: suffices
typo: sufficient?
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Change subject: acpi: Move HPET generation to a common location
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