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Change subject: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c:
https://review.coreboot.org/c/coreboot/+/76175/comment/9aec8df9_c974890e :
PS3, Line 43: (0x00 << 16), (0x5a << 16)
Nit: are the parens necessary there?
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Change subject: mb/siemens/mc_apl1: Rename macro 'TX_DWORD3' to 'TX_DWORD3_P1'
......................................................................
Patch Set 3: Code-Review+2
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Change subject: mb/siemens/{mc_apl3,mc_apl5,mc_apl6}: Remove TX_DWORD3 macro
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/siemens/{mc_apl3,mc_apl5,mc_apl6}: Remove TX_DWORD3 macro
......................................................................
mb/siemens/{mc_apl3,mc_apl5,mc_apl6}: Remove TX_DWORD3 macro
A correction of Tx signal from SATA interface is not necessary on these
boards currently. Therefore remove the define and the corresponding code
on mc_apl5.
Change-Id: I5092ee128cb35e126069d18bb3cbd635e01bbcdb
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
3 files changed, 0 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/76173/2
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Change subject: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76175/comment/8e4f6949_fea4d65c :
PS1, Line 11: appropriate value
> _ of 0. […]
Done
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Change subject: mb/siemens/mc_apl1: Rename macro 'TX_DWORD3' to 'TX_DWORD3_P1'
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76174/comment/a38709a5_3d4dda37 :
PS1, Line 7: Change define name from 'TX_DWORD3' to 'TX_DWORD3_P1'
> Change name → Rename […]
Done
https://review.coreboot.org/c/coreboot/+/76174/comment/2cb132f8_1d3d5e49 :
PS1, Line 11: §
> Shift key was pressed. […]
Done
Patchset:
PS2:
Hi Paul, thanks for the review.
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Change subject: acpi: Set checksum for SPCR table
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Makes sense, you can either rebase on this one or master, your call.
I need to rebase anyway, but having commit that says it fixes something might make bisect nicer.
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Change subject: acpi: Move HPET generation to a common location
......................................................................
acpi: Move HPET generation to a common location
HPET is usually a feature of the hardware that needs to no runtime to
check whether it is present or it is typically unconditionally enabled.
This means a simple Kconfig option to generate the ACPI tables is
suffices, which allows reduction of boilerplate.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I38b9962a8d568267356256a3edc51348b9417e20
---
M src/acpi/Kconfig
M src/acpi/acpi.c
M src/include/acpi/acpi.h
M src/soc/amd/common/block/acpi/Kconfig
M src/soc/amd/common/block/acpi/Makefile.inc
D src/soc/amd/common/block/acpi/tables.c
M src/soc/amd/common/block/include/amdblocks/acpi.h
M src/soc/amd/common/block/lpc/lpc.c
M src/soc/intel/baytrail/Kconfig
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/braswell/Kconfig
M src/soc/intel/braswell/acpi.c
M src/soc/intel/broadwell/pch/Kconfig
M src/soc/intel/broadwell/pch/lpc.c
M src/soc/intel/common/block/acpi/Kconfig
M src/soc/intel/common/block/acpi/acpi.c
M src/soc/intel/common/block/include/intelblocks/lpc_lib.h
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/acpi.c
M src/southbridge/amd/pi/hudson/Kconfig
M src/southbridge/amd/pi/hudson/lpc.c
M src/southbridge/intel/bd82x6x/Kconfig
M src/southbridge/intel/bd82x6x/lpc.c
M src/southbridge/intel/i82371eb/Kconfig
M src/southbridge/intel/i82371eb/isa.c
M src/southbridge/intel/i82801gx/Kconfig
M src/southbridge/intel/i82801gx/lpc.c
M src/southbridge/intel/i82801ix/Kconfig
M src/southbridge/intel/i82801ix/lpc.c
M src/southbridge/intel/i82801jx/Kconfig
M src/southbridge/intel/i82801jx/lpc.c
M src/southbridge/intel/ibexpeak/Kconfig
M src/southbridge/intel/ibexpeak/lpc.c
M src/southbridge/intel/lynxpoint/Kconfig
M src/southbridge/intel/lynxpoint/lpc.c
35 files changed, 35 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/76128/7
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Change subject: acpi/acpi.c: Move ACPI header creation to a function
......................................................................
acpi/acpi.c: Move ACPI header creation to a function
This reduces boilerplate. One functional difference is that SSDT no
longer has oem_revision set to 42.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Id2e54d61970294e028a61ba86c07c5482784e307
---
M src/acpi/acpi.c
1 file changed, 49 insertions(+), 246 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/76143/3
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Change subject: acpi/acpi.c: Reduce boilerplate
......................................................................
acpi/acpi.c: Reduce boilerplate
Adding tables to R/XSDT, aligning current pointer, computing checksum is
a lot of boilerplate that needs to be done for each table.
TESTED on foxconn/g41.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: If4915b8cdfcfdbb34284ea75fa8a0fd23554152d
---
M src/acpi/acpi.c
1 file changed, 128 insertions(+), 209 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/76127/3
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