coreboot-gerrit June 2023

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[S] Change in coreboot[master]: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0
by Mario Scheithauer (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Werner Zeh. Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76175?usp=email ) Change subject: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0 ...................................................................... mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0 Because of an incorrect transmit voltage swing, the signal must be adjusted. The factor of slices for full swing level can be corrected via the High Speed I/O Transmit Control Register 3. The appropriate value was determined by using an oscilloscope. Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/76175/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c index 1e7fa37..e47965a 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -13,6 +13,8 @@ #include <baseboard/variants.h> #include <types.h> +#define TX_DWORD3_P0 0xc8c + void variant_mainboard_final(void) { struct device *dev = NULL; @@ -32,6 +34,14 @@ */ pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); + /* + * Correct the SATA transmit signal via the High Speed I/O Transmit + * Control Register 3 on SATA port 0. + * Bit [23:16] set the output voltage swing for TX line. + * The value 0x5a sets the swing level to 0.7 V. + */ + pcr_rmw32(PID_MODPHY, TX_DWORD3_P0, (0x00 << 16), (0x5a << 16)); + /* Set Master Enable for on-board PCI device if allowed. */ dev = dev_find_device(PCI_VID_SIEMENS, 0x403e, 0); if (dev) { -- To view, visit https://review.coreboot.org/c/coreboot/+/76175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90 Gerrit-Change-Number: 76175 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/siemens/mc_apl1: Change define name from 'TX_DWORD3' to 'TX_DWORD3...
by Mario Scheithauer (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Werner Zeh. Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76174?usp=email ) Change subject: mb/siemens/mc_apl1: Change define name from 'TX_DWORD3' to 'TX_DWORD3_P1' ...................................................................... mb/siemens/mc_apl1: Change define name from 'TX_DWORD3' to 'TX_DWORD3_P1' The offset '0xa8c' for the High Speed I/O Transmit Control Register 3 refers to SATA port 1 only. To make this clear, change the name of the define from 'TX_DWORD3' to 'TX_DWORD§_P1'. Change-Id: I09d17eeffbe84939297e739586f6b74ed3e2258b Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/76174/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c index c9d4b29..b7b997b 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c @@ -11,7 +11,7 @@ #include <baseboard/variants.h> #include <types.h> -#define TX_DWORD3 0xa8c +#define TX_DWORD3_P1 0xa8c void variant_mainboard_final(void) { @@ -41,11 +41,11 @@ /* * Correct the SATA transmit signal via the High Speed I/O Transmit - * Control Register 3. + * Control Register 3 on SATA port 1. * Bit [23:16] set the output voltage swing for TX line. * The value 0x4a sets the swing level to 0.58 V. */ - pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16)); + pcr_rmw32(PID_MODPHY, TX_DWORD3_P1, (0x00 << 16), (0x4a << 16)); } static void finalize_boot(void *unused) -- To view, visit https://review.coreboot.org/c/coreboot/+/76174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09d17eeffbe84939297e739586f6b74ed3e2258b Gerrit-Change-Number: 76174 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/siemens/{mc_apl3,mc_apl5,mc_apl6}: Remove TX_DWORD3 define
by Mario Scheithauer (Code Review) 29 Jun '23

29 Jun '23

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76173?usp=email ) Change subject: mb/siemens/{mc_apl3,mc_apl5,mc_apl6}: Remove TX_DWORD3 define ...................................................................... mb/siemens/{mc_apl3,mc_apl5,mc_apl6}: Remove TX_DWORD3 define A correction of Tx signal from SATA interface is not necessary on these boards currently. Therefore remove the define and the corresponding code on mc_apl5. Change-Id: I5092ee128cb35e126069d18bb3cbd635e01bbcdb Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c M src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c 3 files changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/76173/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index c17f1be..b61f32d 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -14,8 +14,6 @@ #include <baseboard/variants.h> #include <types.h> -#define TX_DWORD3 0xa8c - void variant_mainboard_final(void) { struct device *dev = NULL; diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c index 7362a48..1e7fa37 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -13,8 +13,6 @@ #include <baseboard/variants.h> #include <types.h> -#define TX_DWORD3 0xa8c - void variant_mainboard_final(void) { struct device *dev = NULL; @@ -34,11 +32,6 @@ */ pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); - /* Correct the SATA transmit signal via the High Speed I/O Transmit Control Register 3. - Bit [23:16] set the output voltage swing for TX line. The value 0x4a sets the swing - level to 0.58 V. */ - pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16)); - /* Set Master Enable for on-board PCI device if allowed. */ dev = dev_find_device(PCI_VID_SIEMENS, 0x403e, 0); if (dev) { diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c index b5aa068..1856a35 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c @@ -14,8 +14,6 @@ #include <baseboard/variants.h> #include <types.h> -#define TX_DWORD3 0xa8c - void variant_mainboard_final(void) { struct device *dev = NULL; -- To view, visit https://review.coreboot.org/c/coreboot/+/76173?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5092ee128cb35e126069d18bb3cbd635e01bbcdb Gerrit-Change-Number: 76173 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/intel/meteorlake: Report CPU clock info
by Subrata Banik (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Felix Singer, Hannah Williams, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Tarun Tuli, Wonkyu Kim. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76124?usp=email ) Change subject: soc/intel/meteorlake: Report CPU clock info ...................................................................... Patch Set 10: (1 comment) Patchset: PS5: > The ramstage print value can be max turbo or other max cpu frequency. > By using default CPU frquency and max turbo(max capable turbo frequency) we can get silicon sku info. my point is what we will gain by this additional information. we shouldn't be caring about non-turbo max freq. -- To view, visit https://review.coreboot.org/c/coreboot/+/76124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b056fb8db04eca345dd7a240d03463de7c59fc2 Gerrit-Change-Number: 76124 Gerrit-PatchSet: 10 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 04:31:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex/var/ovis: Fix mux change as per schematics
by Subrata Banik (Code Review) 29 Jun '23

29 Jun '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76149?usp=email ) Change subject: mb/google/rex/var/ovis: Fix mux change as per schematics ...................................................................... mb/google/rex/var/ovis: Fix mux change as per schematics This patch updates the mux connection to reflect the Ovis schematics dated June to ensure Type-C1 is able to work in DP-ALT mode. BUG=b:289300284 TEST=Able to get display over Type-C1 port. Change-Id: I223eb3a96e6a1b3abb4168fcf59c0df04c1b4498 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/rex/variants/ovis/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/76149/1 diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb index a6d5c04..80a22de 100644 --- a/src/mainboard/google/rex/variants/ovis/overridetree.cb +++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb @@ -203,8 +203,8 @@ device ref soc_espi on chip ec/google/chromeec use conn0 as mux_conn[0] - use conn1 as mux_conn[1] - use conn2 as mux_conn[2] + use conn1 as mux_conn[2] + use conn2 as mux_conn[1] device pnp 0c09.0 on end end end @@ -219,12 +219,12 @@ chip drivers/intel/pmc_mux/conn use usb2_port1 as usb2_port use tcss_usb3_port1 as usb3_port - device generic 1 alias conn1 on end + device generic 2 alias conn1 on end end chip drivers/intel/pmc_mux/conn use usb2_port3 as usb2_port use tcss_usb3_port2 as usb3_port - device generic 2 alias conn2 on end + device generic 1 alias conn2 on end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/76149?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I223eb3a96e6a1b3abb4168fcf59c0df04c1b4498 Gerrit-Change-Number: 76149 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: mb/google/nissa/var/gothrax: Initialise overridetree
by Felix Singer (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Derek Huang, Henry Sun, Tarun Tuli, Yunlong Jia. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76013?usp=email ) Change subject: mb/google/nissa/var/gothrax: Initialise overridetree ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/gothrax/overridetree.cb: https://review.coreboot.org/c/coreboot/+/76013/comment/aa273183_14359931 : PS1, Line 34: register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 : register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC : register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN : register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN : : register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/3 Type A port A1 : > Where is the XHCI you mentioned? I'm Sorry for commenting late. The controller is in line 331. Just put these options there as you did with `chip drivers/usb/acpi` -- To view, visit https://review.coreboot.org/c/coreboot/+/76013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd9788a75f9c342f85d6e1a3d54327d64797dd8 Gerrit-Change-Number: 76013 Gerrit-PatchSet: 3 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 02:37:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/google/nissa/var/gothrax: Initialise overridetree
by Yunlong Jia (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Derek Huang, Felix Singer, Henry Sun, Tarun Tuli. Yunlong Jia has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76013?usp=email ) Change subject: mb/google/nissa/var/gothrax: Initialise overridetree ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/gothrax/overridetree.cb: https://review.coreboot.org/c/coreboot/+/76013/comment/71a2b7d4_29271791 : PS3, Line 168: probed > detect We see that some places use "detect" and "probed", so what is the difference between the two? -- To view, visit https://review.coreboot.org/c/coreboot/+/76013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd9788a75f9c342f85d6e1a3d54327d64797dd8 Gerrit-Change-Number: 76013 Gerrit-PatchSet: 3 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 02:22:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Derek Huang <derekhuang(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: vendorcode/amd/fsp/common: Refactor dmi_info.h
by Eric Lai (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Konrad Adamczyk, Matt DeVillier, Raul Rangel. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76107?usp=email ) Change subject: vendorcode/amd/fsp/common: Refactor dmi_info.h ...................................................................... Patch Set 2: (1 comment) File src/vendorcode/amd/fsp/common/dmi_info.h: https://review.coreboot.org/c/coreboot/+/76107/comment/eb96918e_b0eac359 : PS2, Line 144: } DMI_T17_MEMORY_TYPE; This is the same like https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/thi… Maybe can do more rework for reuse the smbios.h -- To view, visit https://review.coreboot.org/c/coreboot/+/76107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e0109af51b78360f7038b20a2975aceb721a7d5 Gerrit-Change-Number: 76107 Gerrit-PatchSet: 2 Gerrit-Owner: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Konrad Adamczyk <konrada(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Jun 2023 02:07:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/google/nissa/var/gothrax: Initialise overridetree
by Yunlong Jia (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Derek Huang, Felix Singer, Henry Sun, Tarun Tuli. Yunlong Jia has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76013?usp=email ) Change subject: mb/google/nissa/var/gothrax: Initialise overridetree ...................................................................... Patch Set 3: (2 comments) File src/mainboard/google/brya/variants/gothrax/overridetree.cb: https://review.coreboot.org/c/coreboot/+/76013/comment/bdbe0747_da8e4ab5 : PS1, Line 34: register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB2_A1 : register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC : register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN : register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN : : register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/3 Type A port A1 > Don't you need these to enable the USB ports? I just don't know where is the best place to put it. Please refer to　comment#40． File src/mainboard/google/brya/variants/gothrax/overridetree.cb: https://review.coreboot.org/c/coreboot/+/76013/comment/1ce57cd0_589e710b : PS3, Line 176: device i2c 0x10 on end > do you have stop_gpio? Do you mean that we need to "stop_gpio" on the Touchscreen at a certain time? -- To view, visit https://review.coreboot.org/c/coreboot/+/76013?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfd9788a75f9c342f85d6e1a3d54327d64797dd8 Gerrit-Change-Number: 76013 Gerrit-PatchSet: 3 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Simon Yang <simon1.yang(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Henry Sun <henrysun(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 01:58:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Derek Huang <derekhuang(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: WIP:grunt/vboot: The hash read out are all 0 in in S3 resume
by Bao Zheng (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Julius Werner, Zheng Bao. Hello Julius Werner, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76141?usp=email to look at the new patch set (#2). Change subject: WIP:grunt/vboot: The hash read out are all 0 in in S3 resume ...................................................................... WIP:grunt/vboot: The hash read out are all 0 in in S3 resume Change-Id: I48aa8eda74999ecfb95e31c642d332f6e978bd69 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/security/vboot/vboot_logic.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/76141/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76141?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48aa8eda74999ecfb95e31c642d332f6e978bd69 Gerrit-Change-Number: 76141 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

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coreboot-gerrit June 2023