coreboot-gerrit June 2023

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[M] Change in coreboot[master]: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C ...
by CoolStar (Code Review) 28 Jun '23

28 Jun '23

Attention is currently required from: CoolStar, Martin Roth, Stefan Reinauer. Hello Martin Roth, Matt DeVillier, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76159?usp=email to look at the new patch set (#3). Change subject: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver ...................................................................... mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver This is a brand new I2C driver that is designed specifically for the Pixel 2013 chromebook (LINK). The GMBus interface on the IGPU is an i2c-compatible interface, but AFAIK only Link has touch devices attached in this way. On Windows, the PCIe device for the IGP is owned by the Intel proprietary driver, hence a separate ACPI device has to be added for the I2C bus arbitrator to attach to. The MMIO method is used instead of _CRS so that Windows does not try to assign ownership of the resource to our device (even though we're using the MMIO registers at the same time as the IGP driver). Even though in theory 2 drivers accessing the same MMIO may cause problems, in testing, there has been no issues with sleep/wake/hibernate, updating/installing/uninstalling the IGP driver, or changing display resolutions with the i2c driver attached. The arbitrator is necessary as well, since even though there are multiple i2c buses, the MMIO registers are shared. Hence a shared lock is required for i2c access across the buses. The original Sleep Button devices are preserved for Linux due to the completely custom and non-standard implementation of the Windows driver in order to work around the non-standard nature of Link's hardware. Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475 Signed-off-by: CoolStar <coolstarorganization(a)gmail.com> --- M src/mainboard/google/link/acpi/mainboard.asl M src/mainboard/google/link/dsdt.asl M src/mainboard/google/link/onboard.h 3 files changed, 113 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/76159/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/76159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475 Gerrit-Change-Number: 76159 Gerrit-PatchSet: 3 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C ...
by CoolStar (Code Review) 28 Jun '23

28 Jun '23

Attention is currently required from: CoolStar, Martin Roth, Stefan Reinauer. Hello Martin Roth, Matt DeVillier, Stefan Reinauer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76159?usp=email to look at the new patch set (#2). Change subject: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver ...................................................................... mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver This is a brand new I2C driver that is designed specifically for the Pixel 2013 chromebook (LINK). The GMBus interface on the IGPU is an i2c-compatible interface, but AFAIK only Link has touch devices attached in this way. On Windows, the PCIe device for the IGP is owned by the Intel proprietary driver, hence a separate ACPI device has to be added for the I2C driver arbitrator to attach to. The MMIO method is used instead of _CRS so that Windows does not try to assign ownership of the resource to our device (even though we're using the MMIO registers at the same time as the IGP driver). Even though in theory 2 drivers accessing the same MMIO may cause problems, in testing, there has been no issues with sleep/wake/hibernate, updating/installing/uninstalling the IGP driver, or changing display resolutions with the i2c driver attached. The arbitrator is necessary as well, since even though there are multiple i2c buses, the MMIO registers are shared. Hence a shared lock is required for i2c access across the buses. The original Sleep Button devices are preserved for Linux due to the completely custom and non-standard implementation of the Windows driver in order to work around the non-standard nature of Link's hardware. Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475 Signed-off-by: CoolStar <coolstarorganization(a)gmail.com> --- M src/mainboard/google/link/acpi/mainboard.asl M src/mainboard/google/link/dsdt.asl M src/mainboard/google/link/onboard.h 3 files changed, 113 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/76159/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475 Gerrit-Change-Number: 76159 Gerrit-PatchSet: 2 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-MessageType: newpatchset

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[NoOp] Change in gerrit-avatars[main]: Change avatar for 1001369 (CoolStar)
by CoolStar (Code Review) 28 Jun '23

28 Jun '23

CoolStar has uploaded this change for review. ( https://review.coreboot.org/c/gerrit-avatars/+/76161?usp=email ) Change subject: Change avatar for 1001369 (CoolStar) ...................................................................... Change avatar for 1001369 (CoolStar) Change-Id: If3a54c818752a4dc510d1c6d2832bd43a6f40943 Signed-off-by: CoolStar <coolstarorganization(a)gmail.com> --- M 1001369.jpg 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/gerrit-avatars refs/changes/61/76161/1 diff --git a/1001369.jpg b/1001369.jpg index 41d803c..e67c026 100644 --- a/1001369.jpg +++ b/1001369.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/76161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: main Gerrit-Change-Id: If3a54c818752a4dc510d1c6d2832bd43a6f40943 Gerrit-Change-Number: 76161 Gerrit-PatchSet: 1 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C ...
by Matt DeVillier (Code Review) 28 Jun '23

28 Jun '23

Attention is currently required from: CoolStar, Martin Roth, Stefan Reinauer. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76159?usp=email ) Change subject: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver ...................................................................... Patch Set 1: (4 comments) Patchset: PS1: > This is a brand new I2C driver that is designed specifically for the Pixel 2013 chromebook (LINK). […] I would copy/paste this entire comment into the commit msg File src/mainboard/google/link/acpi/mainboard.asl: https://review.coreboot.org/c/coreboot/+/76159/comment/f8acdc66_570c5228 : PS1, Line 14: // Trackpad Wake is GPIO12 : Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 } ) : what do ppl think about commenting out and adding a note as to why vs removing? https://review.coreboot.org/c/coreboot/+/76159/comment/62034983_28cb5ce9 : PS1, Line 38: / Touchscreen Wake is GPIO14 : Name(_PRW, Package(){0x1e, 0x03}) : same as above File src/mainboard/google/link/dsdt.asl: https://review.coreboot.org/c/coreboot/+/76159/comment/71215639_d91cc53f : PS1, Line 36: #include "acpi/mainboard.asl" add a comment here to note the change in ordering was to ensure that we scope _SB.PCI0.GFX after the device is declared in the GMA asl -- To view, visit https://review.coreboot.org/c/coreboot/+/76159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475 Gerrit-Change-Number: 76159 Gerrit-PatchSet: 1 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Jun 2023 20:34:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: CoolStar <coolstarorganization(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Set system_configuration to 3 to avo...
by 9elements QA (Code Review) 28 Jun '23

28 Jun '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76096?usp=email ) Change subject: mb/google/skyrim/var/winterhold: Set system_configuration to 3 to avoid SMU call ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 8 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/171037 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/171035 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/171034 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/171033 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/171032 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/171031 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/171030 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/171029 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/171028 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/171027 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/171026 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/171025 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/171024 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/171023 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/171022 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/171021 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/76096?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib12c73f95030625b52e26f86e932ee2aaa6ea522 Gerrit-Change-Number: 76096 Gerrit-PatchSet: 4 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Jun 2023 20:32:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.4221.00
by Bora Guvendik (Code Review) 28 Jun '23

28 Jun '23

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76147?usp=email ) Change subject: vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.4221.00 ...................................................................... vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP RPL.4221.00 The headers added are generated as per FSP v4221.00 BUG= TEST=Boot to OS Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> Change-Id: I23f6e1e4baa39883475cd93fa6aabcec4e7152cd --- M src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h 2 files changed, 139 insertions(+), 102 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/76147/1 diff --git a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h index a98c554..ef18b43 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h @@ -3354,7 +3354,11 @@ /** Offset 0x08F1 - Reserved **/ - UINT8 Reserved111[3]; + UINT8 Reserved111; + +/** Offset 0x08F2 - Reserved +**/ + UINT8 Reserved112[2]; /** Offset 0x08F4 - PMR Size Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot @@ -3368,31 +3372,31 @@ /** Offset 0x08F9 - Reserved **/ - UINT8 Reserved112; + UINT8 Reserved113; /** Offset 0x08FA - Reserved **/ - UINT16 Reserved113; + UINT16 Reserved114; /** Offset 0x08FC - Reserved **/ - UINT8 Reserved114; + UINT8 Reserved115; /** Offset 0x08FD - Reserved **/ - UINT8 Reserved115; + UINT8 Reserved116; /** Offset 0x08FE - Reserved **/ - UINT8 Reserved116; + UINT8 Reserved117; /** Offset 0x08FF - Reserved **/ - UINT8 Reserved117[88]; + UINT8 Reserved118[88]; /** Offset 0x0957 - Reserved **/ - UINT8 Reserved118; + UINT8 Reserved119; /** Offset 0x0958 - TotalFlashSize Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable @@ -3408,7 +3412,7 @@ /** Offset 0x095C - Reserved **/ - UINT8 Reserved119[12]; + UINT8 Reserved120[12]; /** Offset 0x0968 - Smbus dynamic power gating Disable or Enable Smbus dynamic power gating. @@ -3474,7 +3478,7 @@ /** Offset 0x0972 - Reserved **/ - UINT8 Reserved120[2]; + UINT8 Reserved121[2]; /** Offset 0x0974 - Hybrid Graphics GPIO information for PEG 1 Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs @@ -3511,7 +3515,7 @@ /** Offset 0x0A97 - Reserved **/ - UINT8 Reserved121; + UINT8 Reserved122; /** Offset 0x0A98 - SerialIoUartDebugRxPinMux - FSPT Select RX pin muxing for SerialIo UART used for debug @@ -3537,183 +3541,187 @@ /** Offset 0x0AA8 - Reserved **/ - UINT8 Reserved122; + UINT8 Reserved123; /** Offset 0x0AA9 - Reserved **/ - UINT8 Reserved123; + UINT8 Reserved124; /** Offset 0x0AAA - Reserved **/ - UINT16 Reserved124; + UINT16 Reserved125; /** Offset 0x0AAC - Reserved **/ - UINT8 Reserved125[4]; + UINT8 Reserved126[4]; /** Offset 0x0AB0 - Reserved **/ - UINT8 Reserved126; + UINT8 Reserved127; /** Offset 0x0AB1 - Reserved **/ - UINT8 Reserved127; + UINT8 Reserved128; /** Offset 0x0AB2 - Reserved **/ - UINT8 Reserved128[6]; + UINT8 Reserved129[4]; + +/** Offset 0x0AB6 - Reserved +**/ + UINT8 Reserved130[2]; /** Offset 0x0AB8 - Reserved **/ - UINT64 Reserved129; + UINT64 Reserved131; /** Offset 0x0AC0 - Reserved **/ - UINT64 Reserved130; + UINT64 Reserved132; /** Offset 0x0AC8 - Reserved **/ - UINT32 Reserved131; + UINT32 Reserved133; /** Offset 0x0ACC - Reserved **/ - UINT8 Reserved132[8]; + UINT8 Reserved134[8]; /** Offset 0x0AD4 - Reserved **/ - UINT8 Reserved133; + UINT8 Reserved135; /** Offset 0x0AD5 - Reserved **/ - UINT8 Reserved134[3]; + UINT8 Reserved136[3]; /** Offset 0x0AD8 - Reserved **/ - UINT32 Reserved135; + UINT32 Reserved137; /** Offset 0x0ADC - Reserved **/ - UINT32 Reserved136; + UINT32 Reserved138; /** Offset 0x0AE0 - Reserved **/ - UINT16 Reserved137; + UINT16 Reserved139; /** Offset 0x0AE2 - Reserved **/ - UINT16 Reserved138; + UINT16 Reserved140; /** Offset 0x0AE4 - Reserved **/ - UINT16 Reserved139; + UINT16 Reserved141; /** Offset 0x0AE6 - Reserved **/ - UINT8 Reserved140; + UINT8 Reserved142; /** Offset 0x0AE7 - Reserved **/ - UINT8 Reserved141; + UINT8 Reserved143; /** Offset 0x0AE8 - Reserved **/ - UINT8 Reserved142; + UINT8 Reserved144; /** Offset 0x0AE9 - Reserved **/ - UINT8 Reserved143; + UINT8 Reserved145; /** Offset 0x0AEA - Reserved **/ - UINT8 Reserved144; + UINT8 Reserved146; /** Offset 0x0AEB - Reserved **/ - UINT8 Reserved145[5]; + UINT8 Reserved147[5]; /** Offset 0x0AF0 - Reserved **/ - UINT64 Reserved146; + UINT64 Reserved148; /** Offset 0x0AF8 - Reserved **/ - UINT64 Reserved147; + UINT64 Reserved149; /** Offset 0x0B00 - Reserved **/ - UINT32 Reserved148; + UINT32 Reserved150; /** Offset 0x0B04 - Reserved **/ - UINT16 Reserved149; + UINT16 Reserved151; /** Offset 0x0B06 - Reserved **/ - UINT8 Reserved150; + UINT8 Reserved152; /** Offset 0x0B07 - Reserved **/ - UINT8 Reserved151; + UINT8 Reserved153; /** Offset 0x0B08 - Reserved **/ - UINT8 Reserved152; + UINT8 Reserved154; /** Offset 0x0B09 - Reserved **/ - UINT8 Reserved153; + UINT8 Reserved155; /** Offset 0x0B0A - Reserved **/ - UINT8 Reserved154; + UINT8 Reserved156; /** Offset 0x0B0B - Reserved **/ - UINT8 Reserved155; + UINT8 Reserved157; /** Offset 0x0B0C - Reserved **/ - UINT8 Reserved156; + UINT8 Reserved158; /** Offset 0x0B0D - Reserved **/ - UINT8 Reserved157; + UINT8 Reserved159; /** Offset 0x0B0E - Reserved **/ - UINT16 Reserved158; + UINT16 Reserved160; /** Offset 0x0B10 - Reserved **/ - UINT16 Reserved159; + UINT16 Reserved161; /** Offset 0x0B12 - Reserved **/ - UINT16 Reserved160; + UINT16 Reserved162; /** Offset 0x0B14 - Reserved **/ - UINT16 Reserved161; + UINT16 Reserved163; /** Offset 0x0B16 - Reserved **/ - UINT8 Reserved162[8]; + UINT8 Reserved164[8]; /** Offset 0x0B1E - Reserved **/ - UINT8 Reserved163[8]; + UINT8 Reserved165[8]; /** Offset 0x0B26 - Reserved **/ - UINT16 Reserved164; + UINT16 Reserved166; /** Offset 0x0B28 - Reserved **/ - UINT8 Reserved165; + UINT8 Reserved167; /** Offset 0x0B29 - Reserved **/ - UINT8 Reserved166; + UINT8 Reserved168; /** Offset 0x0B2A - LP5 Bank Mode LP5 Bank Mode. 0: Auto, 1: 8 Bank Mode, 2: 16 Bank Mode, 3: BG Mode, default is 0 @@ -3723,31 +3731,49 @@ /** Offset 0x0B2B - Reserved **/ - UINT8 Reserved167; + UINT8 Reserved169; /** Offset 0x0B2C - Reserved **/ - UINT8 Reserved168; + UINT8 Reserved170; /** Offset 0x0B2D - Reserved **/ - UINT8 Reserved169; + UINT8 Reserved171; /** Offset 0x0B2E - Reserved **/ - UINT8 Reserved170; + UINT8 Reserved172; -/** Offset 0x0B2F - Reserved +/** Offset 0x0B2F - CsPiStartHighinEct + Cs Pi Start with High value in Ect: 0(Default)=Disable, 1=Enable + $EN_DIS **/ - UINT8 Reserved171; + UINT8 CsPiStartHighinEct; /** Offset 0x0B30 - Reserved **/ - UINT8 Reserved172[4]; + UINT8 Reserved173; + +/** Offset 0x0B31 - Reserved +**/ + UINT8 Reserved174; + +/** Offset 0x0B32 - LowerBasicMemTestSize + Reduce BasicMemoryTest size WA: 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 LowerBasicMemTestSize; + +/** Offset 0x0B33 - DisableSagvReorder + Disable Sagv reorder on warm boot: 0(Default)=Disable, 1=Enable + $EN_DIS +**/ + UINT8 DisableSagvReorder; /** Offset 0x0B34 - Reserved **/ - UINT8 Reserved173[4]; + UINT8 Reserved175[4]; } FSP_M_CONFIG; /** Fsp M UPD Configuration diff --git a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h index 2fbf99f..645d7cd 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h @@ -2321,7 +2321,8 @@ UINT8 SataRstPcieDeviceResetDelay[3]; /** Offset 0x0A42 - UFS enable/disable - PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms + Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller + 0 and (0,1) to enable controller 1 $EN_DIS **/ UINT8 UfsEnable[2]; @@ -2962,7 +2963,7 @@ UINT8 CpuPcieRpDpcExtensionsEnabled[4]; /** Offset 0x0C18 - CPU PCIe root port connection type - 0: built-in device, 1:slot + DEPRECATED **/ UINT8 CpuPcieRpSlotImplemented[4]; @@ -3808,11 +3809,21 @@ /** Offset 0x0D87 - Reserved **/ - UINT8 Reserved92[13]; + UINT8 Reserved92; + +/** Offset 0x0D88 - Enable or Disable HwP Scalability Tracking + Enable or Disable HwP Scalability Tracking. 0: Disable; 1: Enable + $EN_DIS +**/ + UINT8 EnableHwpScalabilityTracking; + +/** Offset 0x0D89 - Reserved +**/ + UINT8 Reserved93[11]; /** Offset 0x0D94 - Reserved **/ - UINT8 Reserved93[16]; + UINT8 Reserved94[16]; /** Offset 0x0DA4 - End of Post message Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1): @@ -3861,7 +3872,7 @@ /** Offset 0x0DAB - Reserved **/ - UINT8 Reserved94[1]; + UINT8 Reserved95[1]; /** Offset 0x0DAC - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. @@ -4013,19 +4024,19 @@ /** Offset 0x0F96 - Reserved **/ - UINT8 Reserved95[4]; + UINT8 Reserved96[4]; /** Offset 0x0F9A - Reserved **/ - UINT8 Reserved96[4]; + UINT8 Reserved97[4]; /** Offset 0x0F9E - Reserved **/ - UINT8 Reserved97[4]; + UINT8 Reserved98[4]; /** Offset 0x0FA2 - Reserved **/ - UINT8 Reserved98[4]; + UINT8 Reserved99[4]; /** Offset 0x0FA6 - FOMS Control Policy Choose the Foms Control Policy, Default = 0 @@ -4047,23 +4058,23 @@ /** Offset 0x0FAF - Reserved **/ - UINT8 Reserved99[8]; + UINT8 Reserved100[8]; /** Offset 0x0FB7 - Reserved **/ - UINT8 Reserved100[8]; + UINT8 Reserved101[8]; /** Offset 0x0FBF - Reserved **/ - UINT8 Reserved101[8]; + UINT8 Reserved102[8]; /** Offset 0x0FC7 - Reserved **/ - UINT8 Reserved102[8]; + UINT8 Reserved103[8]; /** Offset 0x0FCF - Reserved **/ - UINT8 Reserved103; + UINT8 Reserved104; /** Offset 0x0FD0 - FspEventHandler Optional pointer to the boot loader's implementation of FSP_EVENT_HANDLER. @@ -4078,99 +4089,99 @@ /** Offset 0x0FD5 - Reserved **/ - UINT8 Reserved104[4]; + UINT8 Reserved105[4]; /** Offset 0x0FD9 - Reserved **/ - UINT8 Reserved105; + UINT8 Reserved106; /** Offset 0x0FDA - Reserved **/ - UINT8 Reserved106; + UINT8 Reserved107; /** Offset 0x0FDB - Reserved **/ - UINT8 Reserved107; + UINT8 Reserved108; /** Offset 0x0FDC - Reserved **/ - UINT32 Reserved108; + UINT32 Reserved109; /** Offset 0x0FE0 - Reserved **/ - UINT32 Reserved109; + UINT32 Reserved110; /** Offset 0x0FE4 - Reserved **/ - UINT32 Reserved110[2]; + UINT32 Reserved111[2]; /** Offset 0x0FEC - Reserved **/ - UINT32 Reserved111[2]; + UINT32 Reserved112[2]; /** Offset 0x0FF4 - Reserved **/ - UINT32 Reserved112[2]; + UINT32 Reserved113[2]; /** Offset 0x0FFC - Reserved **/ - UINT32 Reserved113[2]; + UINT32 Reserved114[2]; /** Offset 0x1004 - Reserved **/ - UINT32 Reserved114[2]; + UINT32 Reserved115[2]; /** Offset 0x100C - Reserved **/ - UINT32 Reserved115[2]; + UINT32 Reserved116[2]; /** Offset 0x1014 - Reserved **/ - UINT32 Reserved116[2]; + UINT32 Reserved117[2]; /** Offset 0x101C - Reserved **/ - UINT32 Reserved117[2]; + UINT32 Reserved118[2]; /** Offset 0x1024 - Reserved **/ - UINT32 Reserved118[2]; + UINT32 Reserved119[2]; /** Offset 0x102C - Reserved **/ - UINT32 Reserved119[2]; + UINT32 Reserved120[2]; /** Offset 0x1034 - Reserved **/ - UINT32 Reserved120[2]; + UINT32 Reserved121[2]; /** Offset 0x103C - Reserved **/ - UINT32 Reserved121[2]; + UINT32 Reserved122[2]; /** Offset 0x1044 - Reserved **/ - UINT32 Reserved122[2]; + UINT32 Reserved123[2]; /** Offset 0x104C - Reserved **/ - UINT8 Reserved123[4]; + UINT8 Reserved124[4]; /** Offset 0x1050 - Reserved **/ - UINT64 Reserved124; + UINT64 Reserved125; /** Offset 0x1058 - Reserved **/ - UINT32 Reserved125; + UINT32 Reserved126; /** Offset 0x105C - Reserved **/ - UINT8 Reserved126[2]; + UINT8 Reserved127[2]; /** Offset 0x105E - Reserved **/ - UINT8 Reserved127[2]; + UINT8 Reserved128[2]; } FSP_S_CONFIG; /** Fsp S UPD Configuration -- To view, visit https://review.coreboot.org/c/coreboot/+/76147?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23f6e1e4baa39883475cd93fa6aabcec4e7152cd Gerrit-Change-Number: 76147 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C ...
by CoolStar (Code Review) 28 Jun '23

28 Jun '23

Attention is currently required from: Martin Roth, Matt DeVillier. CoolStar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76159?usp=email ) Change subject: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: This is a brand new I2C driver that is designed specifically for the Pixel 2013 chromebook (LINK). The GMBus interface on the IGPU is an i2c-compatible interface, but AFAIK only Link has touch devices attached in this way. On Windows, the PCIe device for the IGP is owned by the Intel proprietary driver, hence a separate ACPI device has to be added for the I2C driver arbitrator to attach to. The `MMIO` method is used instead of `_CRS` so that Windows does not try to assign ownership of the resource to our device (even though we're using the MMIO registers at the same time as the IGP driver). Even though in theory 2 drivers accessing the same MMIO may cause problems, in testing, there has been no issues with sleep/wake/hibernate, updating/installing/uninstalling the IGP driver, or changing display resolutions with the i2c driver attached. The arbitrator is necessary as well, since even though there are multiple i2c buses, the MMIO registers are shared. Hence a shared lock is required for i2c access across the buses. The original Sleep Button devices are preserved for Linux due to the completely custom and non-standard implementation of the Windows driver in order to work around the non-standard nature of Link's hardware. -- To view, visit https://review.coreboot.org/c/coreboot/+/76159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475 Gerrit-Change-Number: 76159 Gerrit-PatchSet: 1 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Jun 2023 20:23:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C ...
by CoolStar (Code Review) 28 Jun '23

28 Jun '23

CoolStar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76159?usp=email ) Change subject: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver ...................................................................... mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475 Signed-off-by: CoolStar <coolstarorganization(a)gmail.com> --- M src/mainboard/google/link/acpi/mainboard.asl M src/mainboard/google/link/dsdt.asl M src/mainboard/google/link/onboard.h 3 files changed, 113 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/76159/1 diff --git a/src/mainboard/google/link/acpi/mainboard.asl b/src/mainboard/google/link/acpi/mainboard.asl index 3e751bb..fe0c8fc 100644 --- a/src/mainboard/google/link/acpi/mainboard.asl +++ b/src/mainboard/google/link/acpi/mainboard.asl @@ -11,9 +11,6 @@ // automatically enable it as a wake source Name(_HID, EisaId("PNP0C0E")) - // Trackpad Wake is GPIO12 - Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 } ) - Name(_CRS, ResourceTemplate() { // PIRQE -> GSI20 @@ -35,9 +32,6 @@ // automatically enable it as a wake source Name(_HID, EisaId("PNP0C0E")) - // Touchscreen Wake is GPIO14 - Name(_PRW, Package(){0x1e, 0x03}) - Name(_CRS, ResourceTemplate() { // PIRQG -> GSI22 @@ -48,3 +42,111 @@ }) } } + + +Scope (\_SB.PCI0.GFX0) +{ + Device (GMBS){ + Name (_HID, "LINK0000") + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Method (MMIO, 0, Serialized) + { + Local0 = BAR0 & 0xFFFFFFFFFFFFFFF0 + Return (Local0) + } + + Device (LVGA){ + Name (_HID, "LINK0001") + Name (_UID, 0) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) {"coolstar,bus-number", GMBUS_PIN_VGADDC} + } + }) + + Method (_STA) + { + Return (0xF) + } + + Device (ATPD) + { + Name (_HID, "ATML0000") + Name (_DDN, "Atmel Touchpad") + Name (_UID, 0) + Name (ISTP, 1) //Touchpad + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_TRACKPAD_I2C_ADDR, // SlaveAddress + ControllerInitiated, // SlaveMode + 100000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.GFX0.GMBS.LVGA", // ResourceSource + ) + + Interrupt (ResourceConsumer, Level, ActiveLow) { BOARD_TRACKPAD_IRQ } + }) + + // Trackpad Wake is GPIO12 + Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 } ) + + Method (_STA) + { + Return (0xF) + } + } + } + + Device (LPNL){ + Name (_HID, "LINK0001") + Name (_UID, 1) + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) {"coolstar,bus-number", GMBUS_PIN_PANEL} + } + }) + + Method (_STA) + { + Return (0xF) + } + + Device (ATSA) + { + Name (_HID, "ATML0001") + Name (_DDN, "Atmel TouchScreen") + Name (_UID, 0) + Name (ISTP, 0) //TouchScreen + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_TOUCHSCREEN_I2C_ADDR, // SlaveAddress + ControllerInitiated, // SlaveMode + 100000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.GFX0.GMBS.LPNL", // ResourceSource + ) + + Interrupt (ResourceConsumer, Level, ActiveLow) { BOARD_TOUCHSCREEN_IRQ } + }) + + // Touchscreen Wake is GPIO14 + Name(_PRW, Package(){0x1e, 0x03}) + + Method (_STA) + { + Return (0xF) + } + } + } + } +} diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl index 81e3074..dbb3413 100644 --- a/src/mainboard/google/link/dsdt.asl +++ b/src/mainboard/google/link/dsdt.asl @@ -14,7 +14,6 @@ #include <southbridge/intel/common/acpi/platform.asl> #include "acpi/platform.asl" - #include "acpi/mainboard.asl" // Thermal handler #include "acpi/thermal.asl" @@ -34,5 +33,7 @@ } } + #include "acpi/mainboard.asl" + #include <southbridge/intel/common/acpi/sleepstates.asl> } diff --git a/src/mainboard/google/link/onboard.h b/src/mainboard/google/link/onboard.h index efcda92..30cb7d1 100644 --- a/src/mainboard/google/link/onboard.h +++ b/src/mainboard/google/link/onboard.h @@ -20,4 +20,7 @@ #define GPIO_SPI_WP 57 +#define GMBUS_PIN_VGADDC 2 +#define GMBUS_PIN_PANEL 3 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/76159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475 Gerrit-Change-Number: 76159 Gerrit-PatchSet: 1 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: nb/intel/pineview: Drop unused attributes from sysinfo struct
by 9elements QA (Code Review) 28 Jun '23

28 Jun '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76098?usp=email ) Change subject: nb/intel/pineview: Drop unused attributes from sysinfo struct ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 8 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/171020 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/171018 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/171017 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/171016 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/171015 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/171014 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/171013 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/171012 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/171011 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/171010 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/171009 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/171008 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/171007 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/171006 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/171005 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/171004 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/76098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab582458a7dd87e10bf14fd34f15c592b600f706 Gerrit-Change-Number: 76098 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Jun 2023 20:09:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google: AMD: move tpm_tis to AMD common code
by Martin L Roth (Code Review) 28 Jun '23

28 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Grzegorz Bernacki, Jason Glenesk, Jason Nien, Jon Murphy, Martin Roth, Matt DeVillier, Paul Menzel, Raul Rangel, Yu-Ping Wu. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75621?usp=email ) Change subject: mb/google: AMD: move tpm_tis to AMD common code ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/common/block/gpio/Kconfig: https://review.coreboot.org/c/coreboot/+/75621/comment/f0dcbfac_025a1e76 : PS3, Line 22: TPM_TIS_INTERRUPT > ```TPM_TIS_INTERRUPT``` is used for Intel platform, I think it make sense to use the same name I was thinking the same thing about this name as Yu-Ping. Is it a GPIO on Intel as well? Maybe change it to TPM_IRQ_GPIO on both in a follow-on patch? This isn't an interrupt number, so in my opinion shouldn't be named "XXX_INTERUPT". -- To view, visit https://review.coreboot.org/c/coreboot/+/75621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I775c4e24cffee99b6ac3e05b58a75425029a86c8 Gerrit-Change-Number: 75621 Gerrit-PatchSet: 3 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 28 Jun 2023 19:57:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Grzegorz Bernacki Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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