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Change subject: intel/common/block/cpu: add cpu clock measure api
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/cpu/cpulib.c:
https://review.coreboot.org/c/coreboot/+/76123/comment/8a643497_254acd02 :
PS3, Line 527: udelay(100);
> Need to be careful about static delay if we are going to call this function multiple times.
Agreed. This function will be used early time for checking different silicon SKU.
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Change subject: vendorcode/amd/fsp/common: Refactor dmi_info.h
......................................................................
Patch Set 2:
(2 comments)
File src/vendorcode/amd/fsp/glinda/soc_dmi_info.h:
https://review.coreboot.org/c/coreboot/+/76107/comment/8e5582e5_5824f01b :
PS2, Line 6:
Please add `/* TODO: Update for Glinda */`
File src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h:
https://review.coreboot.org/c/coreboot/+/76107/comment/d3db53b4_f367fb6b :
PS2, Line 10: #define MAX_SOCKETS_SUPPORTED 2 ///< Max number of sockets in system
: #define MAX_CHANNELS_PER_SOCKET 8 ///< Max Channels per sockets
: #define MAX_DIMMS_PER_CHANNEL 4 ///< Max DIMMs on a memory channel (independent of platform)
:
I *think* mendocino is 4/12/2 here like phoenix - at least that matches the constants in the FSP code.
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Change subject: acpi: Set checksum for SPCR table
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76158/comment/02879de6_4ad79a84 :
PS1, Line 13: Fixes: commit 90464073e4a1 (acpi: Add SPCR table)
> Not confirmed yet if it fixes the errors that the 9e QA sees.
Which error specifically?
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Change subject: acpi: Set checksum for SPCR table
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76158/comment/99b252da_9464f64f :
PS1, Line 13: Fixes: commit 90464073e4a1 (acpi: Add SPCR table)
Not confirmed yet if it fixes the errors that the 9e QA sees.
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Hello Arthur Heymans, Lean Sheng Tan,
I'd like you to do a code review.
Please visit
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to review the following change.
Change subject: acpi: Set checksum for SPCR table
......................................................................
acpi: Set checksum for SPCR table
This was missed recently when adding the table.
Change-Id: I0086a3e8c5b3a06da9edf40a7a288c534fc5a6b2
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
Fixes: commit 90464073e4a1 (acpi: Add SPCR table)
---
M src/acpi/acpi.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/76158/1
diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c
index e0e72f7..267a989 100644
--- a/src/acpi/acpi.c
+++ b/src/acpi/acpi.c
@@ -1866,6 +1866,8 @@
spcr->language = 0;
spcr->pci_did = 0xffff;
spcr->pci_vid = 0xffff;
+
+ header->checksum = acpi_checksum((void *)spcr, header->length);
}
unsigned long __weak fw_cfg_acpi_tables(unsigned long start)
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Hello Jason Nien, Karthik Ramasubramanian, Mark Hasemeyer, Martin Roth, Raul Rangel, Tim Van Patten, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/74607?usp=email
to look at the new patch set (#6).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/google/skyrim: Add named GPIO's
......................................................................
mb/google/skyrim: Add named GPIO's
Add named GPIOs to help prevent confusion in GPIO management
BUG=b:278968729
TEST=TIMELESS=1 emerge-...coreboot before and after change
compare binaries
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
Change-Id: I24a8f7e5bfa9e3e586d4189132f47551202f7d2d
---
M src/mainboard/google/skyrim/chromeos.c
M src/mainboard/google/skyrim/ec.c
M src/mainboard/google/skyrim/port_descriptors.c
M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h
M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h
M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/skyrim/variants/baseboard/smihandler.c
M src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c
A src/mainboard/google/skyrim/variants/crystaldrift/include/variant/gpio.h
A src/mainboard/google/skyrim/variants/frostflow/include/variant/gpio.h
M src/mainboard/google/skyrim/variants/markarth/gpio.c
A src/mainboard/google/skyrim/variants/markarth/include/variant/gpio.h
M src/mainboard/google/skyrim/variants/markarth/port_descriptors.c
A src/mainboard/google/skyrim/variants/skyrim/include/variant/gpio.h
A src/mainboard/google/skyrim/variants/winterhold/include/variant/gpio.h
M src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c
M src/mainboard/google/skyrim/verstage.c
17 files changed, 116 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/74607/6
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Change subject: mb/google/kahlee: Enable Secure OS
......................................................................
Patch Set 9: Code-Review+2
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Change subject: mb/google/kahlee: Enable Secure OS
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/google/kahlee/Kconfig:
https://review.coreboot.org/c/coreboot/+/75874/comment/a80260e0_106ce9e8 :
PS7, Line 149: config USE_PSPSECUREOS
: def_bool n if CHROMEOS
: def_bool y
> nit: I guess we should only define the type one: […]
Done
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