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Change subject: mb/google/skyrim/var/markarth: Add custom ABL
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Change subject: mb/google/skyrim/var/markarth: Add amdfw.cfg
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Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75874?usp=email )
Change subject: mb/google/kahlee: Enable Secure OS
......................................................................
Patch Set 7:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75874/comment/6edaa072_8e39f32f :
PS5, Line 7: secure
> Secure
Done
https://review.coreboot.org/c/coreboot/+/75874/comment/17cca391_3bf5b8f6 :
PS5, Line 10: risks
> Just out of curiosity: The help text of the Kconfig doesn't mention […]
Nothing specific, just reduce attack surface, it's not used, so it was disabled
https://review.coreboot.org/c/coreboot/+/75874/comment/83f8f212_ec5f4bda :
PS5, Line 15: secure
> Secure
Done
https://review.coreboot.org/c/coreboot/+/75874/comment/a6b7e472_29566766 :
PS5, Line 17:
> does not resolve because updated PSP bootloader is needed
Yea, this will enable the solution but does not resolve the issue.
File src/mainboard/google/kahlee/Kconfig:
https://review.coreboot.org/c/coreboot/+/75874/comment/8f9c0317_1d1fe261 :
PS5, Line 148: # Don't use AMD's Secure OS if ChromeOS build.
> Commit 09abb879a41a (mainboard/google/kahlee: Don't use AMD's secure OS, Change-Id https://review. […]
Acknowledged
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Hello CoolStar, Jason Nien, Martin Roth, Matt DeVillier, Nico Huber, Raul Rangel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75874?usp=email
to look at the new patch set (#7).
Change subject: mb/google/kahlee: Enable Secure OS
......................................................................
mb/google/kahlee: Enable Secure OS
Secure OS was disabled on Grunt devices since it isn't used.
This reduces the attack surface and is meant to mitigate potential
security risks. However, this prevents users from using an alternate OS.
Enable Secure OS upstream to allows users to use Windows, and ensure
that it is still disabled in the chromium repo.
BUG=b:287630343
TEST=Builds with Secure OS included.
Cq-Depend: chromium:4620881
Change-Id: I213aebc41cae300ecee8c01fc5c7687f7e7f5ee3
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
---
M src/mainboard/google/kahlee/Kconfig
1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/75874/7
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Hello CoolStar, Jason Nien, Martin Roth, Matt DeVillier, Nico Huber, Raul Rangel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75874?usp=email
to look at the new patch set (#6).
Change subject: mb/google/kahlee: Enable Secure OS
......................................................................
mb/google/kahlee: Enable Secure OS
Secure OS was disabled on Grunt devices to mitigate potential security
risks. However, this prevents users from using an alternate OS.
Enable Secure OS upstream to allows users to use Windows, and ensure
that it is still disabled in the chromium repo.
BUG=b:287630343
TEST=Builds with Secure OS included.
Cq-Depend: chromium:4620881
Change-Id: I213aebc41cae300ecee8c01fc5c7687f7e7f5ee3
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
---
M src/mainboard/google/kahlee/Kconfig
1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/75874/6
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76134?usp=email )
Change subject: mb/google/rex: Avoid boot hang due to missing SOC/IOE SRAM device
......................................................................
mb/google/rex: Avoid boot hang due to missing SOC/IOE SRAM device
The SOC/IOE SRAM device is used to store crash logs. Previously, the
crashlog enablement was hardcoded in the baseboard.common module.
This commit moves the crashlog enablement logic to the baseboard
module, so that it can be enabled or disabled based on the specific
baseboard.
Additionally, the SOC/IOE SRAM is now enabled by default in the
baseboard devicetree.cb file. This prevents the system from hanging
if the SOC/IOE SRAM device is not present.
BUG=b:262501347
TEST=Able to build and boot google/screebo with this patch.
w/o this patch:
[ERROR] Â SOC SRAM device not found!
[ERROR] Â IOE SRAM base not valid
Change-Id: I02d581e5b62cfa114a3761a9704ad9f24dead8aa
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76134
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
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---
M src/mainboard/google/rex/Kconfig
M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
M src/mainboard/google/rex/variants/rex0/overridetree.cb
3 files changed, 3 insertions(+), 4 deletions(-)
Approvals:
Eric Lai: Looks good to me, approved
build bot (Jenkins): Verified
Kapil Porwal: Looks good to me, approved
diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig
index 4bb9a67..f131b70 100644
--- a/src/mainboard/google/rex/Kconfig
+++ b/src/mainboard/google/rex/Kconfig
@@ -25,11 +25,9 @@
select MAINBOARD_HAS_TPM2
select PMC_IPC_ACPI_INTERFACE
select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT
- select SOC_INTEL_CRASHLOG
select SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2
select SOC_INTEL_CSE_SEND_EOP_ASYNC
- select SOC_INTEL_IOE_DIE_SUPPORT
config BOARD_GOOGLE_BASEBOARD_REX
def_bool n
@@ -40,6 +38,8 @@
select HAVE_SLP_S0_GATE
select MAINBOARD_HAS_CHROMEOS
select MEMORY_SOLDERDOWN
+ select SOC_INTEL_CRASHLOG
+ select SOC_INTEL_IOE_DIE_SUPPORT
select SOC_INTEL_METEORLAKE_U_H
select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
select SYSTEM_TYPE_LAPTOP
diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
index 7acc0ae..76b9dcd 100644
--- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
+++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb
@@ -73,6 +73,7 @@
device domain 0 on
device ref igpu on end
device ref dtt on end
+ device ref ioe_shared_sram on end
device ref xhci on end
device ref pmc_shared_sram on end
device ref heci1 on end
diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb
index bd38595..4f74ea4 100644
--- a/src/mainboard/google/rex/variants/rex0/overridetree.cb
+++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb
@@ -349,7 +349,6 @@
device generic 0 on end
end
end
- device ref ioe_shared_sram on end
device ref xhci on
chip drivers/usb/acpi
device ref xhci_root_hub on
@@ -413,7 +412,6 @@
end
end
end
- device ref pmc_shared_sram on end
device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "GPE0_PME_B0"
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75357?usp=email )
Change subject: cpu/intel/microcode: Have CPU microcode per CPUID into CBFS
......................................................................
Patch Set 18:
(1 comment)
File src/cpu/Kconfig:
https://review.coreboot.org/c/coreboot/+/75357/comment/a19406f5_6c843c8c :
PS14, Line 123: bool "Include microcode per CPUID into CBFS"
> > > This option will show on ALL platforms. Does it even make sense to have it as a user visible option?
> >
> > it will allow to override the default value from site-local rather forcing to enable from SoC/MB config using upstream coreboot.
> >
> > As we are not uploading the ucode blobs in coreboot upstream build hence it's easy to go by default value which is `n` and don't need to specify the split ucode blob path.
>
> @Arthur, ping! can you please take a relook.
marking this resolved for now after keeping open for 1 week
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