coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: drivers/spi_flash: Always exit 4-byte address mode when memory-mapped
by Fred Reitberger (Code Review) 28 Jun '23

28 Jun '23

Attention is currently required from: Julius Werner. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76093?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/spi_flash: Always exit 4-byte address mode when memory-mapped ...................................................................... drivers/spi_flash: Always exit 4-byte address mode when memory-mapped Always send the Exit 4-Byte Address Mode (E9h) command before the first access to the SPI flash in all stages when the SPI flash is memory-mapped. This is useful for x86 mainboards that do not access SPI flash in bootblock yet still need to exit 4-byte addressing mode in romstage or ramstage. Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I3a62bfa44a0a5645c1bb80b32d0b9f92075c66bf --- M src/drivers/spi/spi_flash.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/76093/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76093?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a62bfa44a0a5645c1bb80b32d0b9f92075c66bf Gerrit-Change-Number: 76093 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: soc/amd/common/block/acpi/ivrs: fix missing IOAPIC[1] error
by Arthur Heymans (Code Review) 28 Jun '23

28 Jun '23

Attention is currently required from: Felix Held, Jason Glenesk, Martin L Roth, Matt DeVillier, Raul Rangel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76117?usp=email ) Change subject: soc/amd/common/block/acpi/ivrs: fix missing IOAPIC[1] error ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id88f17d68ba5accef6561837478828bd3d24baa5 Gerrit-Change-Number: 76117 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 28 Jun 2023 12:54:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/phoenix/Kconfig: Drop TODO for FSP_DMI_TABLES
by Konrad Adamczyk (Code Review) 28 Jun '23

28 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Konrad Adamczyk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76109?usp=email ) Change subject: soc/amd/phoenix/Kconfig: Drop TODO for FSP_DMI_TABLES ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/76109?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a8aae12ec449fe921814a6e363306fced969367 Gerrit-Change-Number: 76109 Gerrit-PatchSet: 2 Gerrit-Owner: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 28 Jun 2023 12:50:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: vendorcode/amd/fsp/common: Refactor dmi_info.h
by Konrad Adamczyk (Code Review) 28 Jun '23

28 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Konrad Adamczyk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76107?usp=email ) Change subject: vendorcode/amd/fsp/common: Refactor dmi_info.h ...................................................................... Patch Set 2: (1 comment) This change is ready for review. Patchset: PS1: > Looks like the only difference between this and the common one is a few MemType enum values that can […] Sure, it makes sense. See v2. -- To view, visit https://review.coreboot.org/c/coreboot/+/76107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e0109af51b78360f7038b20a2975aceb721a7d5 Gerrit-Change-Number: 76107 Gerrit-PatchSet: 2 Gerrit-Owner: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 28 Jun 2023 12:50:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/common/fsp: Fix dimm_num assignment
by Konrad Adamczyk (Code Review) 28 Jun '23

28 Jun '23

Attention is currently required from: Eric Lai, Felix Held, Fred Reitberger, Jason Glenesk, Konrad Adamczyk, Matt DeVillier, Raul Rangel. Hello Eric Lai, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76108?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+2 by Eric Lai, Code-Review+2 by Fred Reitberger, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/amd/common/fsp: Fix dimm_num assignment ...................................................................... soc/amd/common/fsp: Fix dimm_num assignment The dimm_num shall be dimm, not channel. BUG=b:288520486 TEST=In kernel, see output from `dmidecode -t 17`. Observe that Locator reflects proper location of the module. Change-Id: Id876a5c245ed1a145c930b3456830d7b42780b74 Signed-off-by: Konrad Adamczyk <konrada(a)google.com> --- M src/soc/amd/common/fsp/dmi.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/76108/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76108?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id876a5c245ed1a145c930b3456830d7b42780b74 Gerrit-Change-Number: 76108 Gerrit-PatchSet: 2 Gerrit-Owner: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Konrad Adamczyk <konrada(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: drivers/spi_flash: Add option to always exit 4-byte address mode
by Fred Reitberger (Code Review) 28 Jun '23

28 Jun '23

Attention is currently required from: Julius Werner. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76093?usp=email ) Change subject: drivers/spi_flash: Add option to always exit 4-byte address mode ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I don't think there's a point in making this a separate Kconfig. […] That's a much better idea and it should not conflict with other mainboards that use the EXIT_4_BYTE_ADDR_MODE config. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/76093?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a62bfa44a0a5645c1bb80b32d0b9f92075c66bf Gerrit-Change-Number: 76093 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 28 Jun 2023 12:01:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: sb/intel/lynxpoint: Don't generate second SSDT
by Arthur Heymans (Code Review) 28 Jun '23

28 Jun '23

Arthur Heymans has uploaded a new patch set (#7). ( https://review.coreboot.org/c/coreboot/+/76129?usp=email ) Change subject: sb/intel/lynxpoint: Don't generate second SSDT ...................................................................... sb/intel/lynxpoint: Don't generate second SSDT Move the entries in SSDT to acpi_fill_ssdt(). There is need for a separate table. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ie23d5b5b967de162ea9ac60a64bc92d0b3bee08e --- M src/southbridge/intel/lynxpoint/Makefile.inc D src/southbridge/intel/lynxpoint/acpi.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.h 4 files changed, 16 insertions(+), 73 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/76129/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/76129?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie23d5b5b967de162ea9ac60a64bc92d0b3bee08e Gerrit-Change-Number: 76129 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: acpi: Add SPCR table
by 9elements QA (Code Review) 28 Jun '23

28 Jun '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75685?usp=email ) Change subject: acpi: Add SPCR table ...................................................................... Patch Set 7: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 8 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/170847 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/170845 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/170844 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/170843 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/170842 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/170841 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/170840 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/170839 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/170838 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/170837 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/170836 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/170835 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/170834 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/170833 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/170832 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/170831 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/75685?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64e624c17a27b9215a8ba83bd6cbb2c0a7aa1dfc Gerrit-Change-Number: 75685 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Jun 2023 10:17:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/meteorlake: remove unused tcss mailbox code
by Kapil Porwal (Code Review) 28 Jun '23

28 Jun '23

Attention is currently required from: Jakub Czapiga, John Zhao, Kane Chen, Marx Wang, Subrata Banik, Tarun Tuli. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76126?usp=email ) Change subject: soc/intel/meteorlake: remove unused tcss mailbox code ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a4b26c38ec3f5fe1d81fd70f8c2196d0e5b84c3 Gerrit-Change-Number: 76126 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Marx Wang <marx.wang(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Comment-Date: Wed, 28 Jun 2023 09:14:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: acpi: Add SPCR table
by Lean Sheng Tan (Code Review) 28 Jun '23

28 Jun '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75685?usp=email ) Change subject: acpi: Add SPCR table ...................................................................... acpi: Add SPCR table TESTED works on IO and MMIO console with linux using 'earlycon=' in the commandline argument. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I64e624c17a27b9215a8ba83bd6cbb2c0a7aa1dfc Reviewed-on: https://review.coreboot.org/c/coreboot/+/75685 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 87 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index cfc388b..e0e72f7 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1799,6 +1799,75 @@ return lpi_desc->header.length; } +static uint8_t acpi_spcr_type(void) +{ + /* 16550-compatible with parameters defined in Generic Address Structure */ + if (CONFIG(DRIVERS_UART_8250IO) || CONFIG(DRIVERS_UART_8250MEM)) + return 0x12; + if (CONFIG(DRIVERS_UART_PL011)) + return 0x3; + + printk(BIOS_ERR, "%s: unknown serial type\n", __func__); + return 0xff; +} + +static void acpi_create_spcr(acpi_spcr_t *spcr) +{ + acpi_header_t *header = &(spcr->header); + struct lb_serial serial; + + /* The caller checks the header size, so call this first */ + memset((void *)spcr, 0, sizeof(acpi_spcr_t)); + + if (!CONFIG(CONSOLE_SERIAL)) + return; + + if (fill_lb_serial(&serial) != CB_SUCCESS) + return; + + memcpy(header->signature, "SPCR", 4); + header->length = sizeof(acpi_spcr_t); + header->revision = get_acpi_table_revision(SPCR); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = asl_revision; + + spcr->interface_type = acpi_spcr_type(); + assert(serial.type == LB_SERIAL_TYPE_IO_MAPPED + || serial.type == LB_SERIAL_TYPE_MEMORY_MAPPED); + spcr->base_address.space_id = serial.type == LB_SERIAL_TYPE_IO_MAPPED ? + ACPI_ADDRESS_SPACE_IO : ACPI_ADDRESS_SPACE_MEMORY; + spcr->base_address.bit_width = serial.regwidth * 8; + spcr->base_address.bit_offset = 0; + switch (serial.regwidth) { + case 1: + spcr->base_address.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + break; + case 2: + spcr->base_address.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + break; + case 4: + spcr->base_address.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + break; + default: + printk(BIOS_ERR, "%s, Invalid serial regwidth\n", __func__); + } + + spcr->base_address.addrl = serial.baseaddr; + spcr->base_address.addrh = 0; + spcr->interrupt_type = 0; + spcr->irq = 0; + spcr->configured_baudrate = 0; /* Have the OS use whatever is currently set */ + spcr->parity = 0; + spcr->stop_bits = 1; + spcr->flow_control = 0; + spcr->terminal_type = 2; /* 2 = VT-UTF8 */ + spcr->language = 0; + spcr->pci_did = 0xffff; + spcr->pci_vid = 0xffff; +} + unsigned long __weak fw_cfg_acpi_tables(unsigned long start) { return 0; @@ -2122,6 +2191,15 @@ } } + printk(BIOS_DEBUG, "ACPI: * SPCR\n"); + acpi_spcr_t * const spcr = (acpi_spcr_t *)current; + acpi_create_spcr(spcr); + if (spcr->header.length >= sizeof(acpi_spcr_t)) { + current += spcr->header.length; + acpi_add_table(rsdp, spcr); + } + current = acpi_align_current(current); + printk(BIOS_DEBUG, "current = %lx\n", current); for (dev = all_devices; dev; dev = dev->next) { @@ -2292,6 +2370,8 @@ return 1; case LPIT: /* ACPI 5.1 up to 6.3: 0 */ return 0; + case SPCR: + return 4; default: return -1; } diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index d3f209a..1704393 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -75,6 +75,7 @@ /* Tables defined by ACPI and used by coreboot */ BERT, CEDT, DBG2, DMAR, DSDT, EINJ, FACS, FADT, HEST, HMAT, HPET, IVRS, MADT, MCFG, RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, LPIT, + SPCR, /* Additional proprietary tables used by coreboot */ VFCT, NHLT, SPMI, CRAT }; @@ -1328,6 +1329,12 @@ } __packed acpi_spcr_t; _Static_assert(sizeof(acpi_spcr_t) == 88, "acpi_spcr_t must have an 88 byte size\n"); +#define PC_AT_COMPATIBLE_INTERRUPT (1 << 0) +#define IO_APIC_COMPATIBLE_INTERRUPT (1 << 1) +#define IO_SAPIC_COMPATIBLE_INTERRUPT (1 << 2) +#define ARMH_GIC_COMPATIBLE_INTERRUPT (1 << 3) +#define RISCV_PLIC_COMPATIBLE_INTERRUPT (1 << 4) + uintptr_t get_coreboot_rsdp(void); void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions); -- To view, visit https://review.coreboot.org/c/coreboot/+/75685?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64e624c17a27b9215a8ba83bd6cbb2c0a7aa1dfc Gerrit-Change-Number: 75685 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit June 2023