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Change subject: mb/google/rex/var/ovis: Enable SaGv
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Patch Set 2: Code-Review+2
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Change subject: soc/intel/meteorlake: remove unused tcss mailbox code
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76126/comment/23e668d1_c2661e1b :
PS1, Line 16: TEST
Can it be more like
"Made sure that no errors were seen after S0ix test and DP/USB over TCSS were working as expected"
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Change subject: intel/common/block/cpu: add cpu clock measure api
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Patch Set 3:
(1 comment)
File src/soc/intel/common/block/cpu/cpulib.c:
https://review.coreboot.org/c/coreboot/+/76123/comment/bb1d40db_676f7623 :
PS3, Line 527: udelay(100);
Need to be careful about static delay if we are going to call this function multiple times.
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Change subject: mb/google/rex/var/ovis: Enable SaGv
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Patch Set 2: Code-Review+2
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Change subject: mb/google/nissa/var/uldren: Modify DPTF parameters
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Patch Set 1:
(1 comment)
File src/mainboard/google/brya/variants/uldren/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/76105/comment/e06cd4cc_4d4962a0 :
PS1, Line 180: 130
> > Where can I find this SSDT sheet? […]
Hi Sumeet,
If you find the SSDT sheet, could you please mark this to resolved and review +2'? Thank you.
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Hello Eric Lai, Jakub Czapiga, Kapil Porwal, Tarun Tuli, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/76138?usp=email
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Code-Review+1 by Eric Lai, Verified+1 by build bot (Jenkins)
Change subject: mb/google/rex/var/ovis: Enable SaGv
......................................................................
mb/google/rex/var/ovis: Enable SaGv
This patch enables SaGv with fixed frequency and gears for Ovis.
Restrict memory speed to 6400 MTS as per board design.
BUG=b:282164577
TEST=Verified the settings on google/ovis using debug FSP logs
Change-Id: Ia9703344a8ae9d2ba44a16c62afab820fd8e2177
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb
1 file changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/76138/2
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Change subject: mb/google/rex/var/ovis: Enable SaGv
......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/76138/comment/bed3d5b5_940c136a :
PS1, Line 44: register "sagv_freq_mhz[0]" = "3200"
> maybe gather together as array assigning?
Acknowledged
https://review.coreboot.org/c/coreboot/+/76138/comment/8b6d4172_8fa0d944 :
PS1, Line 53: register "sagv_freq_mhz[3]" = "5600"
> curious why we back to gear2 here?
I don't have any good answer to your question except this what we found as per the doc
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Change subject: mb/system76: Add space for ramtop in CMOS layout
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Should this be within the checksum range?
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Change subject: mb/google/rex/var/ovis: Enable SaGv
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/76138/comment/20ce3349_3049347b :
PS1, Line 53: register "sagv_freq_mhz[3]" = "5600"
curious why we back to gear2 here?
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