coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

1 participants
5387 discussions

[M] Change in coreboot[master]: mb/google/brya/acpi: Hades Update ACPI GPU Sequences to have Aborts
by Eran Mitrani (Code Review) 28 Jun '23

28 Jun '23

Eran Mitrani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76146?usp=email ) Change subject: mb/google/brya/acpi: Hades Update ACPI GPU Sequences to have Aborts ...................................................................... mb/google/brya/acpi: Hades Update ACPI GPU Sequences to have Aborts For Hades power on sequence , in case an expected handshake fails when powering on, abort and power off. Note: Also added an error if timing out waiting for correct vendor ID. BUG=287218791 TEST=Tested on Hades. currently fails on the VID error, set to WIP. Signed-off-by: Eran Mitrani <mitrani(a)google.com> Change-Id: I1ea1916c52461d36f2fc8d4cb98bbc0f56d998c7 --- M src/mainboard/google/brya/acpi/power.asl 1 file changed, 53 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/76146/1 diff --git a/src/mainboard/google/brya/acpi/power.asl b/src/mainboard/google/brya/acpi/power.asl index 7eb31d8..8626bcb 100644 --- a/src/mainboard/google/brya/acpi/power.asl +++ b/src/mainboard/google/brya/acpi/power.asl @@ -111,6 +111,21 @@ Local0, PMC_RP_IDX, Local1) } +/* + * Check return code from GPPL, and shut down if it failed. + * Arg0 == return code from GPPL: 0 = OK, FF = Failure + * Arg1 == calling function name + * Arg2 == signal name + */ +Method(PGOR, 3, Serialized) +{ + if (Arg0 != 0) { + Printf("[ERROR] %o: %o not asserted. Shutting down power.", Arg1, Arg2) + PGOF() + } + Return (Arg0) +} + /* "GC6 In", i.e. GC6 Entry Sequence */ Method (GC6I, 0, Serialized) { @@ -168,15 +183,24 @@ STXS (GPIO_GPU_PERST_L) /* Wait for GPU to assert GPU_NVVDD_EN */ - GPPL (GPIO_GPU_NVVDD_EN, 1, 20) + Local0 = GPPL (GPIO_GPU_NVVDD_EN, 1, 20) + if (PGOR(Local0, "GC6O", "GPIO_GPU_NVVDD_EN") != 0) { + return + } /* Ramp up NVVDD */ STXS (GPIO_NVVDD_PWR_EN) - GPPL (NVPG, 1, 4) + Local0 = GPPL (NVPG, 1, 4) + if (PGOR(Local0, "GC6O", "GPIO_GPU_NVVDD_EN") != 0) { + return + } /* Ramp up PEXVDD */ STXS (GPIO_PEXVDD_PWR_EN) - GPPL (GPIO_PEXVDD_PG, 1, 4) + Local0 = GPPL (GPIO_PEXVDD_PG, 1, 4) + if (PGOR(Local0, "GC6O", "GPIO_PEXVDD_PG") != 0) { + return + } /* Ramp up FBVDD - TODO: Remove Agah when board is dropped */ #if CONFIG(BOARD_GOOGLE_AGAH) @@ -200,6 +224,7 @@ Local0-- If (Local0 == 0) { + Printf("[ERROR] dGPU didn't reappear on the bus.. NVID=0x%x", NVID) Break } } @@ -229,23 +254,38 @@ /* Ramp up 1.2V rail on boards with support */ STXS (GPIO_NV12_PWR_EN) - GPPL (GPIO_NV12_PG, 1, 5) + Local0 = GPPL (GPIO_NV12_PG, 1, 5) + if (PGOR(Local0, "PGON", "GPIO_NV12_PG") != 0) { + return + } /* Ramp up 1.8V rail */ STXS (GPEN) - GPPL (GPIO_1V8_PG, 1, 20) + Local0 = GPPL (GPIO_1V8_PG, 1, 20) + if (PGOR(Local0, "PGON", "GPIO_1V8_PG") != 0) { + return + } /* Ramp up NV33 rail */ STXS (GPIO_NV33_PWR_EN) - GPPL (GPIO_NV33_PG, 1, 20) + Local0 = GPPL (GPIO_NV33_PG, 1, 20) + if (PGOR(Local0, "PGON", "GPIO_NV33_PG") != 0) { + return + } /* Ramp up NVVDD rail */ STXS (GPIO_NVVDD_PWR_EN) - GPPL (NVPG, 1, 5) + Local0 = GPPL (NVPG, 1, 5) + if (PGOR(Local0, "PGON", "NVPG") != 0) { + return + } /* Ramp up PEXVDD rail */ STXS (GPIO_PEXVDD_PWR_EN) - GPPL (GPIO_PEXVDD_PG, 1, 5) + Local0 = GPPL (GPIO_PEXVDD_PG, 1, 5) + if (PGOR(Local0, "PGON", "GPIO_PEXVDD_PG") != 0) { + return + } /* Ramp up FBVDD rail */ #if CONFIG(BOARD_GOOGLE_AGAH) @@ -254,7 +294,10 @@ STXS (GPIO_FBVDD_PWR_EN) #endif - GPPL (GPIO_FBVDD_PG, 1, 5) + Local0 = GPPL (GPIO_FBVDD_PG, 1, 5) + if (PGOR(Local0, "PGON", "GPIO_FBVDD_PG") != 0) { + return + } /* All rails are good */ STXS (GPIO_GPU_ALLRAILS_PG) @@ -333,6 +376,7 @@ Local0-- If (Local0 == 0) { + Printf("[ERROR] dGPU didn't reappear on the bus.. NVID=0x%x", NVID) Break } } -- To view, visit https://review.coreboot.org/c/coreboot/+/76146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ea1916c52461d36f2fc8d4cb98bbc0f56d998c7 Gerrit-Change-Number: 76146 Gerrit-PatchSet: 1 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: cpu/intel/microcode: Have CPU microcode per CPUID into CBFS
by Subrata Banik (Code Review) 28 Jun '23

28 Jun '23

Attention is currently required from: Arthur Heymans, Himanshu Sahdev, Julius Werner, Lean Sheng Tan, Rizwan Qureshi, Tarun Tuli, Wonkyu Kim. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75357?usp=email ) Change subject: cpu/intel/microcode: Have CPU microcode per CPUID into CBFS ...................................................................... Patch Set 18: (1 comment) File src/cpu/Kconfig: https://review.coreboot.org/c/coreboot/+/75357/comment/54885759_f42ad61c : PS14, Line 123: bool "Include microcode per CPUID into CBFS" > > > > > > This option will show on ALL platforms. Does it even make sense to have it as a user visible option? > > > > > > > > > > it will allow to override the default value from site-local rather forcing to enable from SoC/MB config using upstream coreboot. > > > > > > > > > > As we are not uploading the ucode blobs in coreboot upstream build hence it's easy to go by default value which is `n` and don't need to specify the split ucode blob path. > > > > > > > > @Arthur, ping! can you please take a relook. > > > > > > marking this resolved for now after keeping open for 1 week > > > > It's not about default values. If I run make menuconfig and select a mainboard I should not be able to see any option that makes no sense. > > Which is the case now. I can see the option to split microcode on platforms that would not boot when selecting it as they rely on concatenation. Also I would see the existing options to include microcode and this new method. This should be mutually exclusive. do you suggest to use a HAVE_ config to ensure this user visible prompt is only visible for the desired platform and not to others ? -- To view, visit https://review.coreboot.org/c/coreboot/+/75357?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7db73335ffa25399869cfb0d59129ee118f1012 Gerrit-Change-Number: 75357 Gerrit-PatchSet: 18 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 28 Jun 2023 17:41:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: payloads/filo: Update branch name from master to main
by 9elements QA (Code Review) 28 Jun '23

28 Jun '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76101?usp=email ) Change subject: payloads/filo: Update branch name from master to main ...................................................................... Patch Set 4: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 8 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/170921 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/170919 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/170918 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/170917 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/170916 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/170915 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/170914 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/170913 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/170912 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/170911 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/170910 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/170909 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/170908 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/170907 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/170906 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/170905 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/76101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6c355d757987551e850f9d24f6bfb14167cb8046 Gerrit-Change-Number: 76101 Gerrit-PatchSet: 4 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 28 Jun 2023 17:37:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: cpu/intel/microcode: Have CPU microcode per CPUID into CBFS
by Arthur Heymans (Code Review) 28 Jun '23

28 Jun '23

1 0

[XS] Change in coreboot[master]: mb/google/rex/var/rex0: Change touch over spi interrupt trigger to edge
by Eran Mitrani (Code Review) 28 Jun '23

28 Jun '23

Attention is currently required from: Eric Lai, Jakub Czapiga, Kapil Porwal, Tarun Tuli. Eran Mitrani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76116?usp=email ) Change subject: mb/google/rex/var/rex0: Change touch over spi interrupt trigger to edge ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/rex/variants/rex0/include/variant/acpi/hid_spi_elan.asl: https://review.coreboot.org/c/coreboot/+/76116/comment/86dc36dc_de0cd9af : PS3, Line 42: Edge > For I2C mode, it's level. Wondering why level not working here. It is mentioned in the hid over spi spec here: https://www.microsoft.com/en-us/download/details.aspx?id=103325: "HID SPI peripheral must provide a dedicated falling (HIGH-TO-LOW) edge triggered interrupt line to indicate when data or status is ready. This interrupt line must be pulled HIGH by hardware otherwise, meeting both HOST and DEVICE electrical requirements" -- To view, visit https://review.coreboot.org/c/coreboot/+/76116?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78937af22df22d80a702477b6790a7aa40d782a4 Gerrit-Change-Number: 76116 Gerrit-PatchSet: 3 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 28 Jun 2023 17:36:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: cpu/intel/microcode: Have CPU microcode per CPUID into CBFS
by Arthur Heymans (Code Review) 28 Jun '23

28 Jun '23

Attention is currently required from: Himanshu Sahdev, Julius Werner, Lean Sheng Tan, Rizwan Qureshi, Subrata Banik, Tarun Tuli, Wonkyu Kim. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75357?usp=email ) Change subject: cpu/intel/microcode: Have CPU microcode per CPUID into CBFS ...................................................................... Patch Set 18: (1 comment) File src/cpu/Kconfig: https://review.coreboot.org/c/coreboot/+/75357/comment/15a03f1d_a51b3645 : PS14, Line 123: bool "Include microcode per CPUID into CBFS" > > > > > This option will show on ALL platforms. Does it even make sense to have it as a user visible option? > > > > > > > > it will allow to override the default value from site-local rather forcing to enable from SoC/MB config using upstream coreboot. > > > > > > > > As we are not uploading the ucode blobs in coreboot upstream build hence it's easy to go by default value which is `n` and don't need to specify the split ucode blob path. > > > > > > @Arthur, ping! can you please take a relook. > > > > marking this resolved for now after keeping open for 1 week > > It's not about default values. If I run make menuconfig and select a mainboard I should not be able to see any option that makes no sense. Which is the case now. I can see the option to split microcode on platforms that would not boot when selecting it as they rely on concatenation. Also I would see the existing options to include microcode and this new method. This should be mutually exclusive. -- To view, visit https://review.coreboot.org/c/coreboot/+/75357?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7db73335ffa25399869cfb0d59129ee118f1012 Gerrit-Change-Number: 75357 Gerrit-PatchSet: 18 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 28 Jun 2023 17:27:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: cpu/intel/microcode: Have CPU microcode per CPUID into CBFS
by Arthur Heymans (Code Review) 28 Jun '23

28 Jun '23

Attention is currently required from: Himanshu Sahdev, Julius Werner, Lean Sheng Tan, Rizwan Qureshi, Subrata Banik, Tarun Tuli, Wonkyu Kim. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75357?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: cpu/intel/microcode: Have CPU microcode per CPUID into CBFS ...................................................................... Patch Set 18: (1 comment) File src/cpu/Kconfig: https://review.coreboot.org/c/coreboot/+/75357/comment/ce261704_c7b41645 : PS14, Line 123: bool "Include microcode per CPUID into CBFS" > > > > This option will show on ALL platforms. Does it even make sense to have it as a user visible option? > > > > > > it will allow to override the default value from site-local rather forcing to enable from SoC/MB config using upstream coreboot. > > > > > > As we are not uploading the ucode blobs in coreboot upstream build hence it's easy to go by default value which is `n` and don't need to specify the split ucode blob path. > > > > @Arthur, ping! can you please take a relook. > > marking this resolved for now after keeping open for 1 week It's not about default values. If I run make menuconfig and select a mainboard I should not be able to see any option that makes no sense. -- To view, visit https://review.coreboot.org/c/coreboot/+/75357?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7db73335ffa25399869cfb0d59129ee118f1012 Gerrit-Change-Number: 75357 Gerrit-PatchSet: 18 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 28 Jun 2023 17:23:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/skyrim: Add named GPIO's
by Jon Murphy (Code Review) 28 Jun '23

28 Jun '23

Attention is currently required from: Jason Nien, Jon Murphy, Karthik Ramasubramanian, Mark Hasemeyer, Martin Roth, Raul Rangel, Tim Van Patten. Hello Jason Nien, Karthik Ramasubramanian, Mark Hasemeyer, Martin Roth, Raul Rangel, Tim Van Patten, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74607?usp=email to look at the new patch set (#3). Change subject: mb/google/skyrim: Add named GPIO's ...................................................................... mb/google/skyrim: Add named GPIO's Add named GPIOs to help prevent confusion in GPIO management BUG=b:278968729 TEST=TIMELESS=1 emerge-...coreboot before and after change compare binaries Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Change-Id: I24a8f7e5bfa9e3e586d4189132f47551202f7d2d --- M src/mainboard/google/skyrim/chromeos.c M src/mainboard/google/skyrim/ec.c M src/mainboard/google/skyrim/port_descriptors.c M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/gpio.h M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/skyrim/variants/baseboard/smihandler.c M src/mainboard/google/skyrim/variants/baseboard/tpm_tis.c A src/mainboard/google/skyrim/variants/crystaldrift/include/variant/gpio.h A src/mainboard/google/skyrim/variants/frostflow/include/variant/gpio.h M src/mainboard/google/skyrim/variants/markarth/gpio.c A src/mainboard/google/skyrim/variants/markarth/include/variant/gpio.h M src/mainboard/google/skyrim/variants/markarth/port_descriptors.c A src/mainboard/google/skyrim/variants/skyrim/include/variant/gpio.h A src/mainboard/google/skyrim/variants/winterhold/include/variant/gpio.h M src/mainboard/google/skyrim/variants/winterhold/port_descriptors.c M src/mainboard/google/skyrim/verstage.c 17 files changed, 116 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/74607/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/74607?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24a8f7e5bfa9e3e586d4189132f47551202f7d2d Gerrit-Change-Number: 74607 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Mark Hasemeyer <markhas(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Mark Hasemeyer <markhas(a)google.com> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: payloads/Memtest86Plus: Update branch name from master to main
by 9elements QA (Code Review) 28 Jun '23

28 Jun '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76100?usp=email ) Change subject: payloads/Memtest86Plus: Update branch name from master to main ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 8 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/170904 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/170902 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/170901 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/170900 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/170899 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/170898 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/170897 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/170896 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/170895 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/170894 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/170893 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/170892 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/170891 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/170890 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/170889 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/170888 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/76100?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I269249518019f5d0d12c57f1c14012abca86b48b Gerrit-Change-Number: 76100 Gerrit-PatchSet: 3 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 28 Jun 2023 17:15:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: mb/google/kahlee: Enable Secure OS
by Raul Rangel (Code Review) 28 Jun '23

28 Jun '23

Attention is currently required from: CoolStar, Felix Held, Jason Nien, Jon Murphy, Martin Roth, Matt DeVillier, Nico Huber, Paul Menzel. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75874?usp=email ) Change subject: mb/google/kahlee: Enable Secure OS ...................................................................... Patch Set 7: Code-Review+1 (1 comment) File src/mainboard/google/kahlee/Kconfig: https://review.coreboot.org/c/coreboot/+/75874/comment/b082ff0a_0a8f4fa0 : PS7, Line 149: config USE_PSPSECUREOS : def_bool n if CHROMEOS : def_bool y nit: I guess we should only define the type one: ``` config USE_PSPSECUREOS bool default n if CHROMEOS default y ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/75874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I213aebc41cae300ecee8c01fc5c7687f7e7f5ee3 Gerrit-Change-Number: 75874 Gerrit-PatchSet: 7 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 28 Jun 2023 17:11:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2023