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Change subject: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/link/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/76159/comment/715938d5_793c0c23 :
PS1, Line 14: // Trackpad Wake is GPIO12
: Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 } )
:
> well, there's no reason to make it either-or, since the two coexist without issue. […]
Okay, well then I didn't say anything 😊
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Change subject: acpi/acpi.c: Move ACPI header creation to a function
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/link/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/76159/comment/5e31fa2c_ef722a51 :
PS1, Line 14: // Trackpad Wake is GPIO12
: Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 } )
:
> I don't know if it's worth it, but how about using a Kconfig option to decide which code should be u […]
well, there's no reason to make it either-or, since the two coexist without issue. And using a Kconfig would mean you could only have the TP/TS functional in one OS vs the other, which is not what we want here. As it is now, both OSes work without issue.
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Change subject: vendorcode/amd/fsp/common: Refactor dmi_info.h
......................................................................
Patch Set 2:
(5 comments)
Patchset:
PS2:
I think we should list what's actually supported by coreboot, not the theoretical maximums supported by the silicon. These are limited by the packages we support to far below what the the limits in AGESA are set to, which seems ridiculously high.
File src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h:
https://review.coreboot.org/c/coreboot/+/76107/comment/74096437_68b3b09b :
PS2, Line 9:
coreboot only supports FP6 for Cezanne
FP6 Motherboard Design guide: #56178E Rev .50
1 socket, 2 channels, 1 dimms per channel.
If am5 socket support gets added, we can update it to 2 dimms per channel at that point.
1/2/1
File src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h:
https://review.coreboot.org/c/coreboot/+/76107/comment/15c22baf_d7cfc944 :
PS2, Line 10: #define MAX_SOCKETS_SUPPORTED 2 ///< Max number of sockets in system
: #define MAX_CHANNELS_PER_SOCKET 8 ///< Max Channels per sockets
: #define MAX_DIMMS_PER_CHANNEL 4 ///< Max DIMMs on a memory channel (independent of platform)
:
> I *think* mendocino is 4/12/2 here like phoenix - at least that matches the constants in the FSP cod […]
MDN is only available on FT6 and only supports 2 LPDDR 'DIMMS'
I think this should be 1/2/1
File src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h:
https://review.coreboot.org/c/coreboot/+/76107/comment/0b43b97c_9c76a367 :
PS2, Line 10: #define MAX_SOCKETS_SUPPORTED 4 ///< Max number of sockets in system
: #define MAX_CHANNELS_PER_SOCKET 12 ///< Max Channels per sockets
: #define MAX_DIMMS_PER_CHANNEL 2 ///< Max DIMMs on a memory channel (independent of platform)
MB Design guide for FP7/FP7R2: #56920 Rev1.06
FP7/FP7R2 supports 1 socket, 2 channels, 1 dimm per channel
MB Design guide for FP8: #57263 Rev .92
FP8 supports 1 socket, 4 32-bit channels LPDDR5/5x, 1 dimm per channel.
This is somewhat confusing though as each "DIMM" will have 2 32-bit channels. As far as SMBIOS is concerned, I think this should be reported as 1/2/1, but AGESA may report 1/4/1, so who knows.
1/2/1 ?
File src/vendorcode/amd/fsp/picasso/soc_dmi_info.h:
https://review.coreboot.org/c/coreboot/+/76107/comment/f5c52b81_55003785 :
PS2, Line 9:
Picasso is only on FP5 socket.
FP5 Motherboard design guide: #55597 Rev 1.18
FP5 supports 1 socket, 2 channels, 1 dimm per channel
1/2/1
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Change subject: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/link/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/76159/comment/5e4a5ccd_783aaff7 :
PS1, Line 14: // Trackpad Wake is GPIO12
: Name(_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x03 } )
:
> what do ppl think about commenting out and adding a note as to why vs removing?
I don't know if it's worth it, but how about using a Kconfig option to decide which code should be used? So we could guard these lines with `#ifndef CONFIG_WINDOWS_HACK` and Windows users can choose. Just an idea :)
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Change subject: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/link/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/76159/comment/7561fe1a_59e190b9 :
PS1, Line 36: #include "acpi/mainboard.asl"
> add a comment here to note the change in ordering was to ensure that we scope _SB.PCI0. […]
Done
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Hello Martin Roth, Matt DeVillier, Stefan Reinauer,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/76159?usp=email
to look at the new patch set (#4).
Change subject: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver
......................................................................
mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver
Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475
Signed-off-by: CoolStar <coolstarorganization(a)gmail.com>
---
M src/mainboard/google/link/acpi/mainboard.asl
M src/mainboard/google/link/dsdt.asl
M src/mainboard/google/link/onboard.h
3 files changed, 114 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/76159/4
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