coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: acpi: Set checksum for SPCR table
by Nico Huber (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Felix Singer, Lance Zhao, Lean Sheng Tan, Nico Huber, Tim Wawrzynczak. Hello Arthur Heymans, Lance Zhao, Lean Sheng Tan, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76158?usp=email to look at the new patch set (#2). Change subject: acpi: Set checksum for SPCR table ...................................................................... acpi: Set checksum for SPCR table This was missed recently when adding the table. Linux complains about the missing checksum, e.g. [ 0.186070] ACPI BIOS Warning (bug): Incorrect checksum in table [SPCR] - 0x00, should be 0x87 (20210730/tbprint-173) Tested with QEMU/Q35, albeit with changes to the special handling for ACPI with QEMU. The warning goes away. Change-Id: I0086a3e8c5b3a06da9edf40a7a288c534fc5a6b2 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Fixes: commit 90464073e4a1 (acpi: Add SPCR table) --- M src/acpi/acpi.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/76158/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76158?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0086a3e8c5b3a06da9edf40a7a288c534fc5a6b2 Gerrit-Change-Number: 76158 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/siemens/mc_apl1: Fix wrong register masking
by Jan Samek (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Mario Scheithauer, Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76177?usp=email ) Change subject: mb/siemens/mc_apl1: Fix wrong register masking ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd6e70dcb42c69cf3bc5d36db993e6def52eba58 Gerrit-Change-Number: 76177 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 11:07:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0
by Jan Samek (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Mario Scheithauer, Paul Menzel, Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76175?usp=email ) Change subject: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90 Gerrit-Change-Number: 76175 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 11:07:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0
by Jan Samek (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Mario Scheithauer, Paul Menzel, Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76175?usp=email ) Change subject: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0 ...................................................................... Patch Set 4: (1 comment) File src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c: https://review.coreboot.org/c/coreboot/+/76175/comment/b545cbcb_0bf5d8de : PS3, Line 43: (0x00 << 16) > bad fault... […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90 Gerrit-Change-Number: 76175 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 11:06:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Comment-In-Reply-To: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/nissa/yaviks: Tune eMMC DLL value for boot issue
by Wisley Chen (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: ChiaLing, Jamie Chen, Paul Menzel, Reka Norman, Ryan Lin, Tarun Tuli. Wisley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75812?usp=email ) Change subject: mb/google/nissa/yaviks: Tune eMMC DLL value for boot issue ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75812?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a2727dc0ce9dc86c6bfb6d85567afee1734db62 Gerrit-Change-Number: 75812 Gerrit-PatchSet: 2 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Super Ni <super.ni(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 10:49:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0
by Mario Scheithauer (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Jan Samek, Paul Menzel, Werner Zeh. Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76175?usp=email ) Change subject: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0 ...................................................................... Patch Set 4: (3 comments) File src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c: https://review.coreboot.org/c/coreboot/+/76175/comment/64e39c04_693b07c4 : PS3, Line 40: set > sets Done https://review.coreboot.org/c/coreboot/+/76175/comment/276dc20b_47a6a00f : PS3, Line 43: (0x00 << 16) > 0 is always 0 even shifted by 16 to the left 😊 bad fault...thanks! https://review.coreboot.org/c/coreboot/+/76175/comment/cacd6760_2fbc12e2 : PS3, Line 43: (0x00 << 16), (0x5a << 16) > Nit: are the parens necessary there? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90 Gerrit-Change-Number: 76175 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 09:50:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/siemens/mc_apl1: Fix wrong register masking
by Mario Scheithauer (Code Review) 29 Jun '23

29 Jun '23

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76177?usp=email ) Change subject: mb/siemens/mc_apl1: Fix wrong register masking ...................................................................... mb/siemens/mc_apl1: Fix wrong register masking With the previous instruction the complete register was set to '0'. Corrextly, only the bits 23:16 must be masked. Change-Id: Idd6e70dcb42c69cf3bc5d36db993e6def52eba58 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/76177/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c index b7b997b..8490ddc 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c @@ -12,6 +12,7 @@ #include <types.h> #define TX_DWORD3_P1 0xa8c +#define TX_SWING_MASK 0x00ff0000 void variant_mainboard_final(void) { @@ -42,10 +43,10 @@ /* * Correct the SATA transmit signal via the High Speed I/O Transmit * Control Register 3 on SATA port 1. - * Bit [23:16] set the output voltage swing for TX line. + * Bit [23:16] sets the output voltage swing for TX line. * The value 0x4a sets the swing level to 0.58 V. */ - pcr_rmw32(PID_MODPHY, TX_DWORD3_P1, (0x00 << 16), (0x4a << 16)); + pcr_rmw32(PID_MODPHY, TX_DWORD3_P1, ~TX_SWING_MASK, 0x4a << 16); } static void finalize_boot(void *unused) -- To view, visit https://review.coreboot.org/c/coreboot/+/76177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd6e70dcb42c69cf3bc5d36db993e6def52eba58 Gerrit-Change-Number: 76177 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0
by Mario Scheithauer (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Mario Scheithauer, Paul Menzel, Werner Zeh. Hello Jan Samek, Paul Menzel, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76175?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins) Change subject: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0 ...................................................................... mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0 Because of an incorrect transmit voltage swing, the signal must be adjusted. The factor of slices for full swing level can be corrected via the High Speed I/O Transmit Control Register 3. The appropriate value of 0.7 V was determined by using an oscilloscope. Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/76175/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/76175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90 Gerrit-Change-Number: 76175 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0
by Jan Samek (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Mario Scheithauer, Paul Menzel, Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76175?usp=email ) Change subject: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0 ...................................................................... Patch Set 3: (1 comment) File src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c: https://review.coreboot.org/c/coreboot/+/76175/comment/d516128b_fa908eb1 : PS3, Line 40: set sets -- To view, visit https://review.coreboot.org/c/coreboot/+/76175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90 Gerrit-Change-Number: 76175 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 08:09:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0
by Jan Samek (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Mario Scheithauer, Paul Menzel, Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76175?usp=email ) Change subject: mb/siemens/mc_apl5: Correct the Tx signal from SATA port 0 ...................................................................... Patch Set 3: (1 comment) File src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c: https://review.coreboot.org/c/coreboot/+/76175/comment/dbe9a813_86fcf64e : PS3, Line 43: (0x00 << 16) 0 is always 0 even shifted by 16 to the left 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/76175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I965960004ca44f1b37b16ce6484000fa7fd8ad90 Gerrit-Change-Number: 76175 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 08:08:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit June 2023