coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: acpi.c: Fill in >4G FADT entries correctly
by Arthur Heymans (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Arthur Heymans, Lance Zhao, Tim Wawrzynczak. Hello Lance Zhao, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76179?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: acpi.c: Fill in >4G FADT entries correctly ...................................................................... acpi.c: Fill in >4G FADT entries correctly Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I84ab0068e8409a5e525ddc781347087680d80640 --- M src/acpi/acpi.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/76179/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/76179?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84ab0068e8409a5e525ddc781347087680d80640 Gerrit-Change-Number: 76179 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: acpi: Set checksum for SPCR table
by Lean Sheng Tan (Code Review) 29 Jun '23

29 Jun '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76158?usp=email ) Change subject: acpi: Set checksum for SPCR table ...................................................................... acpi: Set checksum for SPCR table This was missed recently when adding the table. Linux complains about the missing checksum, e.g. [ 0.186070] ACPI BIOS Warning (bug): Incorrect checksum in table [SPCR] - 0x00, should be 0x87 (20210730/tbprint-173) Tested with QEMU/Q35, albeit with changes to the special handling for ACPI with QEMU. The warning goes away. Change-Id: I0086a3e8c5b3a06da9edf40a7a288c534fc5a6b2 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Fixes: commit 90464073e4a1 (acpi: Add SPCR table) Reviewed-on: https://review.coreboot.org/c/coreboot/+/76158 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/acpi/acpi.c 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index e0e72f7..267a989 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1866,6 +1866,8 @@ spcr->language = 0; spcr->pci_did = 0xffff; spcr->pci_vid = 0xffff; + + header->checksum = acpi_checksum((void *)spcr, header->length); } unsigned long __weak fw_cfg_acpi_tables(unsigned long start) -- To view, visit https://review.coreboot.org/c/coreboot/+/76158?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0086a3e8c5b3a06da9edf40a7a288c534fc5a6b2 Gerrit-Change-Number: 76158 Gerrit-PatchSet: 3 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: acpi.c: Fill in >4G FADT entries correctly
by Arthur Heymans (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Arthur Heymans, Lance Zhao, Tim Wawrzynczak. Hello Lance Zhao, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76179?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: acpi.c: Fill in >4G FADT entries correctly ...................................................................... acpi.c: Fill in >4G FADT entries correctly Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I84ab0068e8409a5e525ddc781347087680d80640 --- M src/acpi/acpi.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/76179/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76179?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84ab0068e8409a5e525ddc781347087680d80640 Gerrit-Change-Number: 76179 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: arch/arm64: Hook up FADT
by Arthur Heymans (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Julius Werner. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76180?usp=email ) Change subject: arch/arm64: Hook up FADT ...................................................................... arch/arm64: Hook up FADT Arm needs very little of FADT. Just a HW reduced model bit and low power idle bit set. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I197975f91cd47e418c8583cb0e7b7ea2330363b2 --- M src/arch/arm64/Makefile.inc A src/arch/arm64/acpi.c 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/76180/1 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 6b49743..81abe37 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -118,6 +118,7 @@ ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31.c ramstage-y += transition.c transition_asm.S ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c +ramstage-$(CONFIG_HAVE_ACPI_SUPPORT) += acpi.c rmodules_arm64-y += memset.S rmodules_arm64-y += memcpy.S diff --git a/src/arch/arm64/acpi.c b/src/arch/arm64/acpi.c new file mode 100644 index 0000000..30ccc30 --- /dev/null +++ b/src/arch/arm64/acpi.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> + +void arch_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->flags |= ACPI_FADT_HW_REDUCED_ACPI | ACPI_FADT_LOW_PWR_IDLE_S0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/76180?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I197975f91cd47e418c8583cb0e7b7ea2330363b2 Gerrit-Change-Number: 76180 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: acpi.c: Fill in >4G FADT entries correctly
by Arthur Heymans (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76179?usp=email ) Change subject: acpi.c: Fill in >4G FADT entries correctly ...................................................................... acpi.c: Fill in >4G FADT entries correctly Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I84ab0068e8409a5e525ddc781347087680d80640 --- M src/acpi/acpi.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/76179/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index fac8cf5..98ed61f 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1727,13 +1727,15 @@ header->asl_compiler_revision = asl_revision; fadt->FADT_MinorVersion = get_acpi_fadt_minor_version(); - fadt->firmware_ctrl = (unsigned long)facs; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; + if ((uintptr_t)facs < UINT32_MAX)) + fadt->firmware_ctrl = (unsigned long)facs; + fadt->x_firmware_ctl_l = (uint32_t)(uintptr_t)facs; + fadt->x_firmware_ctl_h =; (uint32_t)((uintptr_t)facs >> 32); - fadt->dsdt = (unsigned long)dsdt; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; + if ((uintptr_t)dsdt < UINT32_MAX) + fadt->dsdt = (unsigned long)dsdt; + fadt->x_dsdt_l = (uint32_t)(uintptr_t)dsdt; + fadt->x_dsdt_h = (uint32_t)((uintptr_t)dsdt >> 32); /* should be 0 ACPI 3.0 */ fadt->reserved = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/76179?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84ab0068e8409a5e525ddc781347087680d80640 Gerrit-Change-Number: 76179 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: acpi.c: Guard FACS generation
by Arthur Heymans (Code Review) 29 Jun '23

29 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76178?usp=email ) Change subject: acpi.c: Guard FACS generation ...................................................................... acpi.c: Guard FACS generation It's not expected that non-x86 arch implement x86 style sleep states and resume. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I7a1f36616e7f6adb021625e62e0fdf81864c7ac3 --- M src/acpi/acpi.c 1 file changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/76178/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index e0e72f7..fac8cf5 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -2050,12 +2050,14 @@ acpi_write_rsdt(rsdt, oem_id, oem_table_id); acpi_write_xsdt(xsdt, oem_id, oem_table_id); - printk(BIOS_DEBUG, "ACPI: * FACS\n"); current = ALIGN_UP(current, 64); - facs = (acpi_facs_t *)current; - current += sizeof(acpi_facs_t); - current = acpi_align_current(current); - acpi_create_facs(facs); + if (ENV_X86) { + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *)current; + current += sizeof(acpi_facs_t); + current = acpi_align_current(current); + acpi_create_facs(facs); + } printk(BIOS_DEBUG, "ACPI: * DSDT\n"); dsdt = (acpi_header_t *)current; -- To view, visit https://review.coreboot.org/c/coreboot/+/76178?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a1f36616e7f6adb021625e62e0fdf81864c7ac3 Gerrit-Change-Number: 76178 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/nissa/var/gothrax: Add GPIO table for gothrax
by 9elements QA (Code Review) 29 Jun '23

29 Jun '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75872?usp=email ) Change subject: mb/google/nissa/var/gothrax: Add GPIO table for gothrax ...................................................................... Patch Set 10: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 8 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/171113 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/171111 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/171110 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/171109 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/171108 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/171107 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/171106 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/171105 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/171104 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/171103 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/171102 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/171101 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/171100 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/171099 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/171098 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/171097 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/75872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If852c7a30edb9fb778872414cb15dc3446aebc55 Gerrit-Change-Number: 75872 Gerrit-PatchSet: 10 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 18:28:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/phoenix/Makefile.inc: Pass APOB_NV address as offset
by Fred Reitberger (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Felix Held, Jason Glenesk, Matt DeVillier. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76162?usp=email ) Change subject: soc/amd/phoenix/Makefile.inc: Pass APOB_NV address as offset ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/76162?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f710f12cc5d933a75840dbce1c4bad0c2ea04cc Gerrit-Change-Number: 76162 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Jun 2023 18:22:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: amdfwtool: Allow bios table source addresses to select base
by Fred Reitberger (Code Review) 29 Jun '23

29 Jun '23

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76163?usp=email ) Change subject: amdfwtool: Allow bios table source addresses to select base ...................................................................... amdfwtool: Allow bios table source addresses to select base Addresses passed to register_bios_fw_addr src_str already have a '0x' prefix for hex values. Forcing the base to 16 causes improper conversion when decimal addresses are passed in. Setting the 'base' parameter to '0' lets strtoull automatically select the correct base from the prefix. TEST=timeless builds identical for chausie and majolica Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I45474600048a33ad186ba4d1baed7b5891ffdefe --- M util/amdfwtool/amdfwtool.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/76163/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 1b2b005..4164c19 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1715,7 +1715,7 @@ continue; if (src_str) - amd_bios_table[i].src = strtoull(src_str, NULL, 16); + amd_bios_table[i].src = strtoull(src_str, NULL, 0); if (dst_str) amd_bios_table[i].dest = strtoull(dst_str, NULL, 16); if (size_str) -- To view, visit https://review.coreboot.org/c/coreboot/+/76163?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45474600048a33ad186ba4d1baed7b5891ffdefe Gerrit-Change-Number: 76163 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C ...
by CoolStar (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: CoolStar, Martin Roth, Matt DeVillier, Stefan Reinauer. Hello Martin Roth, Matt DeVillier, Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76159?usp=email to look at the new patch set (#5). Change subject: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver ...................................................................... mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver This is a brand new I2C driver that is designed specifically for the Pixel 2013 chromebook (LINK). The GMBus interface on the IGPU is an i2c-compatible interface, but AFAIK only Link has touch devices attached in this way. On Windows, the PCIe device for the IGP is owned by the Intel proprietary driver, hence a separate ACPI device has to be added for the I2C driver arbitrator to attach to. The MMIO method is used instead of _CRS so that Windows does not try to assign ownership of the resource to our device (even though we're using the MMIO registers at the same time as the IGP driver). Even though in theory 2 drivers accessing the same MMIO may cause problems, in testing, there has been no issues with sleep/wake/hibernate, updating/installing/uninstalling the IGP driver, or changing display resolutions with the i2c driver attached. The arbitrator is necessary as well, since even though there are multiple i2c buses, the MMIO registers are shared. Hence a shared lock is required for i2c access across the buses. The original Sleep Button devices are preserved for Linux due to the completely custom and non-standard implementation of the Windows driver in order to work around the non-standard nature of Link's hardware. Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475 Signed-off-by: CoolStar <coolstarorganization(a)gmail.com> --- M src/mainboard/google/link/acpi/mainboard.asl M src/mainboard/google/link/dsdt.asl M src/mainboard/google/link/onboard.h 3 files changed, 114 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/76159/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/76159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475 Gerrit-Change-Number: 76159 Gerrit-PatchSet: 5 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit June 2023