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Hello Martin Roth, Matt DeVillier, Stefan Reinauer, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver
......................................................................
mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver
This is a brand new I2C driver that is designed specifically for the
Pixel 2013 chromebook (LINK). The GMBus interface on the IGPU is an
i2c-compatible interface, but AFAIK only Link has touch devices
attached in this way.
On Windows, the PCIe device for the IGP is owned by the Intel
proprietary driver, hence a separate ACPI device has to be added for
the I2C driver arbitrator to attach to. The MMIO method is used instead
of _CRS so that Windows does not try to assign ownership of the
resource to our device (even though we're using the MMIO registers at
the same time as the IGP driver).
Even though in theory 2 drivers accessing the same MMIO may cause
problems, in testing, there has been no issues with
sleep/wake/hibernate, updating/installing/uninstalling the IGP driver,
or changing display resolutions with the i2c driver attached.
The arbitrator is necessary as well, since even though there are
multiple i2c buses, the MMIO registers are shared. Hence a shared lock
is required for i2c access across the buses.
The original Sleep Button devices are preserved for Linux due to the
completely custom and non-standard implementation of the Windows driver
in order to work around the non-standard nature of Link's hardware.
Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475
Signed-off-by: CoolStar <coolstarorganization(a)gmail.com>
---
M src/mainboard/google/link/acpi/mainboard.asl
M src/mainboard/google/link/dsdt.asl
M src/mainboard/google/link/onboard.h
3 files changed, 114 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/76159/6
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Change subject: soc/amd/phoenix: Remove TODO after review
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/phoenix/Kconfig:
https://review.coreboot.org/c/coreboot/+/76165/comment/63fa7f84_f04ecdde :
PS1, Line 40: # TODO: Check if this is still correct
this one can go as well
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Change subject: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76159/comment/64c89d25_71fa800d :
PS5, Line 7: for new Windows I2C driver
Excuse my ignorance, but is that driver implemented in ACPI or do you also need to install a driver on Microsoft Windows?
https://review.coreboot.org/c/coreboot/+/76159/comment/45e3f902_fae13234 :
PS5, Line 9: This is a brand new I2C driver that is designed specifically for the Pixel 2013 chromebook (LINK). The GMBus interface on the IGPU is an i2c-compatible interface, but AFAIK only Link has touch devices attached in this way.
:
: On Windows, the PCIe device for the IGP is owned by the Intel proprietary driver, hence a separate ACPI device has to be added for the I2C driver arbitrator to attach to. The MMIO method is used instead of _CRS so that Windows does not try to assign ownership of the resource to our device (even though we're using the MMIO registers at the same time as the IGP driver).
:
: Even though in theory 2 drivers accessing the same MMIO may cause problems, in testing, there has been no issues with sleep/wake/hibernate, updating/installing/uninstalling the IGP driver, or changing display resolutions with the i2c driver attached.
:
: The arbitrator is necessary as well, since even though there are multiple i2c buses, the MMIO registers are shared. Hence a shared lock is required for i2c access across the buses.
:
: The original Sleep Button devices are preserved for Linux due to the completely custom and non-standard implementation of the Windows driver in order to work around the non-standard nature of Link's hardware.
Please wrap lines after 72 characters.
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Change subject: util/crossgcc/buildgcc: Drop some superfluous comments
......................................................................
Abandoned
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Change subject: mb/google/kahlee: Add EC_HOST_EVENT_PANIC to SCI mask
......................................................................
Patch Set 3: Code-Review+2
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Change subject: acpi/acpi.c: Reduce boilerplate
......................................................................
Patch Set 3:
(3 comments)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/76127/comment/18f060f7_08ea6c15 :
PS3, Line 1875: acpi_header_t *dsdt_file = (acpi_header_t *)(*(acpi_header_t **)(dsdt_file_arg));
Is there a double cast?
https://review.coreboot.org/c/coreboot/+/76127/comment/dbdbfd9b_3c2b6880 :
PS3, Line 1904: * cbfs_unmap() uses mem_pool_free() which works correctly only
This reversed order is no longer honoured?
https://review.coreboot.org/c/coreboot/+/76127/comment/1a54d961_d5bfae00 :
PS3, Line 1914: acpi_header_t *slic_file = (acpi_header_t *)(*(acpi_header_t **)slic_file_arg);
same
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Change subject: acpi.c: Fix generating pointer to cb_tables located >4G
......................................................................
Patch Set 2:
(1 comment)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/76181/comment/fe20d00a_86c4e724 :
PS2, Line 572: MEM_RSRC_FLAG_MEM_READ_WRITE
Write?
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Change subject: acpi.c: Fix generating pointer to cb_tables located >4G
......................................................................
acpi.c: Fix generating pointer to cb_tables located >4G
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I1bc553b18d08cee502b765166227810f8e619631
---
M src/acpi/acpi.c
1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/76181/2
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......................................................................
Patch Set 1: Code-Review+2
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