coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: soc/intel/meteorlake: Report CPU clock info
by Wonkyu Kim (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Felix Singer, Hannah Williams, Jakub Czapiga, Jamie Ryu, Kapil Porwal, Subrata Banik, Tarun Tuli. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76124?usp=email ) Change subject: soc/intel/meteorlake: Report CPU clock info ...................................................................... Patch Set 10: (1 comment) Patchset: PS5: > > The ramstage print value can be max turbo or other max cpu frequency. […] This log can provide info to identify right SKU info for debugging. We have different SKUs with different default CPU frequencies and same default CPU frequency with different max turbo frequencies. -- To view, visit https://review.coreboot.org/c/coreboot/+/76124?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b056fb8db04eca345dd7a240d03463de7c59fc2 Gerrit-Change-Number: 76124 Gerrit-PatchSet: 10 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 23:05:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/*: Utilize get_fmap_value() Makefile function where possible
by Matt DeVillier (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Raul Rangel. Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76168?usp=email ) Change subject: soc/amd/*: Utilize get_fmap_value() Makefile function where possible ...................................................................... soc/amd/*: Utilize get_fmap_value() Makefile function where possible Replace: $(shell awk '$$2 == "xyz" {print $$3}' $(obj)/fmap_config.h) with: $(call get_fmap_value, xyz) to improve code readability/maintainability. Change-Id: If6859108c7d5611a63fc38909dc75195bfb1d59a Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/glinda/Makefile.inc M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/phoenix/Makefile.inc M src/soc/amd/picasso/Makefile.inc 5 files changed, 39 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/76168/1 diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 062a19d..bf9711c 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -59,12 +59,10 @@ AMD_FW_AB_POSITION := 0x40 CEZANNE_FW_A_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value, FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) CEZANNE_FW_B_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value, FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) # # PSP Directory Table items # @@ -130,8 +128,8 @@ # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_SIZE=$(call get_fmap_value, FMAP_SECTION_RW_MRC_CACHE_SIZE) +APOB_NV_BASE=$(call get_fmap_value, FMAP_SECTION_RW_MRC_CACHE_START) ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) # type = 0x6B - PSP Shared memory location diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index 47c121e..025474b 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -62,12 +62,10 @@ AMD_FW_AB_POSITION := 0x40 GLINDA_FW_A_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value, FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) GLINDA_FW_B_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value, FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) # # PSP Directory Table items # @@ -129,8 +127,8 @@ # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_SIZE=$(call get_fmap_value, FMAP_SECTION_RW_MRC_CACHE_SIZE) +APOB_NV_BASE=$(call get_fmap_value, FMAP_SECTION_RW_MRC_CACHE_START) ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) # type = 0x6B - PSP Shared memory location @@ -146,11 +144,11 @@ ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) SIGNED_AMDFW_A_POSITION=$(call int-subtract, \ - $(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) + $(call get_fmap_value, FMAP_SECTION_SIGNED_AMDFW_A_START) \ + $(call get_fmap_value, FMAP_SECTION_FLASH_START)) SIGNED_AMDFW_B_POSITION=$(call int-subtract, \ - $(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) + $(call get_fmap_value, FMAP_SECTION_SIGNED_AMDFW_B_START) \ + $(call get_fmap_value, FMAP_SECTION_FLASH_START)) SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.signed SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.signed endif # CONFIG_SEPARATE_SIGNED_PSPFW diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index ac7ec6d..b2a169b 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -62,12 +62,10 @@ AMD_FW_AB_POSITION := 0x80 MENDOCINO_FW_A_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value, FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) MENDOCINO_FW_B_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value, FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) MENDOCINO_FW_BODY_OFFSET := 0x100 @@ -132,14 +130,14 @@ # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_SIZE=$(call get_fmap_value, FMAP_SECTION_RW_MRC_CACHE_SIZE) +APOB_NV_BASE=$(call get_fmap_value, FMAP_SECTION_RW_MRC_CACHE_START) ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE),y) # On boards with recovery MRC cache, point type 0x63 entry to RECOVERY_MRC_CACHE. # Else use RW_MRC_CACHE. This entry will be added in the RO section. -APOB_NV_RO_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_RO_BASE=$(shell awk '$$2 == "FMAP_SECTION_RECOVERY_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_RO_SIZE=$(call get_fmap_value, FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE) +APOB_NV_RO_BASE=$(call get_fmap_value, FMAP_SECTION_RECOVERY_MRC_CACHE_START) else APOB_NV_RO_SIZE=$(APOB_NV_SIZE) APOB_NV_RO_BASE=$(APOB_NV_BASE) @@ -159,11 +157,11 @@ ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) SIGNED_AMDFW_A_POSITION=$(call int-subtract, \ - $(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) + $(call get_fmap_value, FMAP_SECTION_SIGNED_AMDFW_A_START) \ + $(call get_fmap_value, FMAP_SECTION_FLASH_START)) SIGNED_AMDFW_B_POSITION=$(call int-subtract, \ - $(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) + $(call get_fmap_value, FMAP_SECTION_SIGNED_AMDFW_B_START) \ + $(call get_fmap_value, FMAP_SECTION_FLASH_START)) SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.body.signed SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.body.signed endif # CONFIG_SEPARATE_SIGNED_PSPFW diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc index 0945830..1745479 100644 --- a/src/soc/amd/phoenix/Makefile.inc +++ b/src/soc/amd/phoenix/Makefile.inc @@ -65,12 +65,10 @@ AMD_FW_AB_POSITION := 0x40 PHOENIX_FW_A_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value, FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) PHOENIX_FW_B_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value, FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) # # PSP Directory Table items # @@ -132,21 +130,21 @@ # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_SIZE=$(call get_fmap_value, FMAP_SECTION_RW_MRC_CACHE_SIZE) +APOB_NV_BASE=$(call get_fmap_value, FMAP_SECTION_RW_MRC_CACHE_START) ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE),y) # On boards with recovery MRC cache, point type 0x63 entry to RECOVERY_MRC_CACHE. # Else use RW_MRC_CACHE. This entry will be added in the RO section. -APOB_NV_RO_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_RO_BASE=$(shell awk '$$2 == "FMAP_SECTION_RECOVERY_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_RO_SIZE=$(call get_fmap_value, FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE) +APOB_NV_RO_BASE=$(call get_fmap_value, FMAP_SECTION_RECOVERY_MRC_CACHE_START) else APOB_NV_RO_SIZE=$(APOB_NV_SIZE) APOB_NV_RO_BASE=$(APOB_NV_BASE) endif ifeq ($(CONFIG_AMDFW_SPLIT),y) -FMAP_AMDFW_BODY_LOCATION=$(shell awk '$$2 == "FMAP_SECTION_AMDFWBODY_START" {print $$3}' $(obj)/fmap_config.h) +FMAP_AMDFW_BODY_LOCATION=$(call get_fmap_value, FMAP_SECTION_AMDFWBODY_START) endif ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) @@ -163,11 +161,11 @@ ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW),y) SIGNED_AMDFW_A_POSITION=$(call int-subtract, \ - $(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) + $(call get_fmap_value, FMAP_SECTION_SIGNED_AMDFW_A_START) \ + $(call get_fmap_value, FMAP_SECTION_FLASH_START)) SIGNED_AMDFW_B_POSITION=$(call int-subtract, \ - $(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) + $(call get_fmap_value, FMAP_SECTION_SIGNED_AMDFW_B_START) \ + $(call get_fmap_value, FMAP_SECTION_FLASH_START)) SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.signed SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.signed endif # CONFIG_SEPARATE_SIGNED_PSPFW diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index cb42582..44e58da 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -65,12 +65,10 @@ AMD_FW_AB_POSITION := 0x40 PICASSO_FW_A_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value, FMAP_SECTION_FW_MAIN_A_START) $(AMD_FW_AB_POSITION)) PICASSO_FW_B_POSITION=$(call int-add, \ - $(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \ - $(AMD_FW_AB_POSITION)) + $(call get_fmap_value, FMAP_SECTION_FW_MAIN_B_START) $(AMD_FW_AB_POSITION)) # # PSP Directory Table items @@ -110,8 +108,8 @@ # type = 0x4 # The flashmap section used for this is expected to be named PSP_NVRAM -PSP_NVRAM_BASE=$(shell awk '$$2 == "FMAP_SECTION_PSP_NVRAM_START" {print $$3}' $(obj)/fmap_config.h) -PSP_NVRAM_SIZE=$(shell awk '$$2 == "FMAP_SECTION_PSP_NVRAM_SIZE" {print $$3}' $(obj)/fmap_config.h) +PSP_NVRAM_BASE=$(call get_fmap_value, FMAP_SECTION_PSP_NVRAM_START) +PSP_NVRAM_SIZE=$(call get_fmap_value, FMAP_SECTION_PSP_NVRAM_SIZE) # type = 0x7 # RSA 2048 signature @@ -132,8 +130,8 @@ PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -Wl $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE -APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_SIZE=$(call get_fmap_value, FMAP_SECTION_RW_MRC_CACHE_SIZE) +APOB_NV_BASE=$(call get_fmap_value, FMAP_SECTION_RW_MRC_CACHE_START) ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) # type = 0x6B - PSP Shared memory location -- To view, visit https://review.coreboot.org/c/coreboot/+/76168?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6859108c7d5611a63fc38909dc75195bfb1d59a Gerrit-Change-Number: 76168 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: Makefile.inc: relocate get_fmap_value() here from soc/intel/common/bl...
by Matt DeVillier (Code Review) 29 Jun '23

29 Jun '23

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76167?usp=email ) Change subject: Makefile.inc: relocate get_fmap_value() here from soc/intel/common/block/cse ...................................................................... Makefile.inc: relocate get_fmap_value() here from soc/intel/common/block/cse Move this function to the root Makefile.inc since other Makefiles use the exact same function call. Will allow for deduplication in AMD SoC Makefiles in a follow-on commit. Change-Id: I56a50e21b27a4cd6ce1a08a3aea338c63322a6b2 Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M Makefile.inc M src/soc/intel/common/block/cse/Makefile.inc 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/76167/1 diff --git a/Makefile.inc b/Makefile.inc index ab57abd..9a34c61 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -146,6 +146,7 @@ # tolower: returns the value in all lowercase # toupper: returns the value in all uppercase # ws_to_under: returns the value with any whitespace changed to underscores +# get_fmap_value returns the value of a given FMAP field from fmap_config.h _toint=$(shell printf "%d" $1) _tohex=$(shell printf 0x"%x" $1) _int-add2=$(shell expr $(call _toint,$1) + $(call _toint,$2)) @@ -165,6 +166,7 @@ tolower=$(shell echo '$1' | tr '[:upper:]' '[:lower:]') toupper=$(shell echo '$1' | tr '[:lower:]' '[:upper:]') ws_to_under=$(shell echo '$1' | tr ' \t' '_') +get_fmap_value=$(shell awk '$$2 == "$1" {print $$3}' $(obj)/fmap_config.h) ####################################################################### # Helper functions for ramstage postprocess diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 3e11279..ad15dc4 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -24,7 +24,6 @@ CSE_FPT_INPUT=$(call cse_input_path,$(CONFIG_CSE_FPT_FILE)) CSE_DATA_INPUT=$(call cse_input_path,$(CONFIG_CSE_DATA_FILE)) -get_fmap_value=$(shell awk '$$2 == "$1" {print $$3}' $(obj)/fmap_config.h) get_cse_region_offset=$(call int-subtract,$(call get_fmap_value,$(1)) $(CSE_LAYOUT_OFFSET)) CSE_LAYOUT_OFFSET=$(call get_fmap_value,FMAP_SECTION_CSE_LAYOUT_START) -- To view, visit https://review.coreboot.org/c/coreboot/+/76167?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56a50e21b27a4cd6ce1a08a3aea338c63322a6b2 Gerrit-Change-Number: 76167 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: acpi.c: Guard FACS generation
by Felix Singer (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Kyösti Mälkki, Lance Zhao, Nico Huber, Tim Wawrzynczak. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76178?usp=email ) Change subject: acpi.c: Guard FACS generation ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76178?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a1f36616e7f6adb021625e62e0fdf81864c7ac3 Gerrit-Change-Number: 76178 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Jun 2023 21:57:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: acpi/acpi.h: Add MADT GIC structures
by Felix Singer (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Nico Huber, Tim Wawrzynczak. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76131?usp=email ) Change subject: acpi/acpi.h: Add MADT GIC structures ...................................................................... Patch Set 1: (7 comments) File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/76131/comment/15b38d56_a51657dc : PS1, Line 767: parking_protocol_persion typo: `parking_protocol_version` https://review.coreboot.org/c/coreboot/+/76131/comment/4ea36946_292dc0ca : PS1, Line 781: MADT GICC `acpi_madt_gicc_t`? https://review.coreboot.org/c/coreboot/+/76131/comment/3e5a2739_ad38ccc8 : PS1, Line 794: acpi_gicd_t `acpi_madt_gicd_t` ? https://review.coreboot.org/c/coreboot/+/76131/comment/cd3bd9c0_d3fee456 : PS1, Line 816: apci_girc typo: `acpi_girc` https://review.coreboot.org/c/coreboot/+/76131/comment/a0fba9ed_a01f2491 : PS1, Line 823: acpi_gicr_t `acpi_madt_gicr_t`? https://review.coreboot.org/c/coreboot/+/76131/comment/fe78d620_2c04068f : PS1, Line 826: apci_gic_its typo: `acpi_gic_its` https://review.coreboot.org/c/coreboot/+/76131/comment/af82aec0_e496ff3e : PS1, Line 834: acpi_gic_its_t `acpi_madt_gic_its_t`? -- To view, visit https://review.coreboot.org/c/coreboot/+/76131?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e6544c956cb3d516d2e5900357af9ae8976cc8e Gerrit-Change-Number: 76131 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Jun 2023 21:37:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/phoenix/Makefile.inc: Pass APOB_NV address as offset
by Matt DeVillier (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76162?usp=email ) Change subject: soc/amd/phoenix/Makefile.inc: Pass APOB_NV address as offset ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/phoenix/Makefile.inc: https://review.coreboot.org/c/coreboot/+/76162/comment/922f3fd7_94436a82 : PS2, Line 138: $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) does it make sense to split this line out / save as a variable since it's being used twice (potentially)? -- To view, visit https://review.coreboot.org/c/coreboot/+/76162?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f710f12cc5d933a75840dbce1c4bad0c2ea04cc Gerrit-Change-Number: 76162 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 29 Jun 2023 21:17:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex/var/rex0: Change touch over spi interrupt trigger to edge
by Eran Mitrani (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Eric Lai, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun Tuli. Eran Mitrani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76116?usp=email ) Change subject: mb/google/rex/var/rex0: Change touch over spi interrupt trigger to edge ...................................................................... Patch Set 3: (1 comment) This change is ready for review. File src/mainboard/google/rex/variants/rex0/include/variant/acpi/hid_spi_elan.asl: https://review.coreboot.org/c/coreboot/+/76116/comment/abdba4a4_6500e86c : PS3, Line 42: Edge > It is mentioned in the hid over spi spec here: https://www.microsoft.com/en-us/download/details. […] Since I2C requires Level, and SPI requires Edge, I modified it to be configured to edge/level based on fw_config -- To view, visit https://review.coreboot.org/c/coreboot/+/76116?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78937af22df22d80a702477b6790a7aa40d782a4 Gerrit-Change-Number: 76116 Gerrit-PatchSet: 3 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 21:17:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eran Mitrani <mitrani(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C ...
by Matt DeVillier (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Martin Roth, Paul Menzel, Stefan Reinauer. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76159?usp=email ) Change subject: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76159/comment/acb4c7d1_95d56c34 : PS5, Line 7: for new Windows I2C driver > Excuse my ignorance, but is that driver implemented in ACPI or do you also need to install a driver […] the drivers are not implemented in ACPI, they are OS-specific and interface with the hardware using the resources defined via ACPI -- To view, visit https://review.coreboot.org/c/coreboot/+/76159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475 Gerrit-Change-Number: 76159 Gerrit-PatchSet: 5 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2023 21:12:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C ...
by CoolStar (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Martin Roth, Matt DeVillier, Paul Menzel, Stefan Reinauer. CoolStar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76159?usp=email ) Change subject: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/76159/comment/effc2a28_b8b2d28a : PS5, Line 7: for new Windows I2C driver > Excuse my ignorance, but is that driver implemented in ACPI or do you also need to install a driver […] driver needs to be installed on Windows https://review.coreboot.org/c/coreboot/+/76159/comment/7e4d7b71_7bbd57de : PS5, Line 9: This is a brand new I2C driver that is designed specifically for the Pixel 2013 chromebook (LINK). The GMBus interface on the IGPU is an i2c-compatible interface, but AFAIK only Link has touch devices attached in this way. : : On Windows, the PCIe device for the IGP is owned by the Intel proprietary driver, hence a separate ACPI device has to be added for the I2C driver arbitrator to attach to. The MMIO method is used instead of _CRS so that Windows does not try to assign ownership of the resource to our device (even though we're using the MMIO registers at the same time as the IGP driver). : : Even though in theory 2 drivers accessing the same MMIO may cause problems, in testing, there has been no issues with sleep/wake/hibernate, updating/installing/uninstalling the IGP driver, or changing display resolutions with the i2c driver attached. : : The arbitrator is necessary as well, since even though there are multiple i2c buses, the MMIO registers are shared. Hence a shared lock is required for i2c access across the buses. : : The original Sleep Button devices are preserved for Linux due to the completely custom and non-standard implementation of the Windows driver in order to work around the non-standard nature of Link's hardware. > Please wrap lines after 72 characters. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475 Gerrit-Change-Number: 76159 Gerrit-PatchSet: 7 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Thu, 29 Jun 2023 21:10:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C ...
by CoolStar (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: CoolStar, Martin Roth, Matt DeVillier, Stefan Reinauer. Hello Martin Roth, Matt DeVillier, Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76159?usp=email to look at the new patch set (#7). Change subject: mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver ...................................................................... mb/google/link: rework TP/TS ACPI to add support for new Windows I2C driver This is a brand new I2C driver that is designed specifically for the Pixel 2013 chromebook (LINK). The GMBus interface on the IGPU is an i2c-compatible interface, but AFAIK only Link has touch devices attached in this way. On Windows, the PCIe device for the IGP is owned by the Intel proprietary driver, hence a separate ACPI device has to be added for the I2C driver arbitrator to attach to. The MMIO method is used instead of _CRS so that Windows does not try to assign ownership of the resource to our device (even though we're using the MMIO registers at the same time as the IGP driver). Even though in theory 2 drivers accessing the same MMIO may cause problems, in testing, there has been no issues with sleep/wake/hibernate, updating/installing/uninstalling the IGP driver, or changing display resolutions with the i2c driver attached. The arbitrator is necessary as well, since even though there are multiple i2c buses, the MMIO registers are shared. Hence a shared lock is required for i2c access across the buses. The original Sleep Button devices are preserved for Linux due to the completely custom and non-standard implementation of the Windows driver in order to work around the non-standard nature of Link's hardware. Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475 Signed-off-by: CoolStar <coolstarorganization(a)gmail.com> --- M src/mainboard/google/link/acpi/mainboard.asl M src/mainboard/google/link/dsdt.asl M src/mainboard/google/link/onboard.h 3 files changed, 114 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/76159/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/76159?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475 Gerrit-Change-Number: 76159 Gerrit-PatchSet: 7 Gerrit-Owner: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: CoolStar <coolstarorganization(a)gmail.com> Gerrit-MessageType: newpatchset

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