coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

1 participants
5387 discussions

[S] Change in coreboot[master]: mb/google/dedede/var/dibbi: Update power limits
by 9elements QA (Code Review) 29 Jun '23

29 Jun '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75681?usp=email ) Change subject: mb/google/dedede/var/dibbi: Update power limits ...................................................................... Patch Set 14: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 8 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/171096 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/171094 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/171093 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/171092 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/171091 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/171090 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/171089 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/171088 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/171087 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/171086 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/171085 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/171084 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/171083 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/171082 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/171081 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/171080 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/75681?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6 Gerrit-Change-Number: 75681 Gerrit-PatchSet: 14 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Chia-Ling Hou <chia-ling.hou(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 29 Jun 2023 18:05:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: acpi/acpi.c: Don't set MADT lapic addr on !ENV_X86
by Arthur Heymans (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Kyösti Mälkki, Lance Zhao, Tim Wawrzynczak. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76070?usp=email ) Change subject: acpi/acpi.c: Don't set MADT lapic addr on !ENV_X86 ...................................................................... Patch Set 1: (1 comment) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/76070/comment/c665a451_e7890c85 : PS1, Line 161: if (ENV_X86) > I'm fine with this, but one might consider moving this and the COMMON_MADT conditionals below over to acpi_apic.c. Current expectation is to not see LAPIC or IOAPIC entries for ARM at least? I plan on adding ACPI_HAVE_GIC... here to implement the ARM equivalents. I guess it's safe to say that those will be arch bound. Maybe that can be made explicit in Kconfig? -- To view, visit https://review.coreboot.org/c/coreboot/+/76070?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e5032fd02af7e8e9ffd2e20aa214a8392ab6335 Gerrit-Change-Number: 76070 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 18:01:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <inforichland(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: [SKETCH] acpigen: Pipe data in acpigen_dsm_uuid_enum_functions()
by Arthur Heymans (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Lance Zhao, Nico Huber. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76092?usp=email ) Change subject: [SKETCH] acpigen: Pipe data in acpigen_dsm_uuid_enum_functions() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76092?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad15af08c39d0ddb477216bc3e93bc799899bb0e Gerrit-Change-Number: 76092 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 29 Jun 2023 17:57:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: acpi/acpigen.c: Be explicit about char sign
by Arthur Heymans (Code Review) 29 Jun '23

29 Jun '23

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76006?usp=email ) Change subject: acpi/acpigen.c: Be explicit about char sign ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/76006/comment/a406455e_5f2d88aa : PS1, Line 9: is architecture : dependent > huh, i didn't expect this to be the case Undefined behavior in C is sometimes in the news :-) : https://www.phoronix.com/news/Linux-6.2-funsigned-char . Maybe it's worth fixing it like the kernel to unravel bugs. -- To view, visit https://review.coreboot.org/c/coreboot/+/76006?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53b99835b2ffec5d752fc531fd59e4715f61aced Gerrit-Change-Number: 76006 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 17:56:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/dedede: Support variant specific power limits
by 9elements QA (Code Review) 29 Jun '23

29 Jun '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75680?usp=email ) Change subject: mb/google/dedede: Support variant specific power limits ...................................................................... Patch Set 12: Automatic boot test returned (PASS/FAIL/TOTAL): 8 / 8 / 16 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/171079 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/171077 FAIL: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/171076 FAIL: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/171075 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/171074 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/171073 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/171072 FAIL: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/171071 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/171070 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/171069 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/171068 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/171067 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/171066 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/171065 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/171064 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/171063 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/75680?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I583c930379233322c41027805369f81d02000ee7 Gerrit-Change-Number: 75680 Gerrit-PatchSet: 12 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Chia-Ling Hou <chia-ling.hou(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 29 Jun 2023 17:53:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: mb/google/kahlee: Add EC_HOST_EVENT_PANIC to SCI mask
by Karthik Ramasubramanian (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Edward Hill, Edward Hill, Jason Nien, Martin Roth, Raul Rangel, Rob Barnes. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75323?usp=email ) Change subject: mb/google/kahlee: Add EC_HOST_EVENT_PANIC to SCI mask ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75323?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8eeb5c0935d0531c21bcf4cd3d4fd9dc80b54f79 Gerrit-Change-Number: 75323 Gerrit-PatchSet: 3 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Edward Hill <ecgh(a)chromium.org> Gerrit-Reviewer: Edward Hill <ecgh(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Edward Hill <ecgh(a)google.com> Gerrit-Attention: Edward Hill <ecgh(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 17:46:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: soc/amd/phoenix/Kconfig: Drop TODO for FSP_DMI_TABLES
by Matt DeVillier (Code Review) 29 Jun '23

29 Jun '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76109?usp=email ) Change subject: soc/amd/phoenix/Kconfig: Drop TODO for FSP_DMI_TABLES ...................................................................... soc/amd/phoenix/Kconfig: Drop TODO for FSP_DMI_TABLES BUG=b:288520486 TEST=In kernel, dump `dmidecode -t 17`. Change-Id: I1a8aae12ec449fe921814a6e363306fced969367 Signed-off-by: Konrad Adamczyk <konrada(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76109 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/phoenix/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Fred Reitberger: Looks good to me, approved Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 942c931..4ab26ee 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -78,7 +78,7 @@ select SOC_AMD_COMMON_BLOCK_UCODE select SOC_AMD_COMMON_BLOCK_XHCI select SOC_AMD_COMMON_FSP_CCX_CPPC_HOB # TODO: Check if this is still correct - select SOC_AMD_COMMON_FSP_DMI_TABLES # TODO: Check if this is still correct + select SOC_AMD_COMMON_FSP_DMI_TABLES select SOC_AMD_COMMON_FSP_PCI # TODO: Check if this is still correct select SOC_AMD_COMMON_FSP_PRELOAD_FSPS select SSE2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76109?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a8aae12ec449fe921814a6e363306fced969367 Gerrit-Change-Number: 76109 Gerrit-PatchSet: 3 Gerrit-Owner: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[master]: soc/amd/common/fsp: Fix dimm_num assignment
by Matt DeVillier (Code Review) 29 Jun '23

29 Jun '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76108?usp=email ) Change subject: soc/amd/common/fsp: Fix dimm_num assignment ...................................................................... soc/amd/common/fsp: Fix dimm_num assignment The dimm_num shall be dimm, not channel. BUG=b:288520486 TEST=In kernel, see output from `dmidecode -t 17`. Observe that Locator reflects proper location of the module. Change-Id: Id876a5c245ed1a145c930b3456830d7b42780b74 Signed-off-by: Konrad Adamczyk <konrada(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76108 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/common/fsp/dmi.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/common/fsp/dmi.c b/src/soc/amd/common/fsp/dmi.c index a671476..408c0e4 100644 --- a/src/soc/amd/common/fsp/dmi.c +++ b/src/soc/amd/common/fsp/dmi.c @@ -226,7 +226,7 @@ print_dmi_info(type17_dmi_info); dimm_info = &mem_info->dimm[dimm_cnt]; dimm_info->channel_num = channel; - dimm_info->dimm_num = channel; + dimm_info->dimm_num = dimm; transfer_memory_info(type17_dmi_info, dimm_info); if (use_cbi_part_number) { /* mem_info is memset to 0 above, so it's -- To view, visit https://review.coreboot.org/c/coreboot/+/76108?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id876a5c245ed1a145c930b3456830d7b42780b74 Gerrit-Change-Number: 76108 Gerrit-PatchSet: 3 Gerrit-Owner: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: soc/intel/meteorlake: remove unused tcss mailbox code
by Matt DeVillier (Code Review) 29 Jun '23

29 Jun '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76126?usp=email ) Change subject: soc/intel/meteorlake: remove unused tcss mailbox code ...................................................................... soc/intel/meteorlake: remove unused tcss mailbox code In mtl, there is no MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE So, this patch removes unused code related to MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE ADL also removes this code, see cl:62861 BUG=b:288976547 TEST=Tested on Screebo and DP/USB are working as expected after suspend/resume Change-Id: I5a4b26c38ec3f5fe1d81fd70f8c2196d0e5b84c3 Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76126 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/meteorlake/acpi/tcss.asl 1 file changed, 1 insertion(+), 124 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl index 1d562c9..7b83b5f 100644 --- a/src/soc/intel/meteorlake/acpi/tcss.asl +++ b/src/soc/intel/meteorlake/acpi/tcss.asl @@ -391,100 +391,6 @@ Return (0) } - /* - * Method to send pCode MailBox command TCSS_DEVEN_MAILBOX_SUBCMD_GET_STATUS - * - * Result will be updated in DATA[1:0] - * DATA[0:0] TCSS_DEVEN_CURRENT_STATE: - * 0 - TCSS Deven in normal state. - * 1 - TCSS Deven is cleared by BIOS Mailbox request. - * DATA[1:1] TCSS_DEVEN_REQUEST_STATUS: - * 0 - IDLE. TCSS DEVEN has reached its final requested state. - * 1 - In Progress. TCSS DEVEN is currently in progress of switching state - * according to given request (bit 0 reflects source state). - * - * Return 0x00 - TCSS Deven in normal state - * 0x01 - TCSS Deven is cleared by BIOS Mailbox request - * 0x1x - TCSS Deven is in progress of switching state according to given request - * 0xFE - Command timeout - * 0xFF - Command corrupt - */ - Method (DSGS, 0) - { - If ((PMBY () == 0)) { - PMBC = MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE - PSCM = TCSS_DEVEN_MAILBOX_SUBCMD_GET_STATUS - PMBR = 1 - If (PMBY () == 0) { - Local0 = PMBD - Local1 = PMBC - Stall (10) - If ((Local0 != PMBD) || (Local1 != PMBC)) { - Printf("pCode MailBox is corrupt.") - Return (0xFF) - } - Return (Local0) - } Else { - Printf("pCode MailBox is not ready.") - Return (0xFE) - } - } Else { - Printf("pCode MailBox is not ready.") - Return (0xFE) - } - } - - /* - * Method to send pCode MailBox command TCSS_DEVEN_MAILBOX_SUBCMD_TCSS_CHANGE_REQ - * - * Arg0 : 0 - Restore to previously saved value of TCSS DEVEN - * 1 - Save current TCSS DEVEN value and clear it - * - * Return 0x00 - MAILBOX_BIOS_CMD_CLEAR_TCSS_DEVEN command completed - * 0xFD - Input argument is invalid - * 0xFE - Command timeout - * 0xFF - Command corrupt - */ - Method (DSCR, 1) - { - If (Arg0 > 1) { - Printf("pCode MailBox is corrupt.") - Return (0xFD) - } - If ((PMBY () == 0)) { - PMBC = MAILBOX_BIOS_CMD_TCSS_DEVEN_INTERFACE - PSCM = TCSS_DEVEN_MAILBOX_SUBCMD_TCSS_CHANGE_REQ - PMBD = Arg0 - PMBR = 1 - If ((PMBY () == 0)) { - Local0 = PMBD - Local1 = PMBC - Stall (10) - If ((Local0 != PMBD) || (Local1 != PMBC)) { - Printf("pCode MailBox is corrupt.") - Return (0xFF) - } - /* Poll TCSS_DEVEN_REQUEST_STATUS, timeout value is 10ms. */ - Local0 = 0 - While ((DSGS () & 0x10) && (Local0 < 100)) { - Stall (100) - Local0++ - } - If (Local0 == 100) { - Printf("pCode MailBox is not ready.") - Return (0xFE) - } Else { - Return (0x00) - } - } Else { - Printf("pCode MailBox is not ready.") - Return (0xFE) - } - } Else { - Printf("pCode MailBox is not ready.") - Return (0xFE) - } - } /* From RegBar Base, IOM_TypeC_SW_configuration_1 is at offset 0x40 */ OperationRegion (IOMR, SystemMemory, IOM_BASE_ADDR, 0x100) @@ -681,21 +587,7 @@ } Else { - /* - * If the TCSS Deven is cleared by BIOS Mailbox request, then - * restore to previously saved value of TCSS DEVNE. - */ - Local0 = 0 - While (\_SB.PCI0.TXHC.VDID == 0xFFFFFFFF) { - If (DSGS () == 1) { - DSCR (0) - } - Local0++ - If (Local0 == 5) { - Printf("pCode mailbox command failed.") - Break - } - } + Printf("TCSS D3 exit."); } } Else { @@ -712,21 +604,6 @@ Return } - /* - * If the TCSS Deven in normal state, then Save current TCSS DEVEN value and - * clear it. - */ - Local0 = 0 - While (\_SB.PCI0.TXHC.VDID != 0xFFFFFFFF) { - If (DSGS () == 0) { - DSCR (1) - } - Local0++ - If (Local0 == 5) { - Printf("pCode mailbox command failed.") - Break - } - } /* Request IOM for D3 cold entry sequence. */ /* -- To view, visit https://review.coreboot.org/c/coreboot/+/76126?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a4b26c38ec3f5fe1d81fd70f8c2196d0e5b84c3 Gerrit-Change-Number: 76126 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: mb/google/nissa/var/gothrax: Add GPIO table for gothrax
by Matt DeVillier (Code Review) 29 Jun '23

29 Jun '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75872?usp=email ) Change subject: mb/google/nissa/var/gothrax: Add GPIO table for gothrax ...................................................................... mb/google/nissa/var/gothrax: Add GPIO table for gothrax Configure GPIOs according to schematics. BUG=b:287563817 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Change-Id: If852c7a30edb9fb778872414cb15dc3446aebc55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75872 Reviewed-by: Henry Sun <henrysun(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang(a)google.com> --- A src/mainboard/google/brya/variants/gothrax/Makefile.inc A src/mainboard/google/brya/variants/gothrax/gpio.c M src/mainboard/google/brya/variants/gothrax/include/variant/gpio.h 3 files changed, 102 insertions(+), 0 deletions(-) Approvals: Derek Huang: Looks good to me, approved Henry Sun: Looks good to me, but someone else must approve build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/gothrax/Makefile.inc b/src/mainboard/google/brya/variants/gothrax/Makefile.inc new file mode 100644 index 0000000..6c29346 --- /dev/null +++ b/src/mainboard/google/brya/variants/gothrax/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/gothrax/gpio.c b/src/mainboard/google/brya/variants/gothrax/gpio.c new file mode 100644 index 0000000..cc2ee73 --- /dev/null +++ b/src/mainboard/google/brya/variants/gothrax/gpio.c @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_CFG_GPO(GPP_H23, 1, DEEP), + /* H3 : WLAN_PCIE_WAKE_ODL */ + PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG), + /* E13 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO_LOCK(GPP_E13, 1, LOCK_CONFIG), + /* F12 : WWAN_RST_L */ + PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), + + /* A21 : GPP_A21 ==> USB_C1_AUX_DC_P */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), + /* A22 : GPP_A22 ==> USB_C1_AUX_DC_N */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + + /* B5 : SOC_I2C_SUB_SDA */ + PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG), + /* B6 : SOC_I2C_SUB_SCL */ + PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG), + + /* D3 : WCAM_RST_L */ + PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG), + /* D15 : EN_PP2800_WCAM_X */ + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), + /* D16 : EN_PP1800_PP1200_WCAM_X */ + PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), + + /* H22 : WCAM_MCLK_R */ + PAD_NC(GPP_H22, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* F12 : GSXDOUT ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + /* E13 : SRCCLKREQ1# ==> WWAN_EN */ + PAD_CFG_GPO(GPP_E13, 1, DEEP), + + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), + + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 0, DEEP), + /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + + /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */ + PAD_CFG_GPO(GPP_H13, 1, DEEP), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 1, DEEP), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brya/variants/gothrax/include/variant/gpio.h b/src/mainboard/google/brya/variants/gothrax/include/variant/gpio.h index c4fe342..f80f6ef 100644 --- a/src/mainboard/google/brya/variants/gothrax/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/gothrax/include/variant/gpio.h @@ -4,5 +4,8 @@ #define VARIANT_GPIO_H #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_E13 +#define WWAN_RST GPP_F12 +#define T2_OFF_MS 20 #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/75872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If852c7a30edb9fb778872414cb15dc3446aebc55 Gerrit-Change-Number: 75872 Gerrit-PatchSet: 10 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-MessageType: merged

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2023