coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: soc/intel/meteorlake: Add QS(C0) stepping CPU ID
by Matt DeVillier (Code Review) 29 Jun '23

29 Jun '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/76135?usp=email ) Change subject: soc/intel/meteorlake: Add QS(C0) stepping CPU ID ...................................................................... soc/intel/meteorlake: Add QS(C0) stepping CPU ID This patch adds CPU ID for C0 stepping (aka QS). DOC=#723567 TEST=Able to boot on C0 rvp (and rex) and get correct CPU Name in coreboot log. Change-Id: I53e3b197f2a0090e178877c1eef783b41670ca83 Signed-off-by: Musse Abdullahi <musse.abdullahi(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76135 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/cpu/intel/cpu_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/meteorlake/bootblock/report_platform.c 3 files changed, 3 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 2d64c5f..77b018f9 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -72,6 +72,7 @@ #define CPUID_METEORLAKE_A0_1 0xa06a0 #define CPUID_METEORLAKE_A0_2 0xa06a1 #define CPUID_METEORLAKE_B0 0xa06a2 +#define CPUID_METEORLAKE_C0 0xa06a4 #define CPUID_RAPTORLAKE_P_J0 0xb06a2 #define CPUID_RAPTORLAKE_P_Q0 0xb06a3 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 7466ff6..dfb4a04 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -35,6 +35,7 @@ { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_1, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_2, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_METEORLAKE_B0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_METEORLAKE_C0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_C0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_D0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0, CPUID_EXACT_MATCH_MASK }, diff --git a/src/soc/intel/meteorlake/bootblock/report_platform.c b/src/soc/intel/meteorlake/bootblock/report_platform.c index 3e8bc56..49d0661 100644 --- a/src/soc/intel/meteorlake/bootblock/report_platform.c +++ b/src/soc/intel/meteorlake/bootblock/report_platform.c @@ -20,6 +20,7 @@ { CPUID_METEORLAKE_A0_1, "MeteorLake A0" }, { CPUID_METEORLAKE_A0_2, "MeteorLake A0" }, { CPUID_METEORLAKE_B0, "MeteorLake B0" }, + { CPUID_METEORLAKE_C0, "MeteorLake C0" }, }; static struct { -- To view, visit https://review.coreboot.org/c/coreboot/+/76135?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53e3b197f2a0090e178877c1eef783b41670ca83 Gerrit-Change-Number: 76135 Gerrit-PatchSet: 2 Gerrit-Owner: Musse Abdullahi <musse.abdullahi(a)intel.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Musse Abdullahi <musse.abdullahi(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/dedede/var/dibbi: Update power limits
by Matt DeVillier (Code Review) 29 Jun '23

29 Jun '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75681?usp=email ) ( 12 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/dedede/var/dibbi: Update power limits ...................................................................... mb/google/dedede/var/dibbi: Update power limits Add ramstage.c in Makefile.inc and update Dibbi power limits in Dibbi ramstage.c. BUG=b:281479111 TEST=emerge-dedede coreboot and check psys and PLx value on dibbi Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com> Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75681 Reviewed-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/dibbi/Makefile.inc A src/mainboard/google/dedede/variants/dibbi/ramstage.c 2 files changed, 36 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved Reka Norman: Looks good to me, approved build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/dibbi/Makefile.inc b/src/mainboard/google/dedede/variants/dibbi/Makefile.inc index eb2c9bc..66f0263 100644 --- a/src/mainboard/google/dedede/variants/dibbi/Makefile.inc +++ b/src/mainboard/google/dedede/variants/dibbi/Makefile.inc @@ -1,3 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/dedede/variants/dibbi/ramstage.c b/src/mainboard/google/dedede/variants/dibbi/ramstage.c new file mode 100644 index 0000000..64510cc --- /dev/null +++ b/src/mainboard/google/dedede/variants/dibbi/ramstage.c @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> + +/* + * Psys_pmax considerations + * + * Given the hardware design in dibbi, the serial shunt resistor is 0.01ohm. + * The full scale of hardware PSYS signal 1.6v maps to system current 6.009A + * instead of real system power. The equation is shown below: + * PSYS = 1.6v ~= (0.01ohm x 6.009A) x 50 (INA213, gain 50V/V) x R631/(R631 + R638) + * R631/(R631 + R638) = 0.5325 = 36K / (36K + 31.6K) + * + * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping between system input + * current and the actual system power. Since there is no voltage information + * from PSYS, different voltage input would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax should be 15v x 6.009A = 90.135W + * For Type-C 20V, the Psys_pmax should be 20v x 6.009A = 120.18W + * For a barrel jack, the Psys_pmax should be 19v x 6.009A = 114.171W + * + * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading, + * and the Psys_pmax setting is 120W. Then IMVP9.1 can calculate the current system + * power = 120W * 5A / 6.009A = 100W, which is the actual system power. + */ +const struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 6009, + .bj_volts_mv = 19000, + .bj_power_w = 65, +}; + +void variant_devtree_update(void) +{ + variant_update_psys_power_limits(&psys_config); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/75681?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6 Gerrit-Change-Number: 75681 Gerrit-PatchSet: 14 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chia-Ling Hou <chia-ling.hou(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/dedede: Support variant specific power limits
by Matt DeVillier (Code Review) 29 Jun '23

29 Jun '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75680?usp=email ) Change subject: mb/google/dedede: Support variant specific power limits ...................................................................... mb/google/dedede: Support variant specific power limits With newer dedede design, it's required to config corresponding psyspmax, psyspl1, psyspl2, pl1 and pl2 by different kinds of adapter. BUG=b:281479111 TEST=emerge-dedede coreboot and check correct value on dibbi Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com> Change-Id: I583c930379233322c41027805369f81d02000ee7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75680 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Reka Norman <rekanorman(a)chromium.org> --- M src/mainboard/google/dedede/variants/baseboard/Makefile.inc M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/dedede/variants/baseboard/ramstage.c 3 files changed, 108 insertions(+), 0 deletions(-) Approvals: Sumeet R Pawnikar: Looks good to me, approved build bot (Jenkins): Verified Reka Norman: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/baseboard/Makefile.inc b/src/mainboard/google/dedede/variants/baseboard/Makefile.inc index 64a81f9..2c3f2f6 100644 --- a/src/mainboard/google/dedede/variants/baseboard/Makefile.inc +++ b/src/mainboard/google/dedede/variants/baseboard/Makefile.inc @@ -4,5 +4,6 @@ romstage-y += memory.c ramstage-y += gpio.c +ramstage-y += ramstage.c smm-y += gpio.c diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index edb2b07..b258481 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -48,6 +48,30 @@ /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); +struct psys_config { + /* + * The efficiency of type-c chargers + * For example, 'efficiency = 97' means setting 97% of max power to account for + * cable loss and FET Rdson loss in the path from the source. + */ + unsigned int efficiency; + + /* The maximum current maps to the Psys signal */ + unsigned int psys_imax_ma; + + /* The voltage of barrel jack */ + unsigned int bj_volts_mv; + + /* The barrel jack power */ + unsigned int bj_power_w; +}; + +/* + * Modify Power Limit and PsysPL devictree settings during ramstage. + * Note, this function must be called in front of calling variant_update_power_limits. + */ +void variant_update_psys_power_limits(const struct psys_config *config); + /* Modify LTE devictree settings during ramstage. */ void update_lte_device(struct acpi_gpio *lte_reset_gpio, struct acpi_gpio *lte_enable_gpio); diff --git a/src/mainboard/google/dedede/variants/baseboard/ramstage.c b/src/mainboard/google/dedede/variants/baseboard/ramstage.c new file mode 100644 index 0000000..d43d08f --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/ramstage.c @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <drivers/usb/acpi/chip.h> +#include <fw_config.h> +#include <gpio.h> +#include <soc/pci_devs.h> +#include <ec/google/chromeec/ec.h> +#include <device/pci_ops.h> +#include <intelblocks/power_limit.h> +#include <chip.h> +#include <drivers/intel/dptf/chip.h> +#include <soc/pci_devs.h> + +#define SET_PSYSPL2(e, w) ((e) * (w) / 100) +#define MICROWATTS_TO_WATTS 1000000 + +static bool get_sku_index(size_t *intel_idx) +{ + uint16_t mch_id = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + uint8_t tdp = get_cpu_tdp(); + size_t i = 0; + + if (mch_id != 0xFFFF) { + for (i = 0; i < ARRAY_SIZE(cpuid_to_jsl); i++) { + if (mch_id == cpuid_to_jsl[i].pci_did && + tdp == cpuid_to_jsl[i].cpu_tdp) { + *intel_idx = cpuid_to_jsl[i].limits; + break; + } + } + } + + if (i == ARRAY_SIZE(cpuid_to_jsl) || mch_id == 0xFFFF) { + printk(BIOS_ERR, "Cannot find correct intel sku index.\n"); + return false; + } + + return true; +} + +void variant_update_psys_power_limits(const struct psys_config *config_psys) +{ + struct soc_power_limits_config *soc_config; + size_t intel_idx = 0; + u16 volts_mv, current_ma; + enum usb_chg_type type; + u32 psys_pl2; + config_t *conf; + u32 watts; + int rv; + + if (!get_sku_index(&intel_idx)) + return; + + conf = config_of_soc(); + soc_config = &conf->power_limits_config[intel_idx]; + + rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv); + + if (rv == 0 && type == USB_CHG_TYPE_PD) { + /* Detected USB-PD. Base on max value of adapter */ + watts = ((u32)current_ma * volts_mv) / MICROWATTS_TO_WATTS; + } else { + /* Input type is barrel jack */ + volts_mv = config_psys->bj_volts_mv; + watts = config_psys->bj_power_w; + } + /* Set psyspl2 to 97% of adapter rating */ + psys_pl2 = SET_PSYSPL2(config_psys->efficiency, watts); + + /* voltage unit is milliVolts and current is in milliAmps */ + soc_config->psys_pmax = (u16)(((u32)config_psys->psys_imax_ma * volts_mv) / MICROWATTS_TO_WATTS); + conf->PsysPmax = soc_config->psys_pmax; + + soc_config->tdp_psyspl2 = psys_pl2; + + printk(BIOS_INFO, "Overriding PsysPL2 (%uW) Psys_Pmax (%uW)\n", + soc_config->tdp_psyspl2, + soc_config->psys_pmax); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/75680?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I583c930379233322c41027805369f81d02000ee7 Gerrit-Change-Number: 75680 Gerrit-PatchSet: 12 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chia-Ling Hou <chia-ling.hou(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: [WIP] soc/amd/phoenix/Makefile.inc: Pass APOB_NV address as offset
by Fred Reitberger (Code Review) 29 Jun '23

29 Jun '23

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76162?usp=email ) Change subject: [WIP] soc/amd/phoenix/Makefile.inc: Pass APOB_NV address as offset ...................................................................... [WIP] soc/amd/phoenix/Makefile.inc: Pass APOB_NV address as offset Pass the APOB NV address as a flash offset instead of x86 address. Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Change-Id: I0f710f12cc5d933a75840dbce1c4bad0c2ea04cc --- M src/soc/amd/phoenix/Makefile.inc 1 file changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/76162/1 diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc index 0945830..907842d 100644 --- a/src/soc/amd/phoenix/Makefile.inc +++ b/src/soc/amd/phoenix/Makefile.inc @@ -133,13 +133,17 @@ # type = 0x63 - construct APOB NV base/size from flash map # The flashmap section used for this is expected to be named RW_MRC_CACHE APOB_NV_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_BASE=$(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_BASE=$(shell printf "%#x" $(call int-subtract, \ + $(shell awk '$$2 == "FMAP_SECTION_RW_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) \ + $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h))) ifeq ($(CONFIG_HAS_RECOVERY_MRC_CACHE),y) # On boards with recovery MRC cache, point type 0x63 entry to RECOVERY_MRC_CACHE. # Else use RW_MRC_CACHE. This entry will be added in the RO section. APOB_NV_RO_SIZE=$(shell awk '$$2 == "FMAP_SECTION_RECOVERY_MRC_CACHE_SIZE" {print $$3}' $(obj)/fmap_config.h) -APOB_NV_RO_BASE=$(shell awk '$$2 == "FMAP_SECTION_RECOVERY_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) +APOB_NV_RO_BASE=$(shell printf "%#x" $(call int-subtract, \ + $(shell awk '$$2 == "FMAP_SECTION_RECOVERY_MRC_CACHE_START" {print $$3}' $(obj)/fmap_config.h) \ + $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h))) else APOB_NV_RO_SIZE=$(APOB_NV_SIZE) APOB_NV_RO_BASE=$(APOB_NV_BASE) -- To view, visit https://review.coreboot.org/c/coreboot/+/76162?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f710f12cc5d933a75840dbce1c4bad0c2ea04cc Gerrit-Change-Number: 76162 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/rex/var/ovis: Fix mux change as per schematics
by Jakub Czapiga (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76149?usp=email ) Change subject: mb/google/rex/var/ovis: Fix mux change as per schematics ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76149?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I223eb3a96e6a1b3abb4168fcf59c0df04c1b4498 Gerrit-Change-Number: 76149 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 15:32:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 0
by Jan Samek (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Mario Scheithauer, Paul Menzel, Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75836?usp=email ) Change subject: mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 0 ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75836/comment/76776afa_45e608c3 : PS1, Line 7: Disable all USB 3.0 ports > Maybe: Disable USB 3. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75836?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28465f1c5e6d3167c649da898ec60d8bb97093e2 Gerrit-Change-Number: 75836 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 14:49:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 0
by Jan Samek (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Jan Samek, Mario Scheithauer, Paul Menzel, Werner Zeh. Hello Mario Scheithauer, Paul Menzel, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75836?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins) Change subject: mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 0 ...................................................................... mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 0 It's been decided not to use any of the USB 3.0 ports on this board. This patch disables the remaining USB 3.0 port 0, after the port 1 has already been disabled in commit d0627c7595fe ("mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 1"). BUG=none TEST=None of the USB 3.0 ports functional anymore after boot, the USB 2.0 ports continue working. Change-Id: I28465f1c5e6d3167c649da898ec60d8bb97093e2 Signed-off-by: Jan Samek <jan.samek(a)siemens.com> --- M src/mainboard/siemens/mc_ehl/variants/mc_ehl3/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/75836/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75836?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28465f1c5e6d3167c649da898ec60d8bb97093e2 Gerrit-Change-Number: 75836 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/siemens/mc_ehl3/devicetree.cb: Disable all USB 3.0 ports
by Paul Menzel (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Jan Samek, Mario Scheithauer, Werner Zeh. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75836?usp=email ) Change subject: mb/siemens/mc_ehl3/devicetree.cb: Disable all USB 3.0 ports ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75836/comment/cf6d22ec_a03d8ed8 : PS1, Line 7: Disable all USB 3.0 ports Maybe: Disable USB 3.0 port 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/75836?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28465f1c5e6d3167c649da898ec60d8bb97093e2 Gerrit-Change-Number: 75836 Gerrit-PatchSet: 1 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 14:38:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: acpi: Set checksum for SPCR table
by Lean Sheng Tan (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Felix Singer, Lance Zhao, Nico Huber, Tim Wawrzynczak. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76158?usp=email ) Change subject: acpi: Set checksum for SPCR table ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/76158?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0086a3e8c5b3a06da9edf40a7a288c534fc5a6b2 Gerrit-Change-Number: 76158 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 12:39:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: acpi: Set checksum for SPCR table
by Nico Huber (Code Review) 29 Jun '23

29 Jun '23

Attention is currently required from: Felix Singer, Lance Zhao, Lean Sheng Tan, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76158?usp=email ) Change subject: acpi: Set checksum for SPCR table ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/76158/comment/fb8e3b2d_9357bd7e : PS1, Line 13: Fixes: commit 90464073e4a1 (acpi: Add SPCR table) > Here's the log that mentions the checksum: […] I doubt it'll fix fwts, but I've confirmed that the checksum complaint goes away in QEMU (which was a little hackish because of the odd `/* Special case for qemu */` in write_acpi_tables()). File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/76158/comment/6d1645ca_d0dc4ef0 : PS1, Line 1870: header->checksum = acpi_checksum((void *)spcr, header->length); > It's just one struct with a constant length. Resoved, right? -- To view, visit https://review.coreboot.org/c/coreboot/+/76158?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0086a3e8c5b3a06da9edf40a7a288c534fc5a6b2 Gerrit-Change-Number: 76158 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 29 Jun 2023 12:03:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: comment

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