coreboot-gerrit June 2023

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[M] Change in coreboot[master]: mb/google/geralt: Fix MIPI panel power on/off sequence
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Hung-Te Lin, Paul Menzel, Ruihai Zhou, Yidi Lin, Yu-Ping Wu. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75512?usp=email ) Change subject: mb/google/geralt: Fix MIPI panel power on/off sequence ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/geralt/panel_geralt.c: https://review.coreboot.org/c/coreboot/+/75512/comment/503dff7e_bb0c65ef : PS3, Line 51: printk(BIOS_ERR, "Failed to setup tps65132s\n"); > Error messages should be user understandable. Maybe: […] TPS65132 isn't a display panel, but a voltage regulator -- To view, visit https://review.coreboot.org/c/coreboot/+/75512?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ccb5be04062a0516f84a054ff3f40afbf5279be Gerrit-Change-Number: 75512 Gerrit-PatchSet: 3 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 13:10:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/corsola: Fix MIPI panel power on/off sequence
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75298?usp=email ) ( 9 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/corsola: Fix MIPI panel power on/off sequence ...................................................................... mb/google/corsola: Fix MIPI panel power on/off sequence Based on the power sequence of the panel [1] and PMIC datasheet [2], the power on T2 sequence VSP to VSN should be large than 1ms, but it's -159us now, and the power off T2 sequence VSP to VSN should be large than 0ms, but it's less than 0 now. Let's modify the power sequence to meet the datasheet requirement. [1] HX83102-J02_Datasheet_v03.pdf [2] TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf BUG=b:282902297 TEST=power sequence T2 pass Signed-off-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Change-Id: Ib1625c6a211f849071393f69eaf5c649a8e7f72e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75298 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/corsola/display.c M src/mainboard/google/corsola/display.h M src/mainboard/google/corsola/panel_starmie.c 3 files changed, 19 insertions(+), 74 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/mainboard/google/corsola/display.c b/src/mainboard/google/corsola/display.c index 9a8ecc5..a66d92e 100644 --- a/src/mainboard/google/corsola/display.c +++ b/src/mainboard/google/corsola/display.c @@ -1,17 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <assert.h> #include <boardid.h> #include <cbfs.h> #include <console/console.h> -#include <delay.h> -#include <device/i2c_simple.h> #include <edid.h> #include <gpio.h> #include <soc/ddp.h> #include <soc/dsi.h> #include <soc/gpio_common.h> -#include <soc/i2c.h> #include <soc/mtcmos.h> #include "display.h" @@ -25,67 +21,6 @@ gpio_output(GPIO_EN_PP3300_DISP_X, 1); } -int panel_pmic_reg_mask(unsigned int bus, uint8_t chip, uint8_t addr, - uint8_t val, uint8_t mask) -{ - uint8_t msg = 0; - - if (i2c_read_field(bus, chip, addr, &msg, 0xFF, 0) < 0) { - printk(BIOS_ERR, "%s: Failed to read i2c(%u): addr(%u)\n", - __func__, bus, addr); - return -1; - } - - msg &= ~mask; - msg |= val; - - return i2c_write_field(bus, chip, addr, msg, 0xFF, 0); -} - -void tps65132s_program_eeprom(void) -{ - u8 value = 0; - u8 value1 = 0; - - /* Initialize I2C6 for PMIC TPS65132 */ - mtk_i2c_bus_init(PMIC_TPS65132_I2C, I2C_SPEED_FAST); - mdelay(10); - - /* EN_PP6000_MIPI_DISP */ - gpio_output(GPIO_EN_PP3300_DISP_X, 1); - /* EN_PP6000_MIPI_DISP_150MA */ - gpio_output(GPIO_EN_PP3300_SDBRDG_X, 1); - mdelay(10); - - i2c_read_field(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x00, &value, 0xFF, 0); - i2c_read_field(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x01, &value1, 0xFF, 0); - - if (value != 0x14 || value1 != 0x14) { - printk(BIOS_INFO, "Set AVDD AVEE 6.0V to EEPROM Data in first time\n"); - - /* Set AVDD = 6.0V */ - if (panel_pmic_reg_mask(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x00, 0x14, - 0x1F) < 0) - return; - - /* Set AVEE = -6.0V */ - if (panel_pmic_reg_mask(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0x01, 0x14, - 0x1F) < 0) - return; - - /* Set EEPROM Data */ - if (panel_pmic_reg_mask(PMIC_TPS65132_I2C, PMIC_TPS65132_SLAVE, 0xFF, 0x80, - 0xFC) < 0) - return; - mdelay(50); - } - /* EN_PP6000_MIPI_DISP */ - gpio_output(GPIO_EN_PP3300_DISP_X, 0); - /* EN_PP6000_MIPI_DISP_150MA */ - gpio_output(GPIO_EN_PP3300_SDBRDG_X, 0); - mdelay(5); -} - struct panel_description *get_panel_from_cbfs(struct panel_description *desc) { char cbfs_name[64]; diff --git a/src/mainboard/google/corsola/display.h b/src/mainboard/google/corsola/display.h index afff4bf..11d2f24 100644 --- a/src/mainboard/google/corsola/display.h +++ b/src/mainboard/google/corsola/display.h @@ -9,7 +9,6 @@ #define BRIDGE_I2C I2C0 #define PMIC_TPS65132_I2C I2C6 -#define PMIC_TPS65132_SLAVE 0x3E struct panel_description { void (*power_on)(void); /* Callback to turn on panel */ @@ -34,7 +33,4 @@ /* Load panel serializable data from CBFS */ struct panel_description *get_panel_from_cbfs(struct panel_description *desc); -void tps65132s_program_eeprom(void); -int panel_pmic_reg_mask(u32 bus, u8 chip, u8 addr, u8 val, u8 mask); - #endif diff --git a/src/mainboard/google/corsola/panel_starmie.c b/src/mainboard/google/corsola/panel_starmie.c index ffb7b65..aadabf4 100644 --- a/src/mainboard/google/corsola/panel_starmie.c +++ b/src/mainboard/google/corsola/panel_starmie.c @@ -1,20 +1,34 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <delay.h> #include <gpio.h> #include <soc/regulator.h> +#include <soc/tps65132s.h> #include "display.h" #include "gpio.h" static void mipi_panel_power_on(void) { - tps65132s_program_eeprom(); + const struct tps65132s_reg_setting reg_settings[] = { + { PMIC_TPS65132_VPOS, 0x14, 0x1F }, + { PMIC_TPS65132_VNEG, 0x14, 0x1F }, + { PMIC_TPS65132_DLYX, 0x95, 0xFF }, + { PMIC_TPS65132_ASSDD, 0x5b, 0xFF }, + }; + const struct tps65132s_cfg cfg = { + .i2c_bus = PMIC_TPS65132_I2C, + .en = GPIO_EN_PP3300_DISP_X, + .sync = GPIO_EN_PP3300_SDBRDG_X, + .settings = reg_settings, + .setting_counts = ARRAY_SIZE(reg_settings), + }; + mainboard_set_regulator_voltage(MTK_REGULATOR_VIO18, 1800000); - mdelay(1); - gpio_output(GPIO_EN_PP3300_DISP_X, 1); - gpio_output(GPIO_EN_PP3300_SDBRDG_X, 1); - mdelay(1); + if (tps65132s_setup(&cfg) != CB_SUCCESS) + printk(BIOS_ERR, "Failed to setup tps65132s\n"); + /* DISP_RST_1V8_L */ gpio_output(GPIO_EDPBRDG_RST_L, 1); mdelay(1); -- To view, visit https://review.coreboot.org/c/coreboot/+/75298?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1625c6a211f849071393f69eaf5c649a8e7f72e Gerrit-Change-Number: 75298 Gerrit-PatchSet: 11 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/mediatek/common: Add support for power supply TPS65132S
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75488?usp=email ) Change subject: soc/mediatek/common: Add support for power supply TPS65132S ...................................................................... soc/mediatek/common: Add support for power supply TPS65132S The TPS65132S is designed to supply positive/negative driven application. It communicates through standard I2C compatible interface, and it intergrates a EEPROM whose contents will be loaded into the register at startup. Since TPS65132S is used in staryu and geralt projects, we move the implementation to mediatek/common. The datasheet: TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf BUG=b:282902297 TEST=boot starmie to firmware screen Signed-off-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Change-Id: Iad2c9bdea5824455efcef18b44876111061cfa1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75488 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/soc/mediatek/common/include/soc/tps65132s.h A src/soc/mediatek/common/tps65132s.c M src/soc/mediatek/mt8186/Makefile.inc 3 files changed, 103 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/tps65132s.h b/src/soc/mediatek/common/include/soc/tps65132s.h new file mode 100644 index 0000000..d9e609a --- /dev/null +++ b/src/soc/mediatek/common/include/soc/tps65132s.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_TPS65132S_H__ +#define __SOC_MEDIATEK_TPS65132S_H__ + +#include <commonlib/bsd/cb_err.h> +#include <gpio.h> + +/* TPS65132S I2C slave address */ +#define PMIC_TPS65132_SLAVE 0x3E + +/* TPS65132 register address */ +#define PMIC_TPS65132_VPOS 0x00 +#define PMIC_TPS65132_VNEG 0x01 +#define PMIC_TPS65132_DLYX 0x02 +/* Sequencing at startup and shutdown Field */ +#define PMIC_TPS65132_ASSDD 0x03 +#define PMIC_TPS65132_CONTROL 0xFF + +struct tps65132s_reg_setting { + u8 addr; + u8 val; + u8 mask; +}; + +struct tps65132s_cfg { + uint32_t i2c_bus; + gpio_t en; + gpio_t sync; + const struct tps65132s_reg_setting *settings; + uint32_t setting_counts; +}; + +enum cb_err tps65132s_setup(const struct tps65132s_cfg *cfg); + +#endif /* __SOC_MEDIATEK_TPS65132S_H__ */ diff --git a/src/soc/mediatek/common/tps65132s.c b/src/soc/mediatek/common/tps65132s.c new file mode 100644 index 0000000..4683a43 --- /dev/null +++ b/src/soc/mediatek/common/tps65132s.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include <device/i2c_simple.h> +#include <soc/gpio.h> +#include <soc/i2c.h> +#include <soc/tps65132s.h> + +static int tps65132s_reg_mask(unsigned int bus, uint8_t chip, uint8_t addr, + uint8_t val, uint8_t mask) +{ + uint8_t msg = 0; + + if (i2c_read_field(bus, chip, addr, &msg, 0xFF, 0) < 0) { + printk(BIOS_ERR, "%s: Failed to read i2c(%u): addr(%u)\n", + __func__, bus, addr); + return -1; + } + + msg &= ~mask; + msg |= val; + + return i2c_write_field(bus, chip, addr, msg, 0xFF, 0); +} + +enum cb_err tps65132s_setup(const struct tps65132s_cfg *cfg) +{ + bool write_to_eeprom = false; + u8 val; + int i; + + /* Initialize I2C bus for PMIC TPS65132 */ + mtk_i2c_bus_init(cfg->i2c_bus, I2C_SPEED_FAST); + mdelay(10); + + gpio_output(cfg->en, 1); + gpio_output(cfg->sync, 1); + mdelay(10); + + for (i = 0; i < cfg->setting_counts; i++) { + i2c_read_field(cfg->i2c_bus, PMIC_TPS65132_SLAVE, + cfg->settings[i].addr, &val, 0xFF, 0); + if (val != cfg->settings[i].val) { + if (tps65132s_reg_mask(cfg->i2c_bus, PMIC_TPS65132_SLAVE, + cfg->settings[i].addr, + cfg->settings[i].val, + cfg->settings[i].mask) < 0) { + printk(BIOS_ERR, "Failed to program TPS65132S at %x\n", + cfg->settings[i].addr); + return CB_ERR; + } + write_to_eeprom = true; + } + } + + if (write_to_eeprom) { + if (tps65132s_reg_mask(cfg->i2c_bus, PMIC_TPS65132_SLAVE, + PMIC_TPS65132_CONTROL, 0x80, 0xFC) < 0) + return CB_ERR; + printk(BIOS_INFO, "Program TPS65132S EEPROM at first boot\n"); + mdelay(50); + } + + return CB_SUCCESS; +} diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 04d047a..8fe923f 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -49,6 +49,7 @@ ramstage-y += soc.c ramstage-y += ../common/spm.c spm.c ramstage-y += ../common/sspm.c +ramstage-y += ../common/tps65132s.c ramstage-y += ../common/usb.c usb.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8186/include -- To view, visit https://review.coreboot.org/c/coreboot/+/75488?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad2c9bdea5824455efcef18b44876111061cfa1a Gerrit-Change-Number: 75488 Gerrit-PatchSet: 5 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/nissa/var/uldren: Add DPTF parameters
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75413?usp=email ) Change subject: mb/google/nissa/var/uldren: Add DPTF parameters ...................................................................... mb/google/nissa/var/uldren: Add DPTF parameters The DPTF parameters were verified by the thermal team. BUG=b:282598257 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I1f38ef52d3906960f8b692595fcc3b39bc000243 Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75413 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/brya/variants/uldren/overridetree.cb 1 file changed, 49 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/uldren/overridetree.cb b/src/mainboard/google/brya/variants/uldren/overridetree.cb index 6f54e69..77b86552 100644 --- a/src/mainboard/google/brya/variants/uldren/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldren/overridetree.cb @@ -159,6 +159,55 @@ }" device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""CPU_VR"" + register "options.tsr[1].desc" = ""Charger"" + register "options.tsr[2].desc" = ""Ambient"" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 85, 5000), + [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 85, 5000), + }" + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 98, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 98, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 98, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 6000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 250 + }, + .pl2 = { + .min_power = 25000, + .max_power = 25000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 28 * MSECS_PER_SEC, + .granularity = 1000 + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + device generic 0 on end + end + end device ref cnvi_wifi on chip drivers/wifi/generic register "wake" = "GPE0_PME_B0" -- To view, visit https://review.coreboot.org/c/coreboot/+/75413?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f38ef52d3906960f8b692595fcc3b39bc000243 Gerrit-Change-Number: 75413 Gerrit-PatchSet: 4 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ben Kao <ben.kao(a)intel.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: device/allocator: Allow for multiple domain resources of a type
by 9elements QA (Code Review) 01 Jun '23

01 Jun '23

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67018?usp=email ) Change subject: device/allocator: Allow for multiple domain resources of a type ...................................................................... Patch Set 10: Automatic boot test returned (PASS/FAIL/TOTAL): 15 / 1 / 16 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/166511 FAIL: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/166509 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/166508 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/166507 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/166506 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/166505 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/166504 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/166503 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload TianoCore : https://lava.9esec.io/r/166502 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35_SMM_TSEG and payload SeaBIOS : https://lava.9esec.io/r/166501 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload TianoCore : https://lava.9esec.io/r/166500 PASS: x86_32 "QEMU x86 q35/ich9" , build config EMULATION_QEMU_X86_Q35 and payload SeaBIOS : https://lava.9esec.io/r/166499 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/166498 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/166497 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/166496 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/166495 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/67018?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d3a60c9a4438accdb06444e2b50cc9b0b2eb009 Gerrit-Change-Number: 67018 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Thu, 01 Jun 2023 13:06:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[4.20_branch]: src/vc/intel/fsp/fsp2_0/sapphirerapids_sp: Update Spr header files
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75469?usp=email ) Change subject: src/vc/intel/fsp/fsp2_0/sapphirerapids_sp: Update Spr header files ...................................................................... src/vc/intel/fsp/fsp2_0/sapphirerapids_sp: Update Spr header files This change updates Intel Copyright License for all header files under Sapphirerapids dir Cherry-picked from commit 7e2106627df7. Original-Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/75393 Original-Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Original-Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> Original-Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Original-Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Original-Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Change-Id: Ib04988194e5fe9515bea8620318eadff36f92181 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75469 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/CxlNodeHob.h M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/EnhancedWarningLogLib.h M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspErrorInfoHob.h M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioPcieConfigUpd.h M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioUniversalDataHob.h M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/PrevBootErrSrcHob.h M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/SystemInfoHob.h M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_cxlnode.h M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_enhancedwarningloglib.h M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_memmap.h M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_systeminfo.h 12 files changed, 279 insertions(+), 255 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved Nico Huber: Looks good to me, but someone else must approve diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/CxlNodeHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/CxlNodeHob.h index d8b1903..42b5cc2 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/CxlNodeHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/CxlNodeHob.h @@ -1,29 +1,31 @@ /** @file - CXL GUID HOB definitions - @copyright - INTEL CONFIDENTIAL - Copyright 2019 - 2021 Intel Corporation. +Copyright (c) 2019-2023, Intel Corporation. All rights reserved. - The source code contained or described herein and all documents related to the - source code ("Material") are owned by Intel Corporation or its suppliers or - licensors. Title to the Material remains with Intel Corporation or its suppliers - and licensors. The Material may contain trade secrets and proprietary and - confidential information of Intel Corporation and its suppliers and licensors, - and is protected by worldwide copyright and trade secret laws and treaty - provisions. No part of the Material may be used, copied, reproduced, modified, - published, uploaded, posted, transmitted, distributed, or disclosed in any way - without Intel's prior express written permission. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - No license under any patent, copyright, trade secret or other intellectual - property right is granted to or conferred upon you by disclosure or delivery - of the Materials, either expressly, by implication, inducement, estoppel or - otherwise. Any license under such intellectual property rights must be - express and approved by Intel in writing. +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. - Unless otherwise agreed by Intel in writing, you may not remove or alter - this notice or any other notice embedded in Materials by Intel or - Intel's suppliers or licensors in any way. + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + **/ #ifndef _CXL_NODE_HOB_ @@ -89,4 +91,4 @@ #pragma pack() -#endif //#ifndef _CXL_NODE_HOB_ \ No newline at end of file +#endif //#ifndef _CXL_NODE_HOB_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/EnhancedWarningLogLib.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/EnhancedWarningLogLib.h index 0bbed0b..7c54749 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/EnhancedWarningLogLib.h +++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/EnhancedWarningLogLib.h @@ -1,29 +1,31 @@ /** @file - Interface header file for the Enhanced warning log library class. - @copyright - INTEL CONFIDENTIAL - Copyright 2018 - 2021 Intel Corporation. +Copyright (c) 2019-2023, Intel Corporation. All rights reserved. - The source code contained or described herein and all documents related to the - source code ("Material") are owned by Intel Corporation or its suppliers or - licensors. Title to the Material remains with Intel Corporation or its suppliers - and licensors. The Material may contain trade secrets and proprietary and - confidential information of Intel Corporation and its suppliers and licensors, - and is protected by worldwide copyright and trade secret laws and treaty - provisions. No part of the Material may be used, copied, reproduced, modified, - published, uploaded, posted, transmitted, distributed, or disclosed in any way - without Intel's prior express written permission. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - No license under any patent, copyright, trade secret or other intellectual - property right is granted to or conferred upon you by disclosure or delivery - of the Materials, either expressly, by implication, inducement, estoppel or - otherwise. Any license under such intellectual property rights must be - express and approved by Intel in writing. +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. - Unless otherwise agreed by Intel in writing, you may not remove or alter - this notice or any other notice embedded in Materials by Intel or - Intel's suppliers or licensors in any way. + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + **/ #ifndef _ENHANCED_WARNING_LOG_LIB_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspErrorInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspErrorInfoHob.h index 603db144..ecc2d6f 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspErrorInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/FspErrorInfoHob.h @@ -1,30 +1,31 @@ /** @file - FSP Error Information HOB to describe errors inside FSP that bootloader may - take some actions to handle those error scenarios. - @copyright - INTEL CONFIDENTIAL - Copyright 2022 Intel Corporation. +Copyright (c) 2019-2023, Intel Corporation. All rights reserved. - The source code contained or described herein and all documents related to the - source code ("Material") are owned by Intel Corporation or its suppliers or - licensors. Title to the Material remains with Intel Corporation or its suppliers - and licensors. The Material may contain trade secrets and proprietary and - confidential information of Intel Corporation and its suppliers and licensors, - and is protected by worldwide copyright and trade secret laws and treaty - provisions. No part of the Material may be used, copied, reproduced, modified, - published, uploaded, posted, transmitted, distributed, or disclosed in any way - without Intel's prior express written permission. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - No license under any patent, copyright, trade secret or other intellectual - property right is granted to or conferred upon you by disclosure or delivery - of the Materials, either expressly, by implication, inducement, estoppel or - otherwise. Any license under such intellectual property rights must be - express and approved by Intel in writing. +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. - Unless otherwise agreed by Intel in writing, you may not remove or alter - this notice or any other notice embedded in Materials by Intel or - Intel's suppliers or licensors in any way. + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + **/ #ifndef _FSP_ERROR_INFO_HOB_H_ @@ -80,4 +81,4 @@ #pragma pack() -#endif //#ifndef _FSP_ERROR_INFO_HOB_H_ \ No newline at end of file +#endif //#ifndef _FSP_ERROR_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioPcieConfigUpd.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioPcieConfigUpd.h index 175dd75..567d934 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioPcieConfigUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioPcieConfigUpd.h @@ -1,29 +1,31 @@ /** @file - Header file to define the structures used for FSPM dynamic configuration. - @copyright - INTEL CONFIDENTIAL - Copyright 2021 Intel Corporation. +Copyright (c) 2019-2023, Intel Corporation. All rights reserved. - The source code contained or described herein and all documents related to the - source code ("Material") are owned by Intel Corporation or its suppliers or - licensors. Title to the Material remains with Intel Corporation or its suppliers - and licensors. The Material may contain trade secrets and proprietary and - confidential information of Intel Corporation and its suppliers and licensors, - and is protected by worldwide copyright and trade secret laws and treaty - provisions. No part of the Material may be used, copied, reproduced, modified, - published, uploaded, posted, transmitted, distributed, or disclosed in any way - without Intel's prior express written permission. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - No license under any patent, copyright, trade secret or other intellectual - property right is granted to or conferred upon you by disclosure or delivery - of the Materials, either expressly, by implication, inducement, estoppel or - otherwise. Any license under such intellectual property rights must be - express and approved by Intel in writing. +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. - Unless otherwise agreed by Intel in writing, you may not remove or alter - this notice or any other notice embedded in Materials by Intel or - Intel's suppliers or licensors in any way. + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + **/ #ifndef _IIO_PCIE_CONFIG_UPD_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioUniversalDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioUniversalDataHob.h index 4857d4b..8d4c019 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioUniversalDataHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/IioUniversalDataHob.h @@ -1,29 +1,31 @@ /** @file - Data format for IIO Universal Data HOB Structure - @copyright - INTEL CONFIDENTIAL - Copyright 1999 - 2021 Intel Corporation. +Copyright (c) 2019-2023, Intel Corporation. All rights reserved. - The source code contained or described herein and all documents related to the - source code ("Material") are owned by Intel Corporation or its suppliers or - licensors. Title to the Material remains with Intel Corporation or its suppliers - and licensors. The Material may contain trade secrets and proprietary and - confidential information of Intel Corporation and its suppliers and licensors, - and is protected by worldwide copyright and trade secret laws and treaty - provisions. No part of the Material may be used, copied, reproduced, modified, - published, uploaded, posted, transmitted, distributed, or disclosed in any way - without Intel's prior express written permission. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - No license under any patent, copyright, trade secret or other intellectual - property right is granted to or conferred upon you by disclosure or delivery - of the Materials, either expressly, by implication, inducement, estoppel or - otherwise. Any license under such intellectual property rights must be - express and approved by Intel in writing. +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. - Unless otherwise agreed by Intel in writing, you may not remove or alter - this notice or any other notice embedded in Materials by Intel or - Intel's suppliers or licensors in any way. + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + **/ #ifndef _IIO_UNIVERSAL_DATA_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h index 2534f9a..0d1cdb9 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h @@ -1,29 +1,31 @@ /** @file - GUID used for Memory Map Data entries in the HOB list. - @copyright - INTEL CONFIDENTIAL - Copyright 1999 - 2022 Intel Corporation. +Copyright (c) 2019-2023, Intel Corporation. All rights reserved. - The source code contained or described herein and all documents related to the - source code ("Material") are owned by Intel Corporation or its suppliers or - licensors. Title to the Material remains with Intel Corporation or its suppliers - and licensors. The Material may contain trade secrets and proprietary and - confidential information of Intel Corporation and its suppliers and licensors, - and is protected by worldwide copyright and trade secret laws and treaty - provisions. No part of the Material may be used, copied, reproduced, modified, - published, uploaded, posted, transmitted, distributed, or disclosed in any way - without Intel's prior express written permission. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - No license under any patent, copyright, trade secret or other intellectual - property right is granted to or conferred upon you by disclosure or delivery - of the Materials, either expressly, by implication, inducement, estoppel or - otherwise. Any license under such intellectual property rights must be - express and approved by Intel in writing. +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. - Unless otherwise agreed by Intel in writing, you may not remove or alter - this notice or any other notice embedded in Materials by Intel or - Intel's suppliers or licensors in any way. + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + **/ #ifndef _MEMORY_MAP_DATA_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/PrevBootErrSrcHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/PrevBootErrSrcHob.h index 8df3e85..f1d5554 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/PrevBootErrSrcHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/PrevBootErrSrcHob.h @@ -1,28 +1,31 @@ /** @file - @copyright - INTEL CONFIDENTIAL - Copyright 2007 -2021 Intel Corporation. +Copyright (c) 2019-2023, Intel Corporation. All rights reserved. - The source code contained or described herein and all documents related to the - source code ("Material") are owned by Intel Corporation or its suppliers or - licensors. Title to the Material remains with Intel Corporation or its suppliers - and licensors. The Material may contain trade secrets and proprietary and - confidential information of Intel Corporation and its suppliers and licensors, - and is protected by worldwide copyright and trade secret laws and treaty - provisions. No part of the Material may be used, copied, reproduced, modified, - published, uploaded, posted, transmitted, distributed, or disclosed in any way - without Intel's prior express written permission. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - No license under any patent, copyright, trade secret or other intellectual - property right is granted to or conferred upon you by disclosure or delivery - of the Materials, either expressly, by implication, inducement, estoppel or - otherwise. Any license under such intellectual property rights must be - express and approved by Intel in writing. +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. - Unless otherwise agreed by Intel in writing, you may not remove or alter - this notice or any other notice embedded in Materials by Intel or - Intel's suppliers or licensors in any way. + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + **/ #ifndef _PREV_BOOT_ERR_SRC_HOB_H_ @@ -79,4 +82,4 @@ #pragma pack() -#endif //_PREV_BOOT_ERR_SRC_HOB_H_ \ No newline at end of file +#endif //_PREV_BOOT_ERR_SRC_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/SystemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/SystemInfoHob.h index e87c6e9..b6d88f5 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/SystemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/SystemInfoHob.h @@ -1,29 +1,31 @@ /** @file - System Information HOB Hearder File - @copyright - INTEL CONFIDENTIAL - Copyright 2017 - 2021 Intel Corporation. +Copyright (c) 2019-2023, Intel Corporation. All rights reserved. - The source code contained or described herein and all documents related to the - source code ("Material") are owned by Intel Corporation or its suppliers or - licensors. Title to the Material remains with Intel Corporation or its suppliers - and licensors. The Material may contain trade secrets and proprietary and - confidential information of Intel Corporation and its suppliers and licensors, - and is protected by worldwide copyright and trade secret laws and treaty - provisions. No part of the Material may be used, copied, reproduced, modified, - published, uploaded, posted, transmitted, distributed, or disclosed in any way - without Intel's prior express written permission. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - No license under any patent, copyright, trade secret or other intellectual - property right is granted to or conferred upon you by disclosure or delivery - of the Materials, either expressly, by implication, inducement, estoppel or - otherwise. Any license under such intellectual property rights must be - express and approved by Intel in writing. +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. - Unless otherwise agreed by Intel in writing, you may not remove or alter - this notice or any other notice embedded in Materials by Intel or - Intel's suppliers or licensors in any way. + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + **/ #ifndef _SYSTEM_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_cxlnode.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_cxlnode.h index 2221a38..6086737 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_cxlnode.h +++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_cxlnode.h @@ -1,29 +1,31 @@ /** @file - CXL GUID HOB definitions - @copyright - INTEL CONFIDENTIAL - Copyright 1999 - 2021 Intel Corporation. +Copyright (c) 2019-2023, Intel Corporation. All rights reserved. - The source code contained or described herein and all documents related to the - source code ("Material") are owned by Intel Corporation or its suppliers or - licensors. Title to the Material remains with Intel Corporation or its suppliers - and licensors. The Material may contain trade secrets and proprietary and - confidential information of Intel Corporation and its suppliers and licensors, - and is protected by worldwide copyright and trade secret laws and treaty - provisions. No part of the Material may be used, copied, reproduced, modified, - published, uploaded, posted, transmitted, distributed, or disclosed in any way - without Intel's prior express written permission. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - No license under any patent, copyright, trade secret or other intellectual - property right is granted to or conferred upon you by disclosure or delivery - of the Materials, either expressly, by implication, inducement, estoppel or - otherwise. Any license under such intellectual property rights must be - express and approved by Intel in writing. +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. - Unless otherwise agreed by Intel in writing, you may not remove or alter - this notice or any other notice embedded in Materials by Intel or - Intel's suppliers or licensors in any way. + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + **/ #ifndef _HOB_CXLNODE_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_enhancedwarningloglib.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_enhancedwarningloglib.h index 1a86caa..9b4766b 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_enhancedwarningloglib.h +++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_enhancedwarningloglib.h @@ -1,29 +1,31 @@ /** @file - Interface header file for the Enhanced warning log library class. - @copyright - INTEL CONFIDENTIAL - Copyright 2018 - 2021 Intel Corporation. +Copyright (c) 2019-2023, Intel Corporation. All rights reserved. - The source code contained or described herein and all documents related to the - source code ("Material") are owned by Intel Corporation or its suppliers or - licensors. Title to the Material remains with Intel Corporation or its suppliers - and licensors. The Material may contain trade secrets and proprietary and - confidential information of Intel Corporation and its suppliers and licensors, - and is protected by worldwide copyright and trade secret laws and treaty - provisions. No part of the Material may be used, copied, reproduced, modified, - published, uploaded, posted, transmitted, distributed, or disclosed in any way - without Intel's prior express written permission. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - No license under any patent, copyright, trade secret or other intellectual - property right is granted to or conferred upon you by disclosure or delivery - of the Materials, either expressly, by implication, inducement, estoppel or - otherwise. Any license under such intellectual property rights must be - express and approved by Intel in writing. +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. - Unless otherwise agreed by Intel in writing, you may not remove or alter - this notice or any other notice embedded in Materials by Intel or - Intel's suppliers or licensors in any way. + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + **/ #ifndef _HOB_ENHANCEDWARNINGLOG_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_memmap.h index 8eb8960..0cf1f86 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_memmap.h @@ -1,29 +1,31 @@ /** @file - GUID used for Memory Map Data entries in the HOB list. - @copyright - INTEL CONFIDENTIAL - Copyright 1999 - 2021 Intel Corporation. +Copyright (c) 2019-2023, Intel Corporation. All rights reserved. - The source code contained or described herein and all documents related to the - source code ("Material") are owned by Intel Corporation or its suppliers or - licensors. Title to the Material remains with Intel Corporation or its suppliers - and licensors. The Material may contain trade secrets and proprietary and - confidential information of Intel Corporation and its suppliers and licensors, - and is protected by worldwide copyright and trade secret laws and treaty - provisions. No part of the Material may be used, copied, reproduced, modified, - published, uploaded, posted, transmitted, distributed, or disclosed in any way - without Intel's prior express written permission. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - No license under any patent, copyright, trade secret or other intellectual - property right is granted to or conferred upon you by disclosure or delivery - of the Materials, either expressly, by implication, inducement, estoppel or - otherwise. Any license under such intellectual property rights must be - express and approved by Intel in writing. +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. - Unless otherwise agreed by Intel in writing, you may not remove or alter - this notice or any other notice embedded in Materials by Intel or - Intel's suppliers or licensors in any way. + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + **/ #ifndef _HOB_MEMMAP_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_systeminfo.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_systeminfo.h index 0901651..3466050 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_systeminfo.h +++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_systeminfo.h @@ -1,29 +1,31 @@ /** @file - System Information HOB Hearder File - @copyright - INTEL CONFIDENTIAL - Copyright 2017 - 2021 Intel Corporation. +Copyright (c) 2019-2023, Intel Corporation. All rights reserved. - The source code contained or described herein and all documents related to the - source code ("Material") are owned by Intel Corporation or its suppliers or - licensors. Title to the Material remains with Intel Corporation or its suppliers - and licensors. The Material may contain trade secrets and proprietary and - confidential information of Intel Corporation and its suppliers and licensors, - and is protected by worldwide copyright and trade secret laws and treaty - provisions. No part of the Material may be used, copied, reproduced, modified, - published, uploaded, posted, transmitted, distributed, or disclosed in any way - without Intel's prior express written permission. +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: - No license under any patent, copyright, trade secret or other intellectual - property right is granted to or conferred upon you by disclosure or delivery - of the Materials, either expressly, by implication, inducement, estoppel or - otherwise. Any license under such intellectual property rights must be - express and approved by Intel in writing. +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. - Unless otherwise agreed by Intel in writing, you may not remove or alter - this notice or any other notice embedded in Materials by Intel or - Intel's suppliers or licensors in any way. + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + **/ #ifndef _HOB_SYSTEMINFO_H_ -- To view, visit https://review.coreboot.org/c/coreboot/+/75469?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.20_branch Gerrit-Change-Id: Ib04988194e5fe9515bea8620318eadff36f92181 Gerrit-Change-Number: 75469 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[master]: mb/google/rex/variants/ovis: Add basic DTT
by Jakub Czapiga (Code Review) 01 Jun '23

01 Jun '23

1 0

[S] Change in coreboot[master]: mb/google/rex/variants/ovis: Add display configurarion
by Jakub Czapiga (Code Review) 01 Jun '23

01 Jun '23

1 0

[M] Change in coreboot[master]: mb/google/rex/variants/ovis: Add USB configuration
by Jakub Czapiga (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli. Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75578?usp=email ) Change subject: mb/google/rex/variants/ovis: Add USB configuration ...................................................................... mb/google/rex/variants/ovis: Add USB configuration BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> --- M src/mainboard/google/rex/variants/ovis/overridetree.cb 1 file changed, 151 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/75578/1 diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb index 1ec938e..7a42029 100644 --- a/src/mainboard/google/rex/variants/ovis/overridetree.cb +++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb @@ -1,4 +1,18 @@ chip soc/intel/meteorlake + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C1 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C2 + register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # Type-A Port A0 + register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-A Port A1 + register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" # Type-A Port A2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A3 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type-A Port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type-A Port A1 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)" + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)" register "serial_io_gspi_mode" = "{ [PchSerialIoIndexGSPI0] = PchSerialIoPci, @@ -42,6 +56,119 @@ .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end # PCIE11 SSD card + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tbt_pcie_rp2 on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" + use tcss_usb3_port2 as dfp[0].typec_port + device generic 0 on end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 2))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(5, 2))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(6, 2))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(7, 2))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 3))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(5, 3))" + device ref usb3_port2 on end + end + end + end + end device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" @@ -51,8 +178,32 @@ end device ref soc_espi on chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + use conn2 as mux_conn[2] device pnp 0c09.0 on end end end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 2 alias conn2 on end + end + end + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/75578?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443 Gerrit-Change-Number: 75578 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: mb/google/rex/variants/ovis: Add SPI configuration
by Jakub Czapiga (Code Review) 01 Jun '23

01 Jun '23

1 0

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