coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: mb/google/rex/variants/ovis: Add SSD card config
by Jakub Czapiga (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli. Jakub Czapiga has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75576?usp=email ) Change subject: mb/google/rex/variants/ovis: Add SSD card config ...................................................................... mb/google/rex/variants/ovis: Add SSD card config BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Change-Id: I3795313e784595ac02ee2a38f466bcb9e613a6a4 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> --- M src/mainboard/google/rex/variants/ovis/overridetree.cb 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/75576/1 diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb index 2d43a0e..bc10cd1 100644 --- a/src/mainboard/google/rex/variants/ovis/overridetree.cb +++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb @@ -28,6 +28,14 @@ }" device domain 0 on + device ref pcie_rp11 on + # Enable SSD Card PCIE 11 using clk 7 + register "pcie_rp[PCH_RP(11)]" = "{ + .clk_src = 7, + .clk_req = 7, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end # PCIE11 SSD card device ref i2c4 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" -- To view, visit https://review.coreboot.org/c/coreboot/+/75576?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3795313e784595ac02ee2a38f466bcb9e613a6a4 Gerrit-Change-Number: 75576 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/rex/variants/ovis: Add I2C config
by Jakub Czapiga (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Jan Dabros, Kapil Porwal, Subrata Banik, Tarun Tuli. Hello Kapil Porwal, Subrata Banik, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75503?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rex/variants/ovis: Add I2C config ...................................................................... mb/google/rex/variants/ovis: Add I2C config BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I1644b1d8f49accbb2ea68e236534df80a5151360 --- M src/mainboard/google/rex/variants/ovis/overridetree.cb 1 file changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/75503/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/75503?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1644b1d8f49accbb2ea68e236534df80a5151360 Gerrit-Change-Number: 75503 Gerrit-PatchSet: 5 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Dabros <dabros(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jan Dabros <dabros(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/google/rex: Create ovis variant
by Jakub Czapiga (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Kapil Porwal, Paul Menzel, Subrata Banik, Tarun Tuli. Hello Kapil Porwal, Subrata Banik, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75385?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rex: Create ovis variant ...................................................................... mb/google/rex: Create ovis variant BUG=b:274421383 TEST=util/abuild/abuild -p none -t google/rex -x -a ; Make sure GOOGLE_OVIS built successfully Change-Id: I5c8f290cfdcb4d47c0e5e9d72c1e34073b957681 Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/Kconfig.name A src/mainboard/google/rex/variants/baseboard/ovis/Makefile.inc A src/mainboard/google/rex/variants/baseboard/ovis/devicetree.cb A src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/ec.h A src/mainboard/google/rex/variants/baseboard/ovis/include/baseboard/gpio.h A src/mainboard/google/rex/variants/baseboard/ovis/memory.c A src/mainboard/google/rex/variants/ovis/Makefile.inc A src/mainboard/google/rex/variants/ovis/gpio.c A src/mainboard/google/rex/variants/ovis/include/variant/ec.h A src/mainboard/google/rex/variants/ovis/include/variant/gpio.h A src/mainboard/google/rex/variants/ovis/memory/Makefile.inc A src/mainboard/google/rex/variants/ovis/memory/dram_id.generated.txt A src/mainboard/google/rex/variants/ovis/memory/mem_parts_used.txt A src/mainboard/google/rex/variants/ovis/overridetree.cb 15 files changed, 349 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/75385/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/75385?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c8f290cfdcb4d47c0e5e9d72c1e34073b957681 Gerrit-Change-Number: 75385 Gerrit-PatchSet: 7 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jan Dabros <dabros(a)google.com> Gerrit-CC: Jan Dabros <jsd(a)semihalf.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/google/jacuzzi/: Add new variant Bellis
by Paul Menzel (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Hung-Te Lin, Wizard Shen, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62337?usp=email ) Change subject: mb/google/jacuzzi/: Add new variant Bellis ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: What is the state of this change-set? Was *bellis* ever created? -- To view, visit https://review.coreboot.org/c/coreboot/+/62337?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a167e4a7d287cfbf742c98e5356cf0bc5e0d3da Gerrit-Change-Number: 62337 Gerrit-PatchSet: 5 Gerrit-Owner: Wizard Shen <shenhu5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Zhi7 Li <lizhi7(a)huaqin.corp-partner.google.com> Gerrit-CC: yongkun yu <yuyongkun(a)huaqin.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Wizard Shen <shenhu5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 12:31:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/kukui: change Juniper/Willow Ram table offset to 0x30
by Paul Menzel (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Hung-Te Lin, Sheng-Liang Pan, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75563?usp=email ) Change subject: mb/google/kukui: change Juniper/Willow Ram table offset to 0x30 ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75563/comment/1a7e0237_a39f5bc0 : PS2, Line 7: Ram RAM https://review.coreboot.org/c/coreboot/+/75563/comment/0ec7005b_57841181 : PS2, Line 9: all memory ID What do you mean by “all memory ID”? https://review.coreboot.org/c/coreboot/+/75563/comment/7b196f47_e809ad37 : PS2, Line 9: for For https://review.coreboot.org/c/coreboot/+/75563/comment/2593835e_8336680e : PS2, Line 11: What is the source? -- To view, visit https://review.coreboot.org/c/coreboot/+/75563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I92740275dcc27061a94b7db7ce095655c0bd7cf5 Gerrit-Change-Number: 75563 Gerrit-PatchSet: 2 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 12:29:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/acpi: move acpi_fill_root_complex_tom to Stoneyridge
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75564?usp=email ) Change subject: soc/amd/common/acpi: move acpi_fill_root_complex_tom to Stoneyridge ...................................................................... soc/amd/common/acpi: move acpi_fill_root_complex_tom to Stoneyridge Now that Stoneyridge is the only AMD SoC that still needs the part of the SSDT that contains the TOM1 and TOM2, move it from the common code to the Stoneyridge northbridge code. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9091360d6a82183092ef75417ad652523babe075 --- M src/soc/amd/common/block/acpi/tables.c M src/soc/amd/common/block/include/amdblocks/acpi.h M src/soc/amd/stoneyridge/northbridge.c 3 files changed, 25 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/75564/1 diff --git a/src/soc/amd/common/block/acpi/tables.c b/src/soc/amd/common/block/acpi/tables.c index aaa851e..bda283a 100644 --- a/src/soc/amd/common/block/acpi/tables.c +++ b/src/soc/amd/common/block/acpi/tables.c @@ -3,9 +3,6 @@ #include <acpi/acpi.h> #include <acpi/acpigen.h> #include <amdblocks/acpi.h> -#include <amdblocks/chip.h> -#include <assert.h> -#include <cpu/amd/mtrr.h> #include <device/device.h> #include <types.h> @@ -15,28 +12,3 @@ { return acpi_write_hpet(device, current, rsdp); } - -/* Used by \_SB.PCI0._CRS */ -void acpi_fill_root_complex_tom(const struct device *device) -{ - const char *scope; - - assert(device); - - scope = acpi_device_scope(device); - assert(scope); - acpigen_write_scope(scope); - - acpigen_write_name_dword("TOM1", get_top_of_mem_below_4gb()); - - /* - * Since XP only implements parts of ACPI 2.0, we can't use a qword - * here. - * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt - * slide 22ff. - * Shift value right by 20 bit to make it fit into 32bit, - * giving us 1MB granularity and a limit of almost 4Exabyte of memory. - */ - acpigen_write_name_dword("TOM2", get_top_of_mem_above_4gb() >> 20); - acpigen_pop_len(); -} diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 9105184..682f8ca 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -54,8 +54,6 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); -void acpi_fill_root_complex_tom(const struct device *device); - uintptr_t add_agesa_fsp_acpi_table(guid_t guid, const char *name, acpi_rsdp_t *rsdp, uintptr_t current); diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 75fdfa4..db670e3 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -167,6 +167,31 @@ register_new_ioapic((u8 *)IO_APIC2_ADDR); } +/* Used by \_SB.PCI0._CRS */ +static void acpi_fill_root_complex_tom(const struct device *device) +{ + const char *scope; + + assert(device); + + scope = acpi_device_scope(device); + assert(scope); + acpigen_write_scope(scope); + + acpigen_write_name_dword("TOM1", get_top_of_mem_below_4gb()); + + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + acpigen_write_name_dword("TOM2", get_top_of_mem_above_4gb() >> 20); + acpigen_pop_len(); +} + static unsigned long acpi_fill_hest(acpi_hest_t *hest) { void *addr, *current; -- To view, visit https://review.coreboot.org/c/coreboot/+/75564?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9091360d6a82183092ef75417ad652523babe075 Gerrit-Change-Number: 75564 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[L] Change in coreboot[master]: libpayload/uhci: Re-write UHCI RH driver w/ generic_hub API
by Paul Menzel (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Julius Werner, Nico Huber. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75504?usp=email ) Change subject: libpayload/uhci: Re-write UHCI RH driver w/ generic_hub API ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75504/comment/497bff25_5f1e90c2 : PS1, Line 21: Do you have a QEMU line to test this? -- To view, visit https://review.coreboot.org/c/coreboot/+/75504?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5211728775eb94dfc23fa82ebf00fe5c99039709 Gerrit-Change-Number: 75504 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 01 Jun 2023 12:22:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: libpayload/uhci: Return expected length for control/bulk transfers
by Paul Menzel (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Julius Werner, Nico Huber. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75349?usp=email ) Change subject: libpayload/uhci: Return expected length for control/bulk transfers ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75349?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31d7de495a46af401e2cbe5a3b8f6349facad8ff Gerrit-Change-Number: 75349 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 01 Jun 2023 12:21:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: include/cpu/x86: Simplify en/dis cache functions
by Arthur Heymans (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Felix Singer, Himanshu Sahdev, Jérémy Compostella, Lean Sheng Tan, Subrata Banik. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75552?usp=email ) Change subject: include/cpu/x86: Simplify en/dis cache functions ...................................................................... Patch Set 2: (1 comment) File src/include/cpu/x86/cache.h: https://review.coreboot.org/c/coreboot/+/75552/comment/29de0641_2c7c880e : PS2, Line 48: CR0_CacheDisable > > want me to change it to screaming snake case -> CR0_CACHE_DISABLE? > yup, this is what make sense. > > > > > Also, these macros being in use already, better to do it in different CL to change everywhere. > > sure CR0_CD and CR0_NW is fine too IMO -- To view, visit https://review.coreboot.org/c/coreboot/+/75552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81688e8bbb073e1d09ecf63f3f33e1651dbd778e Gerrit-Change-Number: 75552 Gerrit-PatchSet: 2 Gerrit-Owner: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 12:13:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: device/resource_allocator_v4.c: Fix printing unsigned integers
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75400?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: device/resource_allocator_v4.c: Fix printing unsigned integers ...................................................................... device/resource_allocator_v4.c: Fix printing unsigned integers Use the proper format specifier for unsigned integers. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I5e39377d62981229531027b3153d5b343a0a7538 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75400 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/device/resource_allocator_v4.c 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c index 2f4ea12..0a83d29 100644 --- a/src/device/resource_allocator_v4.c +++ b/src/device/resource_allocator_v4.c @@ -61,7 +61,7 @@ */ base = 0; - res_printk(print_depth, "%s %s: size: %llx align: %d gran: %d limit: %llx\n", + res_printk(print_depth, "%s %s: size: %llx align: %u gran: %u limit: %llx\n", dev_path(bridge), resource2str(bridge_res), bridge_res->size, bridge_res->align, bridge_res->gran, bridge_res->limit); @@ -136,7 +136,7 @@ */ bridge_res->size = ALIGN_UP(base, POWER_OF_2(bridge_res->gran)); - res_printk(print_depth, "%s %s: size: %llx align: %d gran: %d limit: %llx done\n", + res_printk(print_depth, "%s %s: size: %llx align: %u gran: %u limit: %llx done\n", dev_path(bridge), resource2str(bridge_res), bridge_res->size, bridge_res->align, bridge_res->gran, bridge_res->limit); } @@ -319,7 +319,7 @@ if ((res->flags & IORESOURCE_TYPE_MASK) != memrange_type) continue; - printk(BIOS_DEBUG, "%s %s: base: %llx size: %llx align: %d gran: %d limit: %llx\n", + printk(BIOS_DEBUG, "%s %s: base: %llx size: %llx align: %u gran: %u limit: %llx\n", dev_path(dev), resource2str(res), res->base, res->size, res->align, res->gran, res->limit); @@ -518,7 +518,7 @@ static void print_resource_done(const struct device *dev, const struct resource *res) { - printk(BIOS_DEBUG, "%s %s: base: %llx size: %llx align: %d gran: %d limit: %llx done\n", + printk(BIOS_DEBUG, "%s %s: base: %llx size: %llx align: %u gran: %u limit: %llx done\n", dev_path(dev), resource2str(res), res->base, res->size, res->align, res->gran, res->limit); } -- To view, visit https://review.coreboot.org/c/coreboot/+/75400?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e39377d62981229531027b3153d5b343a0a7538 Gerrit-Change-Number: 75400 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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