coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: mb/google/myst: Add USB config to myst
by Fred Reitberger (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Jon Murphy. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75574?usp=email ) Change subject: mb/google/myst: Add USB config to myst ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I329aba80f3003a3a5f343b8dcc3efa8502b98e24 Gerrit-Change-Number: 75574 Gerrit-PatchSet: 2 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 15:38:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/block/ivrs: Add NULL check for IVRS
by Naresh Solanki (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Naresh Solanki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75506?usp=email ) Change subject: soc/amd/block/ivrs: Add NULL check for IVRS ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/acpi/ivrs.c: https://review.coreboot.org/c/coreboot/+/75506/comment/f5c3f7c5_e7653465 : PS1, Line 338: printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); > this warning message is misleading, since the ivrs table is generated by coreboot and isn't from age […] Sure. Will make it like: 'NULL ivrs' ? suggestion ? -- To view, visit https://review.coreboot.org/c/coreboot/+/75506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeb0ea3bcaa3512a93500588ad4f11046edee61f Gerrit-Change-Number: 75506 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 01 Jun 2023 15:35:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mainboard/ibm/sbp1: Enable vtd & x2apic
by Naresh Solanki (Code Review) 01 Jun '23

01 Jun '23

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75582?usp=email ) Change subject: mainboard/ibm/sbp1: Enable vtd & x2apic ...................................................................... mainboard/ibm/sbp1: Enable vtd & x2apic Enabled Vtd & x2apic in devicetree for sbp1 mainboard. TEST=Build for sbp1. Signed-off-by: Naresh Solanki <Naresh.Solanki(a)9elements.com> Change-Id: I3439fab47d015ab2402866433499d0aeae973a41 --- M src/mainboard/ibm/sbp1/devicetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/75582/1 diff --git a/src/mainboard/ibm/sbp1/devicetree.cb b/src/mainboard/ibm/sbp1/devicetree.cb index 098fd9a..e74de1c 100644 --- a/src/mainboard/ibm/sbp1/devicetree.cb +++ b/src/mainboard/ibm/sbp1/devicetree.cb @@ -2,6 +2,10 @@ chip soc/intel/xeon_sp/spr + # configure VT-d + register "vtd_support" = "1" + register "x2apic" = "1" + device domain 0 on device pci 16.3 off end # Serial controller: Intel Corporation Device 1be3 -- To view, visit https://review.coreboot.org/c/coreboot/+/75582?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3439fab47d015ab2402866433499d0aeae973a41 Gerrit-Change-Number: 75582 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/intel/xeon_sp/spr: Add chip config to enable x2apic
by Naresh Solanki (Code Review) 01 Jun '23

01 Jun '23

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75581?usp=email ) Change subject: soc/intel/xeon_sp/spr: Add chip config to enable x2apic ...................................................................... soc/intel/xeon_sp/spr: Add chip config to enable x2apic Add chip config to enable x2apic from mainboard devicetree. TEST=Build for sbp1. Signed-off-by: Naresh Solanki <Naresh.Solanki(a)9elements.com> Change-Id: I81e9f473d0400173afd25278845be5ff34fd7e04 --- M src/soc/intel/xeon_sp/spr/chip.h M src/soc/intel/xeon_sp/spr/romstage.c 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/75581/1 diff --git a/src/soc/intel/xeon_sp/spr/chip.h b/src/soc/intel/xeon_sp/spr/chip.h index 28af550..5144372 100644 --- a/src/soc/intel/xeon_sp/spr/chip.h +++ b/src/soc/intel/xeon_sp/spr/chip.h @@ -46,6 +46,7 @@ uint32_t pstate_req_ratio; uint8_t vtd_support; + uint8_t x2apic; /* Generic IO decode ranges */ uint32_t gen1_dec; diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 8f4e98e..8893bf6 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -164,7 +164,7 @@ * coreboot currently can only switch from XAPIC to X2APIC, * so always select XAPIC mode here. */ - m_cfg->X2apic = 0; + m_cfg->X2apic = config->x2apic; m_cfg->serialDebugMsgLvl = 0x3; -- To view, visit https://review.coreboot.org/c/coreboot/+/75581?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81e9f473d0400173afd25278845be5ff34fd7e04 Gerrit-Change-Number: 75581 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/intel/{alderlake, meteorlake}: Properly assign the FSP ASPM UPD
by Tim Crawford (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Felix Singer, Kapil Porwal, Sean Rhodes, Subrata Banik, Tarun Tuli. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75481?usp=email ) Change subject: soc/intel/{alderlake, meteorlake}: Properly assign the FSP ASPM UPD ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/75481/comment/c2b1029f_24f9ec6b : PS1, Line 899: if (rp_cfg->pcie_rp_aspm) : s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm); : else if (CONFIG(PCIEXP_ASPM)) /* use auto (FSP default) if PCIEXP_ASPM is enabled */ : s_cfg->PcieRpAspm[i] = ASPM_AUTO; : else : s_cfg->PcieRpAspm[i] = ASPM_DISABLE; > > Those aren't disjoint cases. I want both of them. […] `pcie_rp_aspm` is a *per port* config. So AFAICT, the only way to have ASPM enabled on some ports and disabled on others *is* to disable `PCIEXP_ASPM` and explicitly set `pcie_rp_aspm` per port. If you leave `PCIEXP_ASPM` enabled and set `pcie_rp_aspm = ASPM_DISABLE` for a single port, then this still sets it to `ASPM_AUTO`. e.g., CB:63466 -- To view, visit https://review.coreboot.org/c/coreboot/+/75481?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib20c7466c79c3e0757ebda98240a529920c32a16 Gerrit-Change-Number: 75481 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 15:01:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for SataPortsEnable
by Himanshu Sahdev (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Felix Singer, Mario Scheithauer, Maxim Polyakov, Nico Huber, Sean Rhodes, Werner Zeh. Himanshu Sahdev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75553?usp=email ) Change subject: soc/intel/apollolake: Switch to snake case for SataPortsEnable ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75553/comment/1f287ff1_d1231672 : PS3, Line 9: from pascal case -- To view, visit https://review.coreboot.org/c/coreboot/+/75553?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e Gerrit-Change-Number: 75553 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 15:01:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/meteorlake: Hook up UPD PchHdaSdiEnable
by Himanshu Sahdev (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Kapil Porwal, Ronak Kanabar, Subrata Banik. Himanshu Sahdev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75529?usp=email ) Change subject: soc/intel/meteorlake: Hook up UPD PchHdaSdiEnable ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/meteorlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/75529/comment/a46bf695_c3bca916 : PS3, Line 227: remove one space here. -- To view, visit https://review.coreboot.org/c/coreboot/+/75529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43f1e59d28fc07218f8e25266f8ce3bdcf3f6e5c Gerrit-Change-Number: 75529 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 14:51:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for SataPortsEnable
by Jan Samek (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Felix Singer, Mario Scheithauer, Maxim Polyakov, Nico Huber, Sean Rhodes, Werner Zeh. Jan Samek has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75553?usp=email ) Change subject: soc/intel/apollolake: Switch to snake case for SataPortsEnable ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75553?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e Gerrit-Change-Number: 75553 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 14:33:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: include/cpu/x86: Simplify en/dis cache functions
by Himanshu Sahdev (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Arthur Heymans, Felix Singer, Jérémy Compostella, Lean Sheng Tan, Subrata Banik. Himanshu Sahdev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75552?usp=email ) Change subject: include/cpu/x86: Simplify en/dis cache functions ...................................................................... Patch Set 3: (1 comment) File src/include/cpu/x86/cache.h: https://review.coreboot.org/c/coreboot/+/75552/comment/d7518f89_9b504718 : PS2, Line 48: CR0_CacheDisable > > > > want me to change it to screaming snake case -> CR0_CACHE_DISABLE? > > > yup, this is what make sense. > > > > > > > > > > > Also, these macros being in use already, better to do it in different CL to change everywhere. > > > > > > sure > > > > CR0_CD and CR0_NW is fine too IMO > > +1 Done. May be we should drop the usage instead of changing the case of these macros throughout. -- To view, visit https://review.coreboot.org/c/coreboot/+/75552?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81688e8bbb073e1d09ecf63f3f33e1651dbd778e Gerrit-Change-Number: 75552 Gerrit-PatchSet: 3 Gerrit-Owner: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 14:29:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/mediatek/common: Add support for power supply TPS65132S
by Paul Menzel (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Ruihai Zhou. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75488?usp=email ) Change subject: soc/mediatek/common: Add support for power supply TPS65132S ...................................................................... Patch Set 5: (2 comments) File src/soc/mediatek/common/tps65132s.c: https://review.coreboot.org/c/coreboot/+/75488/comment/99a5db69_b8362c1c : PS5, Line 35: mdelay(10); Where do these delays come from? https://review.coreboot.org/c/coreboot/+/75488/comment/63da1d64_5c0ba5de : PS5, Line 62: mdelay(50); For such long delays, a comment mentioning section in the datasheet would be nice. [1]: https://www.ti.com/lit/ds/symlink/tps65132.pdf?ts=1685628433524&ref_url=htt… -- To view, visit https://review.coreboot.org/c/coreboot/+/75488?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad2c9bdea5824455efcef18b44876111061cfa1a Gerrit-Change-Number: 75488 Gerrit-PatchSet: 5 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 14:10:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit June 2023