coreboot-gerrit June 2023

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[S] Change in coreboot[master]: mb/google/rex: Update GPIO PAD IO Standby State
by Subrata Banik (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Bora Guvendik, Kapil Porwal, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75555?usp=email ) Change subject: mb/google/rex: Update GPIO PAD IO Standby State ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/rex/variants/rex0/gpio.c: https://review.coreboot.org/c/coreboot/+/75555/comment/d41dfbce_63690b06 : PS3, Line 19: PAD_CFG_NF_IOSSTATE(GPP_A00, UP_20K, DEEP, NF1, IGNORE), > It was not #1, it was being programmed as NF1. > > FSP was modifying the IO Standby State to PAD_CFG1_IOSSTATE_IGNORE before FSP started skipping GpioConfigureIoStandbyState. Now that we are skipping in FSP, coreboot is setting IO Standby State to PAD_CFG1_IOSSTATE_TxLASTRxE, and seems this caused the keyboard / Type-C issues. > > "wondering why can't we configure as below or even adding LOCK" > PAD_CFG_NF sets PAD_CFG1_IOSSTATE_TxLASTRxE, instead of what we need which is PAD_CFG1_IOSSTATE_IGNORE understood then we need to add the same changes to add different rex variants. -- To view, visit https://review.coreboot.org/c/coreboot/+/75555?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If96c1e71fdde784a55fe079875915ffa5a4f548a Gerrit-Change-Number: 75555 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 16:36:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bora Guvendik <bora.guvendik(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Update GPIO PAD IO Standby State
by Bora Guvendik (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75555?usp=email ) Change subject: mb/google/rex: Update GPIO PAD IO Standby State ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75555/comment/27be73d3_18a34640 : PS3, Line 9: Type-c > Type-C I will change Patchset: PS3: > we need to apply this on all other variants as well ? yes, should I add changes for screebo to this patch? File src/mainboard/google/rex/variants/rex0/gpio.c: https://review.coreboot.org/c/coreboot/+/75555/comment/94428948_90e1df1b : PS3, Line 19: PAD_CFG_NF_IOSSTATE(GPP_A00, UP_20K, DEEP, NF1, IGNORE), > let me understand the problem, was the issue due to #1 or #2 below or for both ? […] It was not #1, it was being programmed as NF1. FSP was modifying the IO Standby State to PAD_CFG1_IOSSTATE_IGNORE before FSP started skipping GpioConfigureIoStandbyState. Now that we are skipping in FSP, coreboot is setting IO Standby State to PAD_CFG1_IOSSTATE_TxLASTRxE, and seems this caused the keyboard / Type-C issues. "wondering why can't we configure as below or even adding LOCK" PAD_CFG_NF sets PAD_CFG1_IOSSTATE_TxLASTRxE, instead of what we need which is PAD_CFG1_IOSSTATE_IGNORE -- To view, visit https://review.coreboot.org/c/coreboot/+/75555?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If96c1e71fdde784a55fe079875915ffa5a4f548a Gerrit-Change-Number: 75555 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 16:24:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Revert "soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum defini...
by Subrata Banik (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Angel Pons, Jeremy Soller, Tarun Tuli, Tim Crawford. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75280?usp=email ) Change subject: Revert "soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitions" ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75280?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60c0ea08513fcb0035449ea3fef1681de528c545 Gerrit-Change-Number: 75280 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 16:08:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: Revert "soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum defini...
by Tim Crawford (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Angel Pons, Jeremy Soller, Subrata Banik, Tarun Tuli. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75280?usp=email ) Change subject: Revert "soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitions" ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > > The above seems reasonable. […] Per discussion in CB:75481, we will go ahead with this revert to restore behavior. -- To view, visit https://review.coreboot.org/c/coreboot/+/75280?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60c0ea08513fcb0035449ea3fef1681de528c545 Gerrit-Change-Number: 75280 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 16:05:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/intel/{alderlake, meteorlake}: Properly assign the FSP ASPM UPD
by Subrata Banik (Code Review) 01 Jun '23

01 Jun '23

Subrata Banik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/75481?usp=email ) Change subject: soc/intel/{alderlake, meteorlake}: Properly assign the FSP ASPM UPD ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/75481?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib20c7466c79c3e0757ebda98240a529920c32a16 Gerrit-Change-Number: 75481 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[XS] Change in coreboot[master]: soc/intel/{alderlake, meteorlake}: Properly assign the FSP ASPM UPD
by Subrata Banik (Code Review) 01 Jun '23

01 Jun '23

Attention is currently required from: Felix Singer, Kapil Porwal, Sean Rhodes, Tarun Tuli, Tim Crawford. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75481?usp=email ) Change subject: soc/intel/{alderlake, meteorlake}: Properly assign the FSP ASPM UPD ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/75481/comment/682e28b9_ff1ce991 : PS1, Line 899: if (rp_cfg->pcie_rp_aspm) : s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm); : else if (CONFIG(PCIEXP_ASPM)) /* use auto (FSP default) if PCIEXP_ASPM is enabled */ : s_cfg->PcieRpAspm[i] = ASPM_AUTO; : else : s_cfg->PcieRpAspm[i] = ASPM_DISABLE; > `pcie_rp_aspm` is a *per port* config. So AFAICT, the only way to have ASPM enabled on some ports and disabled on others *is* to disable `PCIEXP_ASPM` and explicitly set `pcie_rp_aspm` per port. > > If you leave `PCIEXP_ASPM` enabled and set `pcie_rp_aspm = ASPM_DISABLE` for a single port, then this still sets it to `ASPM_AUTO`. > > e.g., CB:63466 Lets revert the CB:70719 CL. -- To view, visit https://review.coreboot.org/c/coreboot/+/75481?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib20c7466c79c3e0757ebda98240a529920c32a16 Gerrit-Change-Number: 75481 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 01 Jun 2023 15:55:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Use SSD type for SATA ports
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75367?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Use SSD type for SATA ports ...................................................................... mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Use SSD type for SATA ports There are only SSD connected to SATA ports on this mainboard. To prevent misbehavior, set the correct hard drive type for enabled SATA ports. BUG=none TEST=Boot into OS and check the stability of the SSD Change-Id: I2c2b0548865e87859a1d742295e09a731bfb3f76 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75367 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jan Samek <jan.samek(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb 3 files changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jan Samek: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index 2b2c32d..1291497 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -69,6 +69,8 @@ device pci 12.0 on # - SATA register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" + register "sata_ports_ssd[0]" = "1" + register "sata_ports_ssd[1]" = "1" register "DisableSataSalpSupport" = "1" register "sata_speed" = "SATA_GEN2" end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 15ca3f1..b308ab2 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -69,6 +69,8 @@ device pci 12.0 on # - SATA register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" + register "sata_ports_ssd[0]" = "1" + register "sata_ports_ssd[1]" = "1" register "DisableSataSalpSupport" = "1" register "sata_speed" = "SATA_GEN2" end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index 3c907e3..1885e81 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -40,6 +40,8 @@ device pci 12.0 on # - SATA register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" + register "sata_ports_ssd[0]" = "1" + register "sata_ports_ssd[1]" = "1" register "DisableSataSalpSupport" = "1" register "sata_speed" = "SATA_GEN2" end -- To view, visit https://review.coreboot.org/c/coreboot/+/75367?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c2b0548865e87859a1d742295e09a731bfb3f76 Gerrit-Change-Number: 75367 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/intel/apollolake: Make hard drive type for SATA ports configurable
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75366?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/apollolake: Make hard drive type for SATA ports configurable ...................................................................... soc/intel/apollolake: Make hard drive type for SATA ports configurable Intel's APL FSP offers the possibility to select the connected hard drive type to SATA ports. One has the option to choose between HDD ('0' - default) and SSD ('1'). This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I52c3566fb3c959ada6be33f0546ac331f4867d10 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75366 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jan Samek <jan.samek(a)siemens.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jan Samek: Looks good to me, approved diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index bd40595..7147011 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -739,6 +739,8 @@ silconfig->SpeedLimit = cfg->sata_speed; memcpy(silconfig->SataPortsEnable, cfg->SataPortsEnable, sizeof(silconfig->SataPortsEnable)); + memcpy(silconfig->SataPortsSolidStateDrive, cfg->sata_ports_ssd, + sizeof(silconfig->SataPortsSolidStateDrive)); } /* Sata Power Optimisation */ diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 3951880..45b60d3 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -109,6 +109,9 @@ /* Sata Ports Enable */ uint8_t SataPortsEnable[2]; + /* Sata Ports Solid State Drive */ + uint8_t sata_ports_ssd[2]; + /* Specifies on which IRQ the SCI will internally appear. */ uint8_t sci_irq; -- To view, visit https://review.coreboot.org/c/coreboot/+/75366?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52c3566fb3c959ada6be33f0546ac331f4867d10 Gerrit-Change-Number: 75366 Gerrit-PatchSet: 5 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Limit SATA speed to Gen 2
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75365?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Limit SATA speed to Gen 2 ...................................................................... mb/siemens/{mc_apl2,mc_apl5,mc_apl6}: Limit SATA speed to Gen 2 Due to mainboard restrictions a SATA link at Gen 3 can cause issues as the margin is not big enough. Limit SATA speed to Gen 2 to achieve a more robust SATA connection. Change-Id: Ifdea4542836b9c75b5507324fbb06b9566a6fe1d Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75365 Reviewed-by: Jan Samek <jan.samek(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb 3 files changed, 3 insertions(+), 0 deletions(-) Approvals: Jan Samek: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index b515170..2b2c32d 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -70,6 +70,7 @@ register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "DisableSataSalpSupport" = "1" + register "sata_speed" = "SATA_GEN2" end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 92bba65..15ca3f1 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -70,6 +70,7 @@ register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "DisableSataSalpSupport" = "1" + register "sata_speed" = "SATA_GEN2" end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "0" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index 8223f68..3c907e3 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -41,6 +41,7 @@ register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "DisableSataSalpSupport" = "1" + register "sata_speed" = "SATA_GEN2" end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" -- To view, visit https://review.coreboot.org/c/coreboot/+/75365?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdea4542836b9c75b5507324fbb06b9566a6fe1d Gerrit-Change-Number: 75365 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/apollolake: Make SATA speed limit configurable
by Felix Held (Code Review) 01 Jun '23

01 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75364?usp=email ) Change subject: soc/intel/apollolake: Make SATA speed limit configurable ...................................................................... soc/intel/apollolake: Make SATA speed limit configurable In cases where there are limitations on the mainboard it can be necessary to limit the used SATA speed even though both, the SATA controller and disk drive support a higher speed rate. The FSP parameter 'SpeedLimit' allows to set the speed limit. It should be noted that Gen 3 equals the default value '0'. This means that inside FSP the same code is executed. This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I9c3eda0649546e3a40eb24a015b7c6efd8f90e0f Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75364 Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Reviewed-by: Jan Samek <jan.samek(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 11 insertions(+), 0 deletions(-) Approvals: Jan Samek: Looks good to me, approved build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index e7a8168..bd40595 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -736,6 +736,7 @@ /* SATA config */ if (is_devfn_enabled(PCH_DEVFN_SATA)) { silconfig->SataSalpSupport = !(cfg->DisableSataSalpSupport); + silconfig->SpeedLimit = cfg->sata_speed; memcpy(silconfig->SataPortsEnable, cfg->SataPortsEnable, sizeof(silconfig->SataPortsEnable)); } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index a92d982..3951880 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -25,6 +25,13 @@ PNP_PERF_POWER, }; +enum sata_speed_limit { + SATA_DEFAULT = 0, + SATA_GEN1, + SATA_GEN2, + SATA_GEN3 +}; + struct soc_intel_apollolake_config { /* Common structure containing soc config data required by common code*/ @@ -215,6 +222,9 @@ /* Sata Power Optimisation */ uint8_t SataPwrOptimizeDisable; + + /* SATA speed limit */ + enum sata_speed_limit sata_speed; }; typedef struct soc_intel_apollolake_config config_t; -- To view, visit https://review.coreboot.org/c/coreboot/+/75364?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c3eda0649546e3a40eb24a015b7c6efd8f90e0f Gerrit-Change-Number: 75364 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: merged

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