coreboot-gerrit June 2023

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[S] Change in coreboot[master]: soc/amd/*/root_complex: use VGA_MMIO_* defines
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75668?usp=email ) Change subject: soc/amd/*/root_complex: use VGA_MMIO_* defines ...................................................................... soc/amd/*/root_complex: use VGA_MMIO_* defines Replace the magic constants by using defines. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I16179a37b6ee19bc3b4862b7dcb3bbc4caf63f2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75668 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/phoenix/root_complex.c M src/soc/amd/picasso/root_complex.c 5 files changed, 10 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index cb35662..bbddfab 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -6,6 +6,7 @@ #include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> #include <arch/ioapic.h> +#include <arch/vga.h> #include <cbmem.h> #include <console/console.h> #include <device/device.h> @@ -121,7 +122,7 @@ ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB); /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_resource_kb(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); + mmio_resource_kb(dev, idx++, VGA_MMIO_BASE / KiB, VGA_MMIO_SIZE / KiB); /* 0xc0000 - 0xfffff: Option ROM */ reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index 071903d..64d90ee 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -8,6 +8,7 @@ #include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> #include <arch/ioapic.h> +#include <arch/vga.h> #include <cbmem.h> #include <console/console.h> #include <device/device.h> @@ -136,7 +137,7 @@ ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB); /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_resource_kb(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); + mmio_resource_kb(dev, idx++, VGA_MMIO_BASE / KiB, VGA_MMIO_SIZE / KiB); /* 0xc0000 - 0xfffff: Option ROM */ reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 492a588..6f93502 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -8,6 +8,7 @@ #include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> #include <arch/ioapic.h> +#include <arch/vga.h> #include <cbmem.h> #include <console/console.h> #include <device/device.h> @@ -164,7 +165,7 @@ ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB); /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_resource_kb(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); + mmio_resource_kb(dev, idx++, VGA_MMIO_BASE / KiB, VGA_MMIO_SIZE / KiB); /* 0xc0000 - 0xfffff: Option ROM */ reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c index f7c4c1e..64f9ca4 100644 --- a/src/soc/amd/phoenix/root_complex.c +++ b/src/soc/amd/phoenix/root_complex.c @@ -8,6 +8,7 @@ #include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> #include <arch/ioapic.h> +#include <arch/vga.h> #include <cbmem.h> #include <console/console.h> #include <device/device.h> @@ -136,7 +137,7 @@ ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB); /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_resource_kb(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); + mmio_resource_kb(dev, idx++, VGA_MMIO_BASE / KiB, VGA_MMIO_SIZE / KiB); /* 0xc0000 - 0xfffff: Option ROM */ reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 7a83197..e61208f 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -6,6 +6,7 @@ #include <amdblocks/memmap.h> #include <amdblocks/ioapic.h> #include <arch/ioapic.h> +#include <arch/vga.h> #include <assert.h> #include <cbmem.h> #include <console/console.h> @@ -121,7 +122,7 @@ ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB); /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_resource_kb(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); + mmio_resource_kb(dev, idx++, VGA_MMIO_BASE / KiB, VGA_MMIO_SIZE / KiB); /* 0xc0000 - 0xfffff: Option ROM */ reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); -- To view, visit https://review.coreboot.org/c/coreboot/+/75668?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16179a37b6ee19bc3b4862b7dcb3bbc4caf63f2e Gerrit-Change-Number: 75668 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/amd/stoneyridge/acpi/sb_pci0_fch: use VGA_MMIO_* defines
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75667?usp=email ) Change subject: soc/amd/stoneyridge/acpi/sb_pci0_fch: use VGA_MMIO_* defines ...................................................................... soc/amd/stoneyridge/acpi/sb_pci0_fch: use VGA_MMIO_* defines Replace the magic constants by using defines. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I94ad285a2c5712d352d4f92697fc3140847d88de Reviewed-on: https://review.coreboot.org/c/coreboot/+/75667 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 08f7a31..37910aa 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/alib.h> +#include <arch/vga.h> External(\_SB.ALIB, MethodObj) @@ -71,7 +72,7 @@ 0xf300 /* length */ ) - Memory32Fixed(READONLY, 0x000a0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, VGA_MMIO_BASE, VGA_MMIO_SIZE, VGAM) /* VGA memory space */ Memory32Fixed(READONLY, 0x000c0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ /* memory space for PCI BARs below 4GB */ -- To view, visit https://review.coreboot.org/c/coreboot/+/75667?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94ad285a2c5712d352d4f92697fc3140847d88de Gerrit-Change-Number: 75667 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/amd/stoneyridge/northbridge: use VGA_MMIO_* defines
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75666?usp=email ) Change subject: soc/amd/stoneyridge/northbridge: use VGA_MMIO_* defines ...................................................................... soc/amd/stoneyridge/northbridge: use VGA_MMIO_* defines Replace the magic constants by using defines. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6303e5a697a7ad09a48cb7a2c79fa76f4c6ce232 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75666 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/stoneyridge/northbridge.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 90d227a..b4c18d3 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -7,6 +7,7 @@ #include <device/pci_ops.h> #include <arch/hpet.h> #include <arch/ioapic.h> +#include <arch/vga.h> #include <acpi/acpi.h> #include <acpi/acpigen.h> #include <cbmem.h> @@ -365,7 +366,7 @@ ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB); /* 0xa0000 -> 0xbffff: legacy VGA */ - mmio_resource_kb(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); + mmio_resource_kb(dev, idx++, VGA_MMIO_BASE / KiB, VGA_MMIO_SIZE / KiB); /* 0xc0000 -> 0xfffff: Option ROM */ reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); -- To view, visit https://review.coreboot.org/c/coreboot/+/75666?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6303e5a697a7ad09a48cb7a2c79fa76f4c6ce232 Gerrit-Change-Number: 75666 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: nb/amd/pi/00730f01/northbridge: use VGA_MMIO_* defines
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75665?usp=email ) Change subject: nb/amd/pi/00730f01/northbridge: use VGA_MMIO_* defines ...................................................................... nb/amd/pi/00730f01/northbridge: use VGA_MMIO_* defines Replace the magic constants by using defines. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie558de02cd4f8914409639a74c54b57df3418ed9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75665 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/amd/pi/00730F01/northbridge.c 1 file changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 355820a..116cf63 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -6,6 +6,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_ivrs.h> #include <arch/ioapic.h> +#include <arch/vga.h> #include <types.h> #include <device/device.h> #include <device/pci.h> @@ -139,7 +140,7 @@ * 0xa0000 - 0xbffff: legacy VGA * 0xc0000 - 0xfffff: option ROMs and SeaBIOS (if used) */ - mmio_resource_kb(dev, index++, 0xa0000 >> 10, (0xc0000 - 0xa0000) >> 10); + mmio_resource_kb(dev, index++, VGA_MMIO_BASE >> 10, VGA_MMIO_SIZE >> 10); reserved_ram_resource_kb(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10); if (fx_devs == 0) -- To view, visit https://review.coreboot.org/c/coreboot/+/75665?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie558de02cd4f8914409639a74c54b57df3418ed9 Gerrit-Change-Number: 75665 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: sb/amd/pi/hudson/acpi/fch: use VGA_MMIO_* defines
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75664?usp=email ) Change subject: sb/amd/pi/hudson/acpi/fch: use VGA_MMIO_* defines ...................................................................... sb/amd/pi/hudson/acpi/fch: use VGA_MMIO_* defines Replace the magic constants by using defines. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3cb150aee8030d1a419f3596ddbc32cb29f65b52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75664 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/southbridge/amd/pi/hudson/acpi/fch.asl 1 file changed, 3 insertions(+), 1 deletion(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/southbridge/amd/pi/hudson/acpi/fch.asl b/src/southbridge/amd/pi/hudson/acpi/fch.asl index 10f25a1..834b346 100644 --- a/src/southbridge/amd/pi/hudson/acpi/fch.asl +++ b/src/southbridge/amd/pi/hudson/acpi/fch.asl @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/vga.h> + /* System Bus */ /* _SB.PCI0 */ @@ -87,7 +89,7 @@ 0xF300 /* length */ ) - Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, VGA_MMIO_BASE, VGA_MMIO_SIZE, VGAM) /* VGA memory space */ Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ /* memory space for PCI BARs below 4GB */ -- To view, visit https://review.coreboot.org/c/coreboot/+/75664?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3cb150aee8030d1a419f3596ddbc32cb29f65b52 Gerrit-Change-Number: 75664 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: soc/amd/phoenix/Kconfig: temporary drop VGA_BIOS_FILE
by Fred Reitberger (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Felix Held, Jason Glenesk, Matt DeVillier. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75484?usp=email ) Change subject: soc/amd/phoenix/Kconfig: temporary drop VGA_BIOS_FILE ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75484?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbc6cbe1e371d8d247f86555a5361ed237897dea Gerrit-Change-Number: 75484 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 07 Jun 2023 21:44:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Introduce configs for TME exclusion range and new k...
by Pratikkumar V Prajapati (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Paul Menzel, Subrata Banik. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75625?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common: Introduce configs for TME exclusion range and new key generation ...................................................................... soc/intel/common: Introduce configs for TME exclusion range and new key generation Add following config options. 1. INTEL_TME_GEN_NEW_KEY_EACH_WARM_REBOOT Program Intel TME to generate a new key for each warm reboot. TME always generates a new key on each cold reboot. With this option enabled TME generates a new key even in warm reboot. Without this option TME reuses the key for warm reboot. 2. INTEL_TME_EXCLUDE_CBMEM Allows CBMEM to get excluded from being encrypted by Intel TME. When TME is enabled it encrypts whole DRAM. TME provides option to carve out a region of physical memory to get excluded from encryption. With this config enabled, CBMEM does not get encrypted by TME. If TME is not programmed to generate a new key in warm reboot, exclusion range does not need be programmed due to the fact that TME uses same key in warm reboot if INTEL_TME_GEN_NEW_KEY_EACH_WARM_REBOOT is not set. But if TME is programmed to generate a new key in warm reboot, contents of the CBMEM get encrypted with a new key in each warm reboot case and that leads to loss of CBMEM data from previous warm boot. So enabling this config allows CBMEM to get excluded from being encrypted and can be accessed in warm reboot case also. Bug=b:276120526 TEST=Able to build rex Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Change-Id: Id5008fee07b97faadc7dd585f445295425173782 --- M src/soc/intel/common/block/cpu/Kconfig 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/75625/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5008fee07b97faadc7dd585f445295425173782 Gerrit-Change-Number: 75625 Gerrit-PatchSet: 2 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/common: Introduce configs for TME exclusion range and new k...
by Pratikkumar V Prajapati (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Paul Menzel, Subrata Banik. Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75625?usp=email ) Change subject: soc/intel/common: Introduce configs for TME exclusion range and new key generation ...................................................................... Patch Set 1: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75625/comment/56a3c09c_06ddf666 : PS1, Line 9: to allow cbmem to get : excluded from being encrypted by Intel TME > Why is that a useful thing to do? What problem is solved? Added more details https://review.coreboot.org/c/coreboot/+/75625/comment/49721313_b391508f : PS1, Line 10: excluded from being encrypted by Intel TME > Please add a dot/period at the end. Done https://review.coreboot.org/c/coreboot/+/75625/comment/6d7ef2b2_b7f96e2f : PS1, Line 9: Add INTEL_TME_EXCLUDE_CBMEM config option to allow cbmem to get : excluded from being encrypted by Intel TME : : Add INTEL_TME_GEN_NEW_KEY_EACH_REBOOT config option to program : TME to generate a new key for each reboot. > As you enumerate the changes, format it as a list? Done Patchset: PS1: > merge with the next CL This is common code change, shouldn't we keep this patch separate from MTL specific patch? File src/soc/intel/common/block/cpu/Kconfig: https://review.coreboot.org/c/coreboot/+/75625/comment/40e747b1_75d87aca : PS1, Line 150: Exclude CBMEM from being encrypted by Intel TME. > can u please elaborate this statement? Added more details https://review.coreboot.org/c/coreboot/+/75625/comment/d9415be6_35b1826b : PS1, Line 157: reboot > we should clarify what does reboot refers to? Added more details -- To view, visit https://review.coreboot.org/c/coreboot/+/75625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5008fee07b97faadc7dd585f445295425173782 Gerrit-Change-Number: 75625 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 07 Jun 2023 21:30:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/brya/acpi: NV12 enable signal should be off on GCOFF entry
by Tarun Tuli (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Eran Mitrani, Eric Lai. Hello Eran Mitrani, Eric Lai, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75533?usp=email to look at the new patch set (#5). Change subject: mb/google/brya/acpi: NV12 enable signal should be off on GCOFF entry ...................................................................... mb/google/brya/acpi: NV12 enable signal should be off on GCOFF entry Properly shutdown NV12 rail in the off sequence (current implementation leaves it asserted). BUG=b:286287940 TEST=NV12 now shuts down on GCOFF entry Change-Id: I7d338fc4a96f119617aff558413a5a9ac44c27d7 Signed-off-by: Tarun Tuli <taruntuli(a)google.com> --- M src/mainboard/google/brya/acpi/power.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/75533/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/75533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d338fc4a96f119617aff558413a5a9ac44c27d7 Gerrit-Change-Number: 75533 Gerrit-PatchSet: 5 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: [TEST ONLY] add VPRO features control by fw config
by Wonkyu Kim (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75714?usp=email ) Change subject: [TEST ONLY] add VPRO features control by fw config ...................................................................... Patch Set 2: (2 comments) File src/mainboard/google/rex/variants/rex0/cpulib.c: https://review.coreboot.org/c/coreboot/+/75714/comment/02daef39_af4d7a65 : PS1, Line 10: if(fw_config_probe(FW_CONFIG(TME, TME_DIS))) { > space required before the open parenthesis '(' Please fix. https://review.coreboot.org/c/coreboot/+/75714/comment/589f7822_66e1cef8 : PS1, Line 20: if(fw_config_probe(FW_CONFIG(KEYLOCKER, KEYLOCKER_DIS))) { > space required before the open parenthesis '(' Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/75714?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I746ba80279dc69d06ac9e06bfeae068e31d23694 Gerrit-Change-Number: 75714 Gerrit-PatchSet: 2 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 21:26:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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