coreboot-gerrit June 2023

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[M] Change in coreboot[master]: acpi: Add a debug option to print out tables in ACPICA compatible hex
by Kyösti Mälkki (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Arthur Heymans, Benjamin Doron, Lance Zhao, Nico Huber, Paul Menzel, Tim Wawrzynczak. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75677?usp=email ) Change subject: acpi: Add a debug option to print out tables in ACPICA compatible hex ...................................................................... Patch Set 5: Code-Review+1 (1 comment) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/75677/comment/9d570c95_1dd87411 : PS5, Line 2160: printk(BIOS_DEBUG, "Printing ACPI tables in ACPICA compatible format\n"); You can probably have arguments both ways whether to use BIOS_DEBUG or BIOS_SPEW here? -- To view, visit https://review.coreboot.org/c/coreboot/+/75677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc Gerrit-Change-Number: 75677 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 07 Jun 2023 19:06:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/phoenix: Hook up xhci ops in chipset.cb
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Eric Lai, Fred Reitberger, Jason Glenesk, Jon Murphy, Martin L Roth, Martin Roth, Matt DeVillier, Paul Menzel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75659?usp=email ) Change subject: soc/amd/phoenix: Hook up xhci ops in chipset.cb ...................................................................... Patch Set 6: Code-Review+2 (1 comment) Patchset: PS3: > as far as i know, this should be done for all 4 xhci controller. […] changed this for the other AMD SoCs in CB:75713 -- To view, visit https://review.coreboot.org/c/coreboot/+/75659?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib59874948725966b04b54def3f6de463afeda709 Gerrit-Change-Number: 75659 Gerrit-PatchSet: 6 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 19:02:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd: add ops xhci_pci_ops to XHCI controllers in devicetree
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75713?usp=email ) Change subject: soc/amd: add ops xhci_pci_ops to XHCI controllers in devicetree ...................................................................... soc/amd: add ops xhci_pci_ops to XHCI controllers in devicetree Instead of adding the new PCI IDs of the XHCI controllers in every new chip generation to the pci_xhci driver, bind the driver to the internal PCI devices of the XHCI controllers via the device ops statement in the chipset devicetree. The PCI device function of the XHCI2 controller in Mendocino can be either a dummy device or the XHCI controller, so the device ops are attached to that device in the mainboard devicetree instead. The Glinda code is right now just a copy of the Mendocino code, so it'll change in the future, but for consistency the equivalent changes to those in Mendocino are applied there too. Since the device ops are now attached to the devices via the static devicetree entry, also remove both the xhci_pci_driver struct and the amd_pci_device_ids array from drivers/usb/pci_xhci/pci_xhci.c. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9c455002c6d2aac576fe24eee0c31744b4507bb0 --- M src/drivers/usb/pci_xhci/pci_xhci.c M src/mainboard/amd/birman/devicetree_glinda.cb M src/mainboard/amd/chausie/devicetree.cb M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb M src/soc/amd/cezanne/chipset.cb M src/soc/amd/glinda/chipset.cb M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb M src/soc/amd/picasso/chipset.cb 9 files changed, 20 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/75713/1 diff --git a/src/drivers/usb/pci_xhci/pci_xhci.c b/src/drivers/usb/pci_xhci/pci_xhci.c index ca51278..6d022d1 100644 --- a/src/drivers/usb/pci_xhci/pci_xhci.c +++ b/src/drivers/usb/pci_xhci/pci_xhci.c @@ -251,20 +251,3 @@ .acpi_fill_ssdt = xhci_fill_ssdt, .acpi_name = xhci_acpi_name, }; - -static const unsigned short amd_pci_device_ids[] = { - PCI_DID_AMD_FAM17H_MODEL18H_XHCI0, - PCI_DID_AMD_FAM17H_MODEL18H_XHCI1, - PCI_DID_AMD_FAM17H_MODEL20H_XHCI0, - PCI_DID_AMD_FAM17H_MODEL60H_XHCI, - PCI_DID_AMD_FAM17H_MODELA0H_XHCI0, - PCI_DID_AMD_FAM17H_MODELA0H_XHCI1, - PCI_DID_AMD_FAM17H_MODELA0H_XHCI2, - 0 -}; - -static const struct pci_driver xhci_pci_driver __pci_driver = { - .ops = &xhci_pci_ops, - .vendor = PCI_VID_AMD, - .devices = amd_pci_device_ids, -}; diff --git a/src/mainboard/amd/birman/devicetree_glinda.cb b/src/mainboard/amd/birman/devicetree_glinda.cb index d6ecae6..dfcd176 100644 --- a/src/mainboard/amd/birman/devicetree_glinda.cb +++ b/src/mainboard/amd/birman/devicetree_glinda.cb @@ -205,6 +205,7 @@ end device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C device ref xhci_2 on + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_2_root_hub on diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index 2e6511e..a186b2d 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -204,6 +204,7 @@ end device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C device ref xhci_2 on + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_2_root_hub on diff --git a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb index 835277a..b605e1c 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/skyrim/variants/baseboard/devicetree.cb @@ -175,6 +175,7 @@ end device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C device ref xhci_2 on # USB 2.0 (USB2) + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_2_root_hub on diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index c779390..0762ea1 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -28,6 +28,7 @@ device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor device pci 0.3 alias xhci_0 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_0_root_hub off @@ -53,6 +54,7 @@ end end device pci 0.4 alias xhci_1 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_1_root_hub off diff --git a/src/soc/amd/glinda/chipset.cb b/src/soc/amd/glinda/chipset.cb index ad477c7..bf7d67d 100644 --- a/src/soc/amd/glinda/chipset.cb +++ b/src/soc/amd/glinda/chipset.cb @@ -26,6 +26,7 @@ device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor device pci 0.3 alias xhci_0 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_0_root_hub off @@ -42,6 +43,7 @@ end end device pci 0.4 alias xhci_1 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_1_root_hub off @@ -71,6 +73,7 @@ device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C ops amd_internal_pcie_gpp_ops device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID + # When using this as XHCI2, the mainboard devicetree needs to add ops xhci_pci_ops end device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function diff --git a/src/soc/amd/mendocino/chipset_mendocino.cb b/src/soc/amd/mendocino/chipset_mendocino.cb index 691cca0..e40124f 100644 --- a/src/soc/amd/mendocino/chipset_mendocino.cb +++ b/src/soc/amd/mendocino/chipset_mendocino.cb @@ -22,6 +22,7 @@ device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor device pci 0.3 alias xhci_0 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_0_root_hub off @@ -38,6 +39,7 @@ end end device pci 0.4 alias xhci_1 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_1_root_hub off @@ -66,6 +68,7 @@ device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C ops amd_internal_pcie_gpp_ops device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID + # When using this as XHCI2, the mainboard devicetree needs to add ops xhci_pci_ops end device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function diff --git a/src/soc/amd/mendocino/chipset_rembrandt.cb b/src/soc/amd/mendocino/chipset_rembrandt.cb index fd31efe..394f057 100644 --- a/src/soc/amd/mendocino/chipset_rembrandt.cb +++ b/src/soc/amd/mendocino/chipset_rembrandt.cb @@ -24,6 +24,7 @@ device pci 0.1 alias gfx_hda off end # Display HD Audio Controller (GFXAZ) device pci 0.2 alias crypto off end # Crypto Coprocessor device pci 0.3 alias xhci_0 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_0_root_hub off @@ -40,6 +41,7 @@ end end device pci 0.4 alias xhci_1 off + ops xhci_pci_ops chip drivers/usb/acpi register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_1_root_hub off @@ -69,6 +71,7 @@ device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C ops amd_internal_pcie_gpp_ops device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID + # When using this as XHCI2, the mainboard devicetree needs to add ops xhci_pci_ops end device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function diff --git a/src/soc/amd/picasso/chipset.cb b/src/soc/amd/picasso/chipset.cb index 6d6177f..bf2c879 100644 --- a/src/soc/amd/picasso/chipset.cb +++ b/src/soc/amd/picasso/chipset.cb @@ -22,8 +22,12 @@ device pci 0.0 alias gfx off ops amd_graphics_ops end # internal GPU device pci 0.1 alias gfx_hda off end # display HD Audio controller device pci 0.2 alias crypto off end # cryptography coprocessor - device pci 0.3 alias xhci_0 off end - device pci 0.4 alias xhci_1 off end + device pci 0.3 alias xhci_0 off + ops xhci_pci_ops + end + device pci 0.4 alias xhci_1 off + ops xhci_pci_ops + end device pci 0.5 alias acp off ops amd_acp_ops end # audio co-processor device pci 0.6 alias hda off end # main HD Audio Controller device pci 0.7 alias mp2 off end # sensor fusion hub (MP2) -- To view, visit https://review.coreboot.org/c/coreboot/+/75713?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c455002c6d2aac576fe24eee0c31744b4507bb0 Gerrit-Change-Number: 75713 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/amd/block/ivrs: Add NULL check for IVRS
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Arthur Heymans, Fred Reitberger, Jason Glenesk, Matt DeVillier, Naresh Solanki, Raul Rangel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75506?usp=email ) Change subject: soc/amd/block/ivrs: Add NULL check for IVRS ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/acpi/ivrs.c: https://review.coreboot.org/c/coreboot/+/75506/comment/2b1b979f_4195fffb : PS1, Line 338: printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); > Sure. Will make it like: […] i'd say "ivrs is NULL". "NULL ivrs" would work too -- To view, visit https://review.coreboot.org/c/coreboot/+/75506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeb0ea3bcaa3512a93500588ad4f11046edee61f Gerrit-Change-Number: 75506 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 19:00:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/glinda/acpi: use ROOT_BRIDGE macro
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75595?usp=email ) Change subject: soc/amd/glinda/acpi: use ROOT_BRIDGE macro ...................................................................... soc/amd/glinda/acpi: use ROOT_BRIDGE macro Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The soc/amd/common/acpi/lpc.asl file which was included in the now removed pci0.asl file now gets included in the correct scope in the soc.asl file. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I373c171f7f4754391012b41d44965561ced4f0b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75595 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- D src/soc/amd/glinda/acpi/pci0.asl M src/soc/amd/glinda/acpi/soc.asl 2 files changed, 6 insertions(+), 27 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/glinda/acpi/pci0.asl b/src/soc/amd/glinda/acpi/pci0.asl deleted file mode 100644 index 3f29c33..0000000 --- a/src/soc/amd/glinda/acpi/pci0.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Update for Glinda */ - -Device(PCI0) { - Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ - Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - - /* Operating System Capabilities Method */ - Method(_OSC, 4) { - CreateDWordField(Arg3, 0, CDW1) /* Capabilities dword 1 */ - - /* Check for proper PCI/PCIe UUID */ - If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { - /* Let OS control everything */ - Return (Arg3) - } Else { - CDW1 |= 4 /* Unrecognized UUID */ - Return (Arg3) - } - } - - /* 0:14.3 - LPC */ - #include <soc/amd/common/acpi/lpc.asl> - -} /* End PCI0 scope */ diff --git a/src/soc/amd/glinda/acpi/soc.asl b/src/soc/amd/glinda/acpi/soc.asl index b810a2b..964cad9 100644 --- a/src/soc/amd/glinda/acpi/soc.asl +++ b/src/soc/amd/glinda/acpi/soc.asl @@ -2,6 +2,7 @@ /* TODO: Update for Glinda */ +#include <soc/amd/common/acpi/pci_root.asl> #include "globalnvs.asl" Scope(\_SB) { @@ -18,7 +19,11 @@ #include "mmio.asl" - #include "pci0.asl" + ROOT_BRIDGE(PCI0) + + Scope(PCI0) { + #include <soc/amd/common/acpi/lpc.asl> + } /* End PCI0 scope */ } /* End \_SB scope */ #include <soc/amd/common/acpi/alib.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/75595?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I373c171f7f4754391012b41d44965561ced4f0b7 Gerrit-Change-Number: 75595 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/phoenix/acpi: use ROOT_BRIDGE macro
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75594?usp=email ) Change subject: soc/amd/phoenix/acpi: use ROOT_BRIDGE macro ...................................................................... soc/amd/phoenix/acpi: use ROOT_BRIDGE macro Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The soc/amd/common/acpi/lpc.asl file which was included in the now removed pci0.asl file now gets included in the correct scope in the soc.asl file. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If293188fc8d0ff41b47ab84c9655333e9ebe58e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75594 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- D src/soc/amd/phoenix/acpi/pci0.asl M src/soc/amd/phoenix/acpi/soc.asl 2 files changed, 6 insertions(+), 27 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/phoenix/acpi/pci0.asl b/src/soc/amd/phoenix/acpi/pci0.asl deleted file mode 100644 index 6039a5aa..0000000 --- a/src/soc/amd/phoenix/acpi/pci0.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Update for Phoenix */ - -Device(PCI0) { - Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ - Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - - /* Operating System Capabilities Method */ - Method(_OSC, 4) { - CreateDWordField(Arg3, 0, CDW1) /* Capabilities dword 1 */ - - /* Check for proper PCI/PCIe UUID */ - If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { - /* Let OS control everything */ - Return (Arg3) - } Else { - CDW1 |= 4 /* Unrecognized UUID */ - Return (Arg3) - } - } - - /* 0:14.3 - LPC */ - #include <soc/amd/common/acpi/lpc.asl> - -} /* End PCI0 scope */ diff --git a/src/soc/amd/phoenix/acpi/soc.asl b/src/soc/amd/phoenix/acpi/soc.asl index 4df7835..ee2e9c8 100644 --- a/src/soc/amd/phoenix/acpi/soc.asl +++ b/src/soc/amd/phoenix/acpi/soc.asl @@ -2,6 +2,7 @@ /* TODO: Update for Phoenix */ +#include <soc/amd/common/acpi/pci_root.asl> #include "globalnvs.asl" Scope(\_SB) { @@ -18,7 +19,11 @@ #include "mmio.asl" - #include "pci0.asl" + ROOT_BRIDGE(PCI0) + + Scope(PCI0) { + #include <soc/amd/common/acpi/lpc.asl> + } /* End PCI0 scope */ } /* End \_SB scope */ #include <soc/amd/common/acpi/alib.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/75594?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If293188fc8d0ff41b47ab84c9655333e9ebe58e8 Gerrit-Change-Number: 75594 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/mendocino/acpi: use ROOT_BRIDGE macro
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75593?usp=email ) Change subject: soc/amd/mendocino/acpi: use ROOT_BRIDGE macro ...................................................................... soc/amd/mendocino/acpi: use ROOT_BRIDGE macro Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The soc/amd/common/acpi/lpc.asl file which was included in the now removed pci0.asl file now gets included in the correct scope in the soc.asl file. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6fc4b09f79e633208ab7536543c876c2c6129eb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75593 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- D src/soc/amd/mendocino/acpi/pci0.asl M src/soc/amd/mendocino/acpi/soc.asl 2 files changed, 6 insertions(+), 27 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/mendocino/acpi/pci0.asl b/src/soc/amd/mendocino/acpi/pci0.asl deleted file mode 100644 index 3aa2aa8..0000000 --- a/src/soc/amd/mendocino/acpi/pci0.asl +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Check if this is still correct */ - -Device(PCI0) { - Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ - Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - - /* Operating System Capabilities Method */ - Method(_OSC, 4) { - CreateDWordField(Arg3, 0, CDW1) /* Capabilities dword 1 */ - - /* Check for proper PCI/PCIe UUID */ - If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { - /* Let OS control everything */ - Return (Arg3) - } Else { - CDW1 |= 4 /* Unrecognized UUID */ - Return (Arg3) - } - } - - /* 0:14.3 - LPC */ - #include <soc/amd/common/acpi/lpc.asl> - -} /* End PCI0 scope */ diff --git a/src/soc/amd/mendocino/acpi/soc.asl b/src/soc/amd/mendocino/acpi/soc.asl index 7e9e2e8..5a73f3b 100644 --- a/src/soc/amd/mendocino/acpi/soc.asl +++ b/src/soc/amd/mendocino/acpi/soc.asl @@ -2,6 +2,7 @@ /* TODO: Check if this is still correct */ +#include <soc/amd/common/acpi/pci_root.asl> #include "globalnvs.asl" Scope(\_SB) { @@ -18,7 +19,11 @@ #include "mmio.asl" - #include "pci0.asl" + ROOT_BRIDGE(PCI0) + + Scope(PCI0) { + #include <soc/amd/common/acpi/lpc.asl> + } /* End PCI0 scope */ } /* End \_SB scope */ #include <soc/amd/common/acpi/alib.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/75593?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fc4b09f79e633208ab7536543c876c2c6129eb3 Gerrit-Change-Number: 75593 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/amd/cezanne/acpi: use ROOT_BRIDGE macro
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75592?usp=email ) Change subject: soc/amd/cezanne/acpi: use ROOT_BRIDGE macro ...................................................................... soc/amd/cezanne/acpi: use ROOT_BRIDGE macro Use the ROOT_BRIDGE macro in soc.asl to replace the pci0.asl file. The soc/amd/common/acpi/lpc.asl file which was included in the now removed pci0.asl file now gets included in the correct scope in the soc.asl file. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia8f0f1619a71f4ab2051714a9d8c7eb200845390 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75592 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- D src/soc/amd/cezanne/acpi/pci0.asl M src/soc/amd/cezanne/acpi/soc.asl 2 files changed, 6 insertions(+), 25 deletions(-) Approvals: Raul Rangel: Looks good to me, approved Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/cezanne/acpi/pci0.asl b/src/soc/amd/cezanne/acpi/pci0.asl deleted file mode 100644 index c778578..0000000 --- a/src/soc/amd/cezanne/acpi/pci0.asl +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -Device(PCI0) { - Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ - Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - - /* Operating System Capabilities Method */ - Method(_OSC, 4) { - CreateDWordField(Arg3, 0, CDW1) /* Capabilities dword 1 */ - - /* Check for proper PCI/PCIe UUID */ - If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { - /* Let OS control everything */ - Return (Arg3) - } Else { - CDW1 |= 4 /* Unrecognized UUID */ - Return (Arg3) - } - } - - /* 0:14.3 - LPC */ - #include <soc/amd/common/acpi/lpc.asl> - -} /* End PCI0 scope */ diff --git a/src/soc/amd/cezanne/acpi/soc.asl b/src/soc/amd/cezanne/acpi/soc.asl index f8f7a8a..4ab03d0 100644 --- a/src/soc/amd/cezanne/acpi/soc.asl +++ b/src/soc/amd/cezanne/acpi/soc.asl @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <soc/amd/common/acpi/pci_root.asl> #include "globalnvs.asl" Scope(\_SB) { @@ -16,7 +17,11 @@ #include "mmio.asl" - #include "pci0.asl" + ROOT_BRIDGE(PCI0) + + Scope(PCI0) { + #include <soc/amd/common/acpi/lpc.asl> + } /* End PCI0 scope */ } /* End \_SB scope */ #include <soc/amd/common/acpi/alib.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/75592?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8f0f1619a71f4ab2051714a9d8c7eb200845390 Gerrit-Change-Number: 75592 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: acpi: Add struct for SPCR table
by Kyösti Mälkki (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Arthur Heymans, Benjamin Doron, David Milosevic, Maximilian Brune, Nico Huber, Paul Menzel. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75684?usp=email ) Change subject: acpi: Add struct for SPCR table ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75684?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46d5caa0af95ec27fd49b0cf8fa704d656c89e7e Gerrit-Change-Number: 75684 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 18:43:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: arch/x86/tables.c: Drop placing ACPI and SMBIOS in lower memory
by Kyösti Mälkki (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Arthur Heymans, Benjamin Doron, Maximilian Brune, Nico Huber, Paul Menzel. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75712?usp=email ) Change subject: arch/x86/tables.c: Drop placing ACPI and SMBIOS in lower memory ...................................................................... Patch Set 1: (3 comments) File src/arch/x86/tables.c: https://review.coreboot.org/c/coreboot/+/75712/comment/284cfc7d_d1fa226a : PS1, Line 31: if (high_table_pointer) { For symmetry, do this too? https://review.coreboot.org/c/coreboot/+/75712/comment/c3ce0b57_3404519a : PS1, Line 60: if (high_table_pointer) { For symmetry, do this too? https://review.coreboot.org/c/coreboot/+/75712/comment/3eb828c8_022f49c9 : PS1, Line 83: /* Write ACPI tables to F segment and high tables area */ Second paragraph of the comment seems obsolete. -- To view, visit https://review.coreboot.org/c/coreboot/+/75712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I216e7c713d112ad1012b0beaf26196967988b951 Gerrit-Change-Number: 75712 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 07 Jun 2023 18:33:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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