coreboot-gerrit June 2023

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[S] Change in coreboot[master]: acpi/acpi.h: Remove global acpi_fill_ivrs_ioapic()
by Arthur Heymans (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75711?usp=email to look at the new patch set (#2). Change subject: acpi/acpi.h: Remove global acpi_fill_ivrs_ioapic() ...................................................................... acpi/acpi.h: Remove global acpi_fill_ivrs_ioapic() In soc/amd this function is unused so drop it and rename _acpi_fill_ivrs_ioapic(). Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ic403fd84cb9cd5805fbc6f0c5a64cefbf4b0cd81 --- M src/include/acpi/acpi.h M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/amd/common/block/acpi/ivrs.c 3 files changed, 4 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/75711/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75711?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic403fd84cb9cd5805fbc6f0c5a64cefbf4b0cd81 Gerrit-Change-Number: 75711 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/block/acpi/ivrs: Remove unused function
by Arthur Heymans (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75711?usp=email ) Change subject: soc/amd/block/acpi/ivrs: Remove unused function ...................................................................... soc/amd/block/acpi/ivrs: Remove unused function Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ic403fd84cb9cd5805fbc6f0c5a64cefbf4b0cd81 --- M src/soc/amd/common/block/acpi/ivrs.c 1 file changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/75711/1 diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 1629ff9..7f94bd8 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -33,18 +33,6 @@ return current; } -unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) -{ - uint32_t dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | - IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | - IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; - - current = _acpi_fill_ivrs_ioapic(current, VIO_APIC_VADDR, - SMBUS_DEVFN, dte_setting); - return _acpi_fill_ivrs_ioapic(current, (u8 *)GNB_IO_APIC_ADDR, - PCI_DEVFN(0, 1), 0); -} - static unsigned long ivhd_describe_hpet(unsigned long current, uint8_t hndl, uint16_t src_devid) { ivrs_ivhd_special_t *ivhd_hpet = (ivrs_ivhd_special_t *)current; -- To view, visit https://review.coreboot.org/c/coreboot/+/75711?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic403fd84cb9cd5805fbc6f0c5a64cefbf4b0cd81 Gerrit-Change-Number: 75711 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/acpi/ivrs: Use specific IOMMU resource index on all SOC
by Arthur Heymans (Code Review) 07 Jun '23

07 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75710?usp=email ) Change subject: soc/amd/acpi/ivrs: Use specific IOMMU resource index on all SOC ...................................................................... soc/amd/acpi/ivrs: Use specific IOMMU resource index on all SOC By adding all DXIO IOAPIC with the same resource index, the IVRS code can always pick that resource which simplifies the code. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I10345e2337dcb709c2c1a8e57a1b7dd9c04adb9e --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/phoenix/root_complex.c M src/soc/amd/picasso/root_complex.c 6 files changed, 10 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/75710/1 diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 6bef915..4922421 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -3,6 +3,7 @@ #include <acpi/acpigen.h> #include <amdblocks/acpi.h> #include <amdblocks/alib.h> +#include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> #include <arch/ioapic.h> @@ -142,7 +143,7 @@ mmconf_resource(dev, idx++); /* GNB IOAPIC resource */ - gnb_apic = new_resource(dev, idx++); + gnb_apic = new_resource(dev, IOMMU_IOAPIC_IDX); gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 3e58a61..1629ff9 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -206,9 +206,6 @@ /* Describe IOAPIC associated with the IOMMU */ current = _acpi_fill_ivrs_ioapic(current, (u8 *)(uintptr_t)res->base, PCI_DEVFN(0, 1) | (dev->link_list->secondary << 8), 0); - } else if (dev->link_list->secondary == 0) { - current = _acpi_fill_ivrs_ioapic(current, (u8 *)GNB_IO_APIC_ADDR, - PCI_DEVFN(0, 1), 0); } /* If the domain has secondary bus as zero then associate HPET & FCH IOAPIC */ diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index a8b54e2..4b582ae 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -5,6 +5,7 @@ #include <acpi/acpigen.h> #include <amdblocks/acpi.h> #include <amdblocks/alib.h> +#include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> #include <arch/ioapic.h> @@ -157,7 +158,7 @@ mmconf_resource(dev, idx++); /* GNB IOAPIC resource */ - gnb_apic = new_resource(dev, idx++); + gnb_apic = new_resource(dev, IOMMU_IOAPIC_IDX); gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 53a245b..7f9220e 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -5,6 +5,7 @@ #include <acpi/acpigen.h> #include <amdblocks/acpi.h> #include <amdblocks/alib.h> +#include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> #include <arch/ioapic.h> @@ -185,7 +186,7 @@ mmconf_resource(dev, idx++); /* GNB IOAPIC resource */ - gnb_apic = new_resource(dev, idx++); + gnb_apic = new_resource(dev, IOMMU_IOAPIC_IDX); gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c index 83fb047..185a88e 100644 --- a/src/soc/amd/phoenix/root_complex.c +++ b/src/soc/amd/phoenix/root_complex.c @@ -5,6 +5,7 @@ #include <acpi/acpigen.h> #include <amdblocks/acpi.h> #include <amdblocks/alib.h> +#include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> #include <arch/ioapic.h> @@ -157,7 +158,7 @@ mmconf_resource(dev, idx++); /* GNB IOAPIC resource */ - gnb_apic = new_resource(dev, idx++); + gnb_apic = new_resource(dev, IOMMU_IOAPIC_IDX); gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 5ea8b79..5d4550d 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -3,6 +3,7 @@ #include <acpi/acpigen.h> #include <amdblocks/acpi.h> #include <amdblocks/alib.h> +#include <amdblocks/data_fabric.h> #include <amdblocks/memmap.h> #include <amdblocks/ioapic.h> #include <arch/ioapic.h> @@ -140,7 +141,7 @@ mmconf_resource(dev, idx++); /* GNB IOAPIC resource */ - gnb_apic = new_resource(dev, idx++); + gnb_apic = new_resource(dev, IOMMU_IOAPIC_IDX); gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -- To view, visit https://review.coreboot.org/c/coreboot/+/75710?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10345e2337dcb709c2c1a8e57a1b7dd9c04adb9e Gerrit-Change-Number: 75710 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/jasperlake: Add per-SKU power limits
by Paul Menzel (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: ChiaLing. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75679?usp=email ) Change subject: soc/intel/jasperlake: Add per-SKU power limits ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75679/comment/5bad3da1_efdb1075 : PS1, Line 10: devicetree. Fits on the line above. https://review.coreboot.org/c/coreboot/+/75679/comment/61d72d53_14518ab8 : PS1, Line 11: Please document the source for these limits. https://review.coreboot.org/c/coreboot/+/75679/comment/f5ae2b38_a5a4bd18 : PS1, Line 13: TEST=emerge-dedede coreboot and read correct value : on DUT register Fits into 72 characters. https://review.coreboot.org/c/coreboot/+/75679/comment/b703509f_ad7d6972 : PS1, Line 15: On what board? -- To view, visit https://review.coreboot.org/c/coreboot/+/75679?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd Gerrit-Change-Number: 75679 Gerrit-PatchSet: 1 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 13:19:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/amd/block/ivrs: Generalize IVRS table generation
by Arthur Heymans (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Felix Held, Felix Singer, Fred Reitberger, Jason Glenesk, Marvin Drees, Matt DeVillier, Naresh Solanki, Raul Rangel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75451?usp=email ) Change subject: soc/amd/block/ivrs: Generalize IVRS table generation ...................................................................... Patch Set 8: -Code-Review (1 comment) File src/soc/amd/common/block/acpi/ivrs.c: https://review.coreboot.org/c/coreboot/+/75451/comment/a53dea42_62149ef5 : PS8, Line 209: else if (dev->link_list->secondary == 0) { : current = _acpi_fill_ivrs_ioapic(current, (u8 *)GNB_IO_APIC_ADDR, : PCI_DEVFN(0, 1), 0); maybe add a TODO to add this resource with this index on all AMD SOCs? -- To view, visit https://review.coreboot.org/c/coreboot/+/75451?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic471f05d6000c21081d70495b7dbd4350e68b774 Gerrit-Change-Number: 75451 Gerrit-PatchSet: 8 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 07 Jun 2023 13:18:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: security/intel/cbnt/Makefile: Fix invalid char '*'
by Paul Menzel (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Elyes Haouas. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75638?usp=email ) Change subject: security/intel/cbnt/Makefile: Fix invalid char '*' ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75638/comment/ef1c4414_5d016fcf : PS2, Line 8: Please write a small explanation for those unfamiliar with Make syntax. -- To view, visit https://review.coreboot.org/c/coreboot/+/75638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I953e06f1ff70a2b61bc5f505f7df9936b7f9b55b Gerrit-Change-Number: 75638 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 07 Jun 2023 13:15:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/amd/block/ivrs: Generalize IVRS table generation
by Arthur Heymans (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Felix Held, Felix Singer, Fred Reitberger, Jason Glenesk, Marvin Drees, Matt DeVillier, Naresh Solanki, Raul Rangel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75451?usp=email ) Change subject: soc/amd/block/ivrs: Generalize IVRS table generation ...................................................................... Patch Set 8: Code-Review+1 (1 comment) Patchset: PS8: This seems to boot on picasso. -- To view, visit https://review.coreboot.org/c/coreboot/+/75451?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic471f05d6000c21081d70495b7dbd4350e68b774 Gerrit-Change-Number: 75451 Gerrit-PatchSet: 8 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 07 Jun 2023 13:15:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in em100[master]: add target/download-RPMC/reset
by Paul Menzel (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: EvyLiu, Martin L Roth, Stefan Reinauer. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/em100/+/75675?usp=email ) Change subject: add target/download-RPMC/reset ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/em100/+/75675/comment/384b5cce_98494d59 : PS1, Line 2: Author: evyevyevy <evy.liu(a)dediprog.cocm> Please use your full name: $ git config --global user.name "Evy Liu" $ git commit --amend -s --author="Evy Liu <evy.liu(a)dediprog.com>" https://review.coreboot.org/c/em100/+/75675/comment/8c63b6ed_9aee21ad : PS1, Line 2: cocm com https://review.coreboot.org/c/em100/+/75675/comment/ea45742f_2affa936 : PS1, Line 8: Please elaborate [1]. [1]: https://cbea.ms/git-commit/ Patchset: PS1: Welcome to the project and thank you very much for your contribution. The changes are quite extensive, so it’d be great, if you wrote a commit message. -- To view, visit https://review.coreboot.org/c/em100/+/75675?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Id470fb9022e6472d90f4a9d3b26076a7518803f3 Gerrit-Change-Number: 75675 Gerrit-PatchSet: 1 Gerrit-Owner: EvyLiu <evy.liu(a)dediprog.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: EvyLiu <evy.liu(a)dediprog.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 13:14:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: WIP acpi: Add SPCR table
by Arthur Heymans (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Benjamin Doron, Lance Zhao, Nico Huber, Tim Wawrzynczak. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75685?usp=email ) Change subject: WIP acpi: Add SPCR table ...................................................................... Patch Set 3: (2 comments) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/75685/comment/a5776b0a_018f2f65 : PS3, Line 1842: /* 16550 compatible, TODO do we need others? */ > Maybe: > ``` > if (!CONFIG(CONSOLE_SERIAL)) > return; > ``` Sounds good. https://review.coreboot.org/c/coreboot/+/75685/comment/17ba0c3d_8ab3eb20 : PS3, Line 1870: /* TODO: provide callback for IRQ on non standard ports*/ > Would it be bad not to use an IRQ at all? Probably best indeed. -- To view, visit https://review.coreboot.org/c/coreboot/+/75685?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64e624c17a27b9215a8ba83bd6cbb2c0a7aa1dfc Gerrit-Change-Number: 75685 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 13:13:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: acpi: Add struct for SPCR table
by Lean Sheng Tan (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Arthur Heymans, Benjamin Doron, David Milosevic, Maximilian Brune, Nico Huber, Paul Menzel. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75684?usp=email ) Change subject: acpi: Add struct for SPCR table ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75684?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46d5caa0af95ec27fd49b0cf8fa704d656c89e7e Gerrit-Change-Number: 75684 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 13:08:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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