coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: soc/amd/phoenix: Hook up xhci ops in chipset.cb
by Paul Menzel (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Eric Lai, Fred Reitberger, Jason Glenesk, Jon Murphy, Martin L Roth, Martin Roth, Matt DeVillier. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75659?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/amd/phoenix: Hook up xhci ops in chipset.cb ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75659/comment/c5f4f872_4fab609f : PS5, Line 9: Add hook up xhci ops for Phoenix xHCI device. Add the motivation? Maybe: … so they are properly configured. https://review.coreboot.org/c/coreboot/+/75659/comment/f4ee1c67_09393025 : PS5, Line 9: Add hook up Hook up -- To view, visit https://review.coreboot.org/c/coreboot/+/75659?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib59874948725966b04b54def3f6de463afeda709 Gerrit-Change-Number: 75659 Gerrit-PatchSet: 5 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 11:27:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: WIP acpi: Add SPCR table
by Arthur Heymans (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Lance Zhao, Tim Wawrzynczak. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75685?usp=email ) Change subject: WIP acpi: Add SPCR table ...................................................................... WIP acpi: Add SPCR table Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I64e624c17a27b9215a8ba83bd6cbb2c0a7aa1dfc --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 73 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/75685/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 4fdbd6f..5cd8e54 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1822,6 +1822,60 @@ return coreboot_rsdp; } +static void acpi_create_spcr(acpi_spcr_t *spcr) +{ + acpi_header_t *header = &(spcr->header); + struct lb_serial serial; + if (fill_lb_serial(&serial) != CB_SUCCESS) + return; + + memset((void *)spcr, 0, sizeof(acpi_spcr_t)); + + memcpy(header->signature, "SPCR", 4); + header->length = sizeof(acpi_spcr_t); + header->revision = get_acpi_table_revision(SPCR); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = asl_revision; + + /* 16550 compatible, TODO do we need others? */ + spcr->interface_type = 0; + assert(serial.type == LB_SERIAL_TYPE_IO_MAPPED + || serial.type == LB_SERIAL_TYPE_MEMORY_MAPPED); + spcr->base_address.space_id = serial.type == LB_SERIAL_TYPE_IO_MAPPED ? ACPI_ADDRESS_SPACE_IO : ACPI_ADDRESS_SPACE_MEMORY; + spcr->base_address.bit_width = serial.regwidth * 8; + spcr->base_address.bit_offset = 0; + spcr->base_address.access_size = serial.regwidth; + spcr->base_address.addrl = serial.baseaddr; + spcr->base_address.addrh = 0; + if (ENV_X86) + spcr->interrupt_type = IO_APIC_COMPATIBLE_INTERRUPT; + if (serial.type == LB_SERIAL_TYPE_IO_MAPPED) + spcr->interrupt_type |= PC_AT_COMPATIBLE_INTERRUPT; + /* TODO: provide callback for IRQ on non standard ports*/ + if (serial.type == LB_SERIAL_TYPE_IO_MAPPED) { + switch (serial.baseaddr) { + case 0x3f8: + spcr->irq = 4; + spcr->global_system_interrupt = 4; + break; + case 0x2f8: + spcr->irq = 3; + spcr->global_system_interrupt = 3; + break; + } + } + spcr->configured_baudrate = 0; /* Have the OS use whatever is currently set */ + spcr->parity = 0; + spcr->stop_bits = 1; + spcr->flow_control = 0; + spcr->terminal_type = 2; /* 2 = VT-UTF8 */ + spcr->language = 0; + spcr->pci_did = 0xffff; + spcr->pci_vid = 0xffff; +} + unsigned long write_acpi_tables(unsigned long start) { unsigned long current; @@ -1839,6 +1893,7 @@ acpi_madt_t *madt; acpi_lpit_t *lpit; acpi_bert_t *bert; + acpi_spcr_t *spcr; struct device *dev; unsigned long fw; size_t slic_size, dsdt_size; @@ -2090,6 +2145,15 @@ } } + printk(BIOS_DEBUG, "ACPI: * SPCR\n"); + spcr = (acpi_spcr_t *)current; + acpi_create_spcr(spcr); + if (spcr->header.length > sizeof(acpi_spcr_t)) { + current += spcr->header.length; + acpi_add_table(rsdp, spcr); + } + current = acpi_align_current(current); + printk(BIOS_DEBUG, "current = %lx\n", current); for (dev = all_devices; dev; dev = dev->next) { @@ -2251,6 +2315,8 @@ return 1; case LPIT: /* ACPI 5.1 up to 6.3: 0 */ return 0; + case SPCR: + return 4; default: return -1; } diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 548b4c3..3676a23 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -75,6 +75,7 @@ /* Tables defined by ACPI and used by coreboot */ BERT, CEDT, DBG2, DMAR, DSDT, EINJ, FACS, FADT, HEST, HMAT, HPET, IVRS, MADT, MCFG, RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT, LPIT, + SPCR, /* Additional proprietary tables used by coreboot */ VFCT, NHLT, SPMI, CRAT }; @@ -1328,6 +1329,12 @@ } __packed acpi_spcr_t; _Static_assert(sizeof(acpi_spcr_t) == 88, "acpi_spcr_t must have an 88 byte size\n"); +#define PC_AT_COMPATIBLE_INTERRUPT (1 << 0) +#define IO_APIC_COMPATIBLE_INTERRUPT (1 << 1) +#define IO_SAPIC_COMPATIBLE_INTERRUPT (1 << 2) +#define ARMH_GIC_COMPATIBLE_INTERRUPT (1 << 3) +#define RISCV_PLIC_COMPATIBLE_INTERRUPT (1 << 4) + uintptr_t get_coreboot_rsdp(void); void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions); -- To view, visit https://review.coreboot.org/c/coreboot/+/75685?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64e624c17a27b9215a8ba83bd6cbb2c0a7aa1dfc Gerrit-Change-Number: 75685 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: acpi: Add struct for SPCR table
by Arthur Heymans (Code Review) 07 Jun '23

07 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75684?usp=email ) Change subject: acpi: Add struct for SPCR table ...................................................................... acpi: Add struct for SPCR table Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I46d5caa0af95ec27fd49b0cf8fa704d656c89e7e --- M src/include/acpi/acpi.h 1 file changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/75684/1 diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 78a6005..548b4c3 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1298,6 +1298,36 @@ acpi_einj_action_table_t action_table[ACTION_COUNT]; } __packed acpi_einj_t; +/* SPCR (Serial Port Console Redirection Table) */ +typedef struct acpi_spcr { + acpi_header_t header; + uint8_t interface_type; + uint8_t reserved[3]; + acpi_addr_t base_address; + uint8_t interrupt_type; + uint8_t irq; + uint32_t global_system_interrupt; + uint8_t configured_baudrate; + uint8_t parity; + uint8_t stop_bits; + uint8_t flow_control; + uint8_t terminal_type; + uint8_t language; + uint16_t pci_did; + uint16_t pci_vid; + uint8_t pci_bus; + uint8_t pci_dev; + uint8_t pci_fun; + uint32_t pci_flags; + uint8_t pci_segment; + uint32_t uart_clock; + uint32_t precise_baud_rate; + uint16_t namespace_string_length; + uint16_t namespace_string_offset; + char namespacestring[]; +} __packed acpi_spcr_t; +_Static_assert(sizeof(acpi_spcr_t) == 88, "acpi_spcr_t must have an 88 byte size\n"); + uintptr_t get_coreboot_rsdp(void); void acpi_create_einj(acpi_einj_t *einj, uintptr_t addr, u8 actions); -- To view, visit https://review.coreboot.org/c/coreboot/+/75684?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46d5caa0af95ec27fd49b0cf8fa704d656c89e7e Gerrit-Change-Number: 75684 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/amd/phoenix: Hook up xhci ops in chipset.cb
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Eric Lai, Fred Reitberger, Jason Glenesk, Jon Murphy, Martin L Roth, Martin Roth, Matt DeVillier, Paul Menzel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75659?usp=email ) Change subject: soc/amd/phoenix: Hook up xhci ops in chipset.cb ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Patchset: PS3: > Working fine. I'll update the patch. You can help clean up the rest SoC. as far as i know, this should be done for all 4 xhci controller. i don't know yet if the two xhci controllers for the usb4 ports will require some special handling, but we'll see that when enabling the full usb4 support. if the ports behave correctly with this patch applied, it should be good for now. i can work on moving the other socs over to using this code. might take some time for me to get around to do that though -- To view, visit https://review.coreboot.org/c/coreboot/+/75659?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib59874948725966b04b54def3f6de463afeda709 Gerrit-Change-Number: 75659 Gerrit-PatchSet: 5 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 10:37:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: vendorcode/intel: Add edk2-stable202302 support
by Nico Huber (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Felix Singer, Kapil Porwal, Meera Ravindranath, Ronak Kanabar, Sridhar Siricilla, Subrata Banik, Tarun Tuli. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75663?usp=email ) Change subject: vendorcode/intel: Add edk2-stable202302 support ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > > Yeah I see. I just don't like copy&paste. […] EDK2 submodules (we would need one per needed version) would create a huge overhead to just build a board with FSP (which are a lot). There used to be a tool to convert FSP headers to standard C, IIRC. This way we could avoid edk2 headers altogether. It would create additional work in other situations, though. For instance, we'd have to re-sync header files with every FSP submodule update (could be semi-automated though). I guess the only way to figure out if it would be less noisy in the long run is to try :) -- To view, visit https://review.coreboot.org/c/coreboot/+/75663?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d4deab0bd1d2c6df28e067894875b80413cd905 Gerrit-Change-Number: 75663 Gerrit-PatchSet: 3 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 10:29:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: acpi: Add a debug option to print out tables in ACPICA compatible hex
by Nico Huber (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Arthur Heymans, Benjamin Doron, Kyösti Mälkki, Lance Zhao, Lean Sheng Tan, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75677?usp=email ) Change subject: acpi: Add a debug option to print out tables in ACPICA compatible hex ...................................................................... Patch Set 3: Code-Review+1 (2 comments) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/75677/comment/72f8e7d4_7de4a959 : PS2, Line 1854: printk(BIOS_SPEW, " %04lX:", i); > There is build error here from Jenkins: […] Done File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/75677/comment/8583bd03_09cdbc76 : PS3, Line 1874: {} Maybe make this `[sizeof(header->signature) + 1] = { 0, }` to make it clear that it's about 0 termination. (random alternative: `%.4s` should do as well, w/o termination) Also, a blank line after the declarations would make it look less bulky. -- To view, visit https://review.coreboot.org/c/coreboot/+/75677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc Gerrit-Change-Number: 75677 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 10:20:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/nissa/var/uldren: Modify WWAN power sequence
by Dtrain Hsu (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Shou-Chieh Hsu, Tarun Tuli. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75690?usp=email ) Change subject: mb/google/nissa/var/uldren: Modify WWAN power sequence ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75690/comment/4e8a28d8_0523a4d6 : PS1, Line 9: WWAN power sequence > IIUC, the modification is for warm reboot case. […] Thanks for review. Update commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/75690?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If59630dbd10e971c91e01f33a657c01d857bc0b9 Gerrit-Change-Number: 75690 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 10:13:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Derek Huang <derekhuang(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/nissa/var/uldren: Modify WWAN power sequence
by Derek Huang (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Dtrain Hsu, Shou-Chieh Hsu, Tarun Tuli. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75690?usp=email ) Change subject: mb/google/nissa/var/uldren: Modify WWAN power sequence ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75690?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If59630dbd10e971c91e01f33a657c01d857bc0b9 Gerrit-Change-Number: 75690 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 09:57:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/nissa/var/uldren: Modify WWAN power sequence
by Dtrain Hsu (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Dtrain Hsu, Shou-Chieh Hsu, Tarun Tuli. Hello Derek Huang, Shou-Chieh Hsu, Tarun Tuli, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75690?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/uldren: Modify WWAN power sequence ...................................................................... mb/google/nissa/var/uldren: Modify WWAN power sequence Follow spec[1] to modify WWAN power sequence. The WWAN power sequence of warm reset is fail. The correct sequence is WWAN_EN should keep high when doing warm reset. Set GPP_D6 to PWROK which is not to do PAD reset when warm reset. [1]: [JDB10] FC ADL-N_WWAN sequence_FM101-GL SDX12 Power Timing Review_V1.6_20230602.xlsx BUG=b:285065375 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot chromeos-bootimage 2. power sequence meets spec. Change-Id: If59630dbd10e971c91e01f33a657c01d857bc0b9 Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/uldren/gpio.c 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/75690/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75690?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If59630dbd10e971c91e01f33a657c01d857bc0b9 Gerrit-Change-Number: 75690 Gerrit-PatchSet: 2 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: soc/amd/block/ivrs: Generalize IVRS table generation
by Arthur Heymans (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Felix Held, Felix Singer, Fred Reitberger, Jason Glenesk, Marvin Drees, Matt DeVillier, Naresh Solanki, Raul Rangel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75451?usp=email ) Change subject: soc/amd/block/ivrs: Generalize IVRS table generation ...................................................................... Patch Set 7: (1 comment) File src/soc/amd/common/block/acpi/ivrs.c: https://review.coreboot.org/c/coreboot/+/75451/comment/a3fe6ff4_70f9c2ac : PS7, Line 262: /* Find EMMC */ : if (!nb_dev->bus) : dev = pcidev_path_behind(nb_dev->bus, PCI_DEVFN(0x13, 1)); > Thanks for the input. > In that case should this limited to 1st IOMMU domain? > i.e., > if (dev->link_list->secondary == 0) { > /* Describe EMMC */ > current = ivhd_describe_f0_device(current, PCI_DEVFN(0x13, 1), > IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | > IVHD_DTE_SYS_MGT_TRANS | IVHD_DTE_NMI_PASS | > IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS); > } Right. EMMC is on FCH so using the first IOMMU domain is a good proxy I think. -- To view, visit https://review.coreboot.org/c/coreboot/+/75451?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic471f05d6000c21081d70495b7dbd4350e68b774 Gerrit-Change-Number: 75451 Gerrit-PatchSet: 7 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 07 Jun 2023 09:36:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-MessageType: comment

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