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[M] Change in coreboot[master]: mb/google/dedede/var/dibbi: Update power limits
by ChiaLing (Code Review) 07 Jun '23

07 Jun '23

ChiaLing has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75681?usp=email ) Change subject: mb/google/dedede/var/dibbi: Update power limits ...................................................................... mb/google/dedede/var/dibbi: Update power limits Update Dibbi power limit in ramstage BUG=b:281479111 TEST=emerge-dedede coreboot and check psys and PLx on DUT Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com> Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6 --- M src/mainboard/google/dedede/variants/dibbi/Makefile.inc A src/mainboard/google/dedede/variants/dibbi/ramstage.c 2 files changed, 73 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/75681/1 diff --git a/src/mainboard/google/dedede/variants/dibbi/Makefile.inc b/src/mainboard/google/dedede/variants/dibbi/Makefile.inc index eb2c9bc..66f0263 100644 --- a/src/mainboard/google/dedede/variants/dibbi/Makefile.inc +++ b/src/mainboard/google/dedede/variants/dibbi/Makefile.inc @@ -1,3 +1,4 @@ ## SPDX-License-Identifier: GPL-2.0-or-later ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/dedede/variants/dibbi/ramstage.c b/src/mainboard/google/dedede/variants/dibbi/ramstage.c new file mode 100644 index 0000000..6953076 --- /dev/null +++ b/src/mainboard/google/dedede/variants/dibbi/ramstage.c @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <drivers/intel/dptf/chip.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/power_limit.h> + +const struct cpu_power_limits pwr_limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + // N4500 + { PCI_DEVICE_ID_INTEL_JSL_ID_1, 6, 6000, 6000, 20000, 20000, 60000 }, + // N6000 + { PCI_DEVICE_ID_INTEL_JSL_ID_2, 6, 6000, 6000, 20000, 20000, 60000 }, + // N5100 + { PCI_DEVICE_ID_INTEL_JSL_ID_3, 6, 6000, 6000, 20000, 20000, 60000 }, + // N4505 + { PCI_DEVICE_ID_INTEL_JSL_ID_4, 10, 10000, 10000, 25000, 25000, 75000 }, + // N5105 + { PCI_DEVICE_ID_INTEL_JSL_ID_5, 10, 10000, 10000, 25000, 25000, 75000 }, +}; + +const struct system_power_limits sys_limits[] = { + /* SKU_ID, TDP (Watts), psys_pl1 (Watts), psys_pl2 (Watts) */ + { PCI_DEVICE_ID_INTEL_JSL_ID_1, 6, 31, 65 }, + { PCI_DEVICE_ID_INTEL_JSL_ID_2, 6, 31, 65 }, + { PCI_DEVICE_ID_INTEL_JSL_ID_3, 6, 31, 65 }, + { PCI_DEVICE_ID_INTEL_JSL_ID_4, 10, 35, 65 }, + { PCI_DEVICE_ID_INTEL_JSL_ID_5, 10, 35, 65 }, +}; + +/* + * Psys_pmax considerations. + * + * Given the hardware design in dibbi, the serial shunt resistor is 0.01ohm. + * The full scale of hardware PSYS signal 1.6v maps to system current 6.009A + * instead of real system power. The equation is shown below: + * PSYS = 1.6v ~= (0.01ohm x 6.009A) x 50 (INA213, gain 50V/V) x R631/(R631 + R638) + * R631/(R631 + R638) = 0.5325 = 36K / (36K + 31.6K) + * + * The Psys_pmax is a SW setting which tells IMVP9.1 the mapping b/w system input + * current and the actual system power. Since there is no voltage information + * from PSYS, different voltage input would map to different Psys_pmax settings: + * For Type-C 15V, the Psys_pmax should be 15v x 6.009A = 90.135W + * For Type-C 20V, the Psys_pmax should be 20v x 6.009A = 120.18W + * For a barrel jack, the Psys_pmax should be 19v x 6.009A = 114.171W + * + * Imagine that there is a type-c 100W (20V/5A) connected to DUT w/ full loading, + * and the Psys_pmax setting is 120W. Then IMVP9.1 can calculate the current system + * power = 120W * 5A / 6.009A = 100W, which is the actual system power. + */ +const struct psys_config psys_config = { + .efficiency = 97, + .psys_imax_ma = 6009, + .bj_volts_mv = 19000 +}; + +static void update_power_limits(void) +{ + size_t total_entries = ARRAY_SIZE(pwr_limits); + variant_update_psys_power_limits(pwr_limits, sys_limits, total_entries, &psys_config); + variant_update_power_limits(pwr_limits, total_entries); +} + +void variant_devtree_update(void) +{ + update_power_limits(); +} \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/75681?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieaff856b762b546f3e99acb7ba2ce15791193da6 Gerrit-Change-Number: 75681 Gerrit-PatchSet: 1 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/dedede: Support variant specific power limits
by ChiaLing (Code Review) 07 Jun '23

07 Jun '23

ChiaLing has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75680?usp=email ) Change subject: mb/google/dedede: Support variant specific power limits ...................................................................... mb/google/dedede: Support variant specific power limits With newer dedede design, it's required to config corresponding psyspmax, psyspl1, psyspl2, pl1 and pl2 by different kind of adapter. BUG=b:281479111 TEST=emerge-dedede coreboot and check correct register value on DUT Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com> Change-Id: I583c930379233322c41027805369f81d02000ee7 --- M src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h A src/mainboard/google/dedede/variants/baseboard/ramstage.c 2 files changed, 211 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/75680/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h index edb2b07..cc262f9 100644 --- a/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/dedede/variants/baseboard/include/baseboard/variants.h @@ -48,6 +48,53 @@ /* Modify devictree settings during ramstage. */ void variant_devtree_update(void); +struct cpu_power_limits { + uint16_t mchid; + u8 cpu_tdp; + unsigned int pl1_min_power; + unsigned int pl1_max_power; + unsigned int pl2_min_power; + unsigned int pl2_max_power; + unsigned int pl4_power; +}; + +struct system_power_limits { + uint16_t mchid; + u8 cpu_tdp; + /* PsysPL1 in Watts */ + unsigned int psys_pl1_power; + /* PsysPL2 in Watts */ + unsigned int psys_pl2_power; +}; + +struct psys_config { + /* + * The efficiency of type-c chargers + * For example, 'efficiency = 97' means setting 97% of max power to account for + * cable loss and FET Rdson loss in the path from the source. + */ + unsigned int efficiency; + + /* The maximum current maps to the Psys signal */ + unsigned int psys_imax_ma; + + /* The voltage of barrel jack */ + unsigned int bj_volts_mv; +}; + +/* Modify Power Limit devictree settings during ramstage */ +void variant_update_power_limits(const struct cpu_power_limits *limits, + size_t num_entries); + +/* + * Modify Power Limit and PsysPL devictree settings during ramstage. + * Note, this function must be called in front of calling variant_update_power_limits. + */ +void variant_update_psys_power_limits(const struct cpu_power_limits *limits, + const struct system_power_limits *sys_limits, + size_t num_entries, + const struct psys_config *config); + /* Modify LTE devictree settings during ramstage. */ void update_lte_device(struct acpi_gpio *lte_reset_gpio, struct acpi_gpio *lte_enable_gpio); diff --git a/src/mainboard/google/dedede/variants/baseboard/ramstage.c b/src/mainboard/google/dedede/variants/baseboard/ramstage.c new file mode 100644 index 0000000..51dbddc --- /dev/null +++ b/src/mainboard/google/dedede/variants/baseboard/ramstage.c @@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpi_device.h> +#include <baseboard/variants.h> +#include <console/console.h> +#include <drivers/usb/acpi/chip.h> +#include <fw_config.h> +#include <gpio.h> +#include <soc/pci_devs.h> +#include <ec/google/chromeec/ec.h> +#include <device/pci_ops.h> +#include <intelblocks/power_limit.h> +#include <chip.h> +#include <drivers/intel/dptf/chip.h> +#include <soc/pci_devs.h> + +#define LTE_USB_PORT_ID 3 +#define LTE_USB_PORT_TYPE 2 + +#define SET_PSYSPL2(e, w) ((e) * (w) / 100) + +static bool get_sku_index(const struct cpu_power_limits *limits, size_t num_entries, + size_t *intel_idx, size_t *dedede_idx) +{ + uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + u8 tdp = get_cpu_tdp(); + size_t i = 0; + + for (i = 0; i < ARRAY_SIZE(cpuid_to_jsl); i++) { + if (mchid == cpuid_to_jsl[i].pci_did && tdp == cpuid_to_jsl[i].cpu_tdp) { + *intel_idx = cpuid_to_jsl[i].limits; + break; + } + } + + if (i == ARRAY_SIZE(cpuid_to_jsl)) { + printk(BIOS_ERR, "Cannot find correct intel sku index.\n"); + return false; + } + + for (i = 0; i < num_entries; i++) { + if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) { + *dedede_idx = i; + break; + } + } + + if (i == num_entries) { + printk(BIOS_ERR, "Cannot find correct dedede sku index.\n"); + return false; + } + + return true; +} + +void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries) +{ + size_t intel_idx, dedede_idx; + struct drivers_intel_dptf_config *config; + struct dptf_power_limits *settings; + config_t *conf; + struct soc_power_limits_config *soc_config; + + if (!num_entries) + return; + + const struct device *dev = pcidev_path_on_root(SA_DEVFN_DPTF); + if(!dev || !dev->chip_info) + return; + + if (!get_sku_index(limits, num_entries, &intel_idx, &dedede_idx)) + return; + + config = dev->chip_info; + settings = &config->controls.power_limits; + conf = config_of_soc(); + soc_config = &conf->power_limits_config[intel_idx]; + settings->pl1.min_power = limits[dedede_idx].pl1_min_power; + settings->pl1.max_power = limits[dedede_idx].pl1_max_power; + settings->pl2.min_power = limits[dedede_idx].pl2_min_power; + settings->pl2.max_power = limits[dedede_idx].pl2_max_power; + + if (soc_config->tdp_pl2_override != 0) { + settings->pl2.max_power = soc_config->tdp_pl2_override * 1000; + settings->pl2.min_power = settings->pl2.max_power; + } + + if (soc_config->tdp_pl4 == 0) + soc_config->tdp_pl4 = DIV_ROUND_UP(limits[dedede_idx].pl4_power, + MILLIWATTS_TO_WATTS); + + printk(BIOS_INFO, "Overriding power limits PL1(mW) (%u, %u) PL2(mW) (%u, %u) PL4 (%u)\n", + settings->pl1.min_power, + settings->pl1.max_power, + settings->pl2.min_power, + settings->pl2.max_power, + soc_config->tdp_pl4); +} + +void variant_update_psys_power_limits(const struct cpu_power_limits *limits, + const struct system_power_limits *sys_limits, + size_t num_entries, + const struct psys_config *config_psys) +{ + struct soc_power_limits_config *soc_config; + size_t intel_idx, dedede_idx; + u16 volts_mv, current_ma; + enum usb_chg_type type; + u32 psyspl2, pl2; + u32 pl2_default; + config_t *conf; + u32 watts; + int rv; + + if (!num_entries) + return; + + const struct device *dev = pcidev_path_on_root(SA_DEVFN_DPTF); + if(!dev || !dev->chip_info) + return; + + if (!get_sku_index(limits, num_entries, &intel_idx, &dedede_idx)) + return; + + conf = config_of_soc(); + soc_config = &conf->power_limits_config[intel_idx]; + soc_config->tdp_pl4 = 0; + + pl2_default = DIV_ROUND_UP(limits[dedede_idx].pl2_max_power, MILLIWATTS_TO_WATTS); + rv = google_chromeec_get_usb_pd_power_info(&type, &current_ma, &volts_mv); + + if (rv == 0 && type == USB_CHG_TYPE_PD) { + /* Detected USB-PD. Base on max value of adapter */ + watts = ((u32)current_ma * volts_mv) / 1000000; + + /* set psyspl2 to 97% of adapter rating */ + psyspl2 = SET_PSYSPL2(config_psys->efficiency, watts); + + /* Limit PL2 if the adapter is with lower capability */ + pl2 = (psyspl2 > pl2_default) ? pl2_default : psyspl2; + + } else { + /* Input type is barrel jack */ + volts_mv = config_psys->bj_volts_mv; + psyspl2 = sys_limits[dedede_idx].psys_pl2_power; + pl2 = pl2_default; + } + + /* voltage unit is milliVolts and current is in milliAmps */ + soc_config->psys_pmax = (u16)(((u32)config_psys->psys_imax_ma * volts_mv) / 1000000); + conf->PsysPmax = soc_config->psys_pmax; + + soc_config->tdp_psyspl1 = sys_limits[dedede_idx].psys_pl1_power; + soc_config->tdp_pl2_override = pl2; + soc_config->tdp_psyspl2 = psyspl2; + soc_config->tdp_pl4 = psyspl2 - soc_config->min_rop; + + printk(BIOS_INFO, "Overriding PL2 (%u) PL4 (%u) PsysPL1 (%u) PsysPL2 (%u) Psys_Pmax (%u)\n", + soc_config->tdp_pl2_override, + soc_config->tdp_pl4, + soc_config->tdp_psyspl1, + soc_config->tdp_psyspl2, + soc_config->psys_pmax); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/75680?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I583c930379233322c41027805369f81d02000ee7 Gerrit-Change-Number: 75680 Gerrit-PatchSet: 1 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/jasperlake: Add per-SKU power limits
by ChiaLing (Code Review) 07 Jun '23

07 Jun '23

ChiaLing has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75679?usp=email ) Change subject: soc/intel/jasperlake: Add per-SKU power limits ...................................................................... soc/intel/jasperlake: Add per-SKU power limits Add JSL SKUs ID and add PLx override in project devicetree. BUG=b:281479111 TEST=emerge-dedede coreboot and read correct value on DUT register Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com> Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/dedede/variants/blipper/overridetree.cb M src/mainboard/google/dedede/variants/drawcia/overridetree.cb M src/mainboard/google/dedede/variants/kracko/overridetree.cb M src/mainboard/google/dedede/variants/lantis/overridetree.cb M src/mainboard/google/dedede/variants/madoo/overridetree.cb M src/mainboard/google/dedede/variants/magolor/overridetree.cb M src/mainboard/google/dedede/variants/metaknight/overridetree.cb M src/mainboard/google/dedede/variants/sasukette/overridetree.cb M src/mainboard/google/dedede/variants/shotzo/overridetree.cb M src/mainboard/google/dedede/variants/storo/overridetree.cb M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/systemagent.c 13 files changed, 164 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/75679/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 30a971c..b9712e8 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -166,9 +166,40 @@ # Enable DPTF register "dptf_enable" = "1" - register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + .tdp_pl4 = 60, + .min_rop = 5, + }" + + register "power_limits_config[JSL_N6000_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + .tdp_pl4 = 60, + .min_rop = 5, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 20, + .tdp_pl4 = 60, + .min_rop = 5, + }" + + register "power_limits_config[JSL_N4505_10W_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 25, + .tdp_pl4 = 75, + .min_rop = 5, + }" + + register "power_limits_config[JSL_N5105_10W_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 25, + .tdp_pl4 = 75, + .min_rop = 5, }" register "tcc_offset" = "10" # TCC of 90C diff --git a/src/mainboard/google/dedede/variants/blipper/overridetree.cb b/src/mainboard/google/dedede/variants/blipper/overridetree.cb index 518b962..a507dd1 100644 --- a/src/mainboard/google/dedede/variants/blipper/overridetree.cb +++ b/src/mainboard/google/dedede/variants/blipper/overridetree.cb @@ -59,11 +59,6 @@ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" - register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, - }" - register "tcc_offset" = "10" # TCC of 95C # Enable Acoustic noise mitigation and set slew rate to 1/8 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 2eb9d81..e90d97e 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -64,11 +64,6 @@ }, }" - register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, - }" - register "tcc_offset" = "20" # TCC of 85C # Enable Acoustic noise mitigation and set slew rate to 1/4 diff --git a/src/mainboard/google/dedede/variants/kracko/overridetree.cb b/src/mainboard/google/dedede/variants/kracko/overridetree.cb index 1ce3a8f..5e39c88 100644 --- a/src/mainboard/google/dedede/variants/kracko/overridetree.cb +++ b/src/mainboard/google/dedede/variants/kracko/overridetree.cb @@ -65,11 +65,6 @@ }, }" - register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, - }" - register "tcc_offset" = "20" # TCC of 85C device domain 0 on diff --git a/src/mainboard/google/dedede/variants/lantis/overridetree.cb b/src/mainboard/google/dedede/variants/lantis/overridetree.cb index b67bd97..0908589 100644 --- a/src/mainboard/google/dedede/variants/lantis/overridetree.cb +++ b/src/mainboard/google/dedede/variants/lantis/overridetree.cb @@ -72,9 +72,20 @@ }, }" - register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 15, + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 15, + }" + + register "power_limits_config[JSL_N6000_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 15, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 15, }" # Enable Acoustic noise mitigation and set slew rate to 1/4 diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb index 2260652..437c60a 100644 --- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb @@ -54,11 +54,6 @@ }, }" - register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, - }" - register "tcc_offset" = "10" # TCC of 95C # Enable Acoustic noise mitigation and set slew rate to 1/8 diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index bb5bf244..2d80eb4 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -95,9 +95,20 @@ }, }" - register "power_limits_config" = "{ - .tdp_pl1_override = 7, - .tdp_pl2_override = 12, + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 12, + }" + + register "power_limits_config[JSL_N6000_6W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 12, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 12, }" register "tcc_offset" = "15" # TCC of 90C diff --git a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb index 75618f4..06102a1 100644 --- a/src/mainboard/google/dedede/variants/metaknight/overridetree.cb +++ b/src/mainboard/google/dedede/variants/metaknight/overridetree.cb @@ -64,9 +64,20 @@ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, }" - register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 12, + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 12, + }" + + register "power_limits_config[JSL_N6000_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 12, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ + .tdp_pl1_override = 6, + .tdp_pl2_override = 12, }" device domain 0 on diff --git a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb index 43a68db..5e4de2a 100644 --- a/src/mainboard/google/dedede/variants/sasukette/overridetree.cb +++ b/src/mainboard/google/dedede/variants/sasukette/overridetree.cb @@ -87,11 +87,6 @@ .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Camera - register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, - }" - register "tcc_offset" = "10" # TCC of 95C register "xhci_lfps_sampling_offtime_ms" = "0" diff --git a/src/mainboard/google/dedede/variants/shotzo/overridetree.cb b/src/mainboard/google/dedede/variants/shotzo/overridetree.cb index b454e3d..b43cdaa 100644 --- a/src/mainboard/google/dedede/variants/shotzo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/shotzo/overridetree.cb @@ -40,9 +40,21 @@ register "disable_external_bypass_vr" = "1" # Does not support external vnn power rail - register "power_limits_config" = "{ - .tdp_pl1_override = 7, - .tdp_pl2_override = 25, + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 25, + }" + + register "power_limits_config[JSL_N6000_6W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 25, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 25, + }" register "tcc_offset" = "5" # TCC of 100C diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb index 3b1f007..4b4c88f 100644 --- a/src/mainboard/google/dedede/variants/storo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb @@ -84,9 +84,20 @@ [PchSerialIoIndexI2C5] = PchSerialIoPci, }" - register "power_limits_config" = "{ - .tdp_pl1_override = 7, - .tdp_pl2_override = 20, + # Power limit config + register "power_limits_config[JSL_N4500_6W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 20, + }" + + register "power_limits_config[JSL_N6000_6W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 20, + }" + + register "power_limits_config[JSL_N5100_6W_CORE]" = "{ + .tdp_pl1_override = 7, + .tdp_pl2_override = 20, }" register "tcc_offset" = "10" # TCC of 95C diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index e6b8f680..d5944a3 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -3,6 +3,7 @@ #ifndef _SOC_CHIP_H_ #define _SOC_CHIP_H_ +#include <device/pci_ids.h> #include <drivers/i2c/designware/dw_i2c.h> #include <gpio.h> #include <drivers/intel/gma/gma.h> @@ -23,13 +24,42 @@ #define MAX_HD_AUDIO_SNDW_LINKS 4 #define MAX_HD_AUDIO_SSP_LINKS 6 +/* Types of different SKUs */ +enum soc_intel_jasperlake_power_limits { + JSL_N4500_6W_CORE, + JSL_N6000_6W_CORE, + JSL_N5100_6W_CORE, + JSL_N4505_10W_CORE, + JSL_N5105_10W_CORE, + JSL_POWER_LIMITS_COUNT +}; + +/* TDP values for different SKUs */ +enum soc_intel_jasperlake_cpu_tdps { + TDP_6W = 6, + TDP_10W = 10 +}; + +/* Mapping of different SKUs based on CPU ID and TDP values */ +static const struct { + unsigned int pci_did; + enum soc_intel_jasperlake_power_limits limits; + enum soc_intel_jasperlake_cpu_tdps cpu_tdp; +} cpuid_to_jsl[] = { + { PCI_DEVICE_ID_INTEL_JSL_ID_1, JSL_N4500_6W_CORE, TDP_6W }, + { PCI_DEVICE_ID_INTEL_JSL_ID_2, JSL_N6000_6W_CORE, TDP_6W }, + { PCI_DEVICE_ID_INTEL_JSL_ID_3, JSL_N5100_6W_CORE, TDP_6W }, + { PCI_DEVICE_ID_INTEL_JSL_ID_4, JSL_N4505_10W_CORE, TDP_10W }, + { PCI_DEVICE_ID_INTEL_JSL_ID_5, JSL_N5105_10W_CORE, TDP_10W }, +}; + struct soc_intel_jasperlake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; /* Common struct containing power limits configuration information */ - struct soc_power_limits_config power_limits_config; + struct soc_power_limits_config power_limits_config[JSL_POWER_LIMITS_COUNT]; /* Gpio group routed to each dword of the GPE0 block. Values are * of the form PMC_GPP_[A:U] or GPD. */ diff --git a/src/soc/intel/jasperlake/systemagent.c b/src/soc/intel/jasperlake/systemagent.c index fd04be5..a12c54c 100644 --- a/src/soc/intel/jasperlake/systemagent.c +++ b/src/soc/intel/jasperlake/systemagent.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <chip.h> +#include <console/console.h> #include <device/device.h> #include <delay.h> #include <device/pci.h> @@ -48,6 +50,9 @@ { struct soc_power_limits_config *soc_config; config_t *config; + uint16_t sa_pci_id; + u8 tdp; + size_t i; /* Enable Power Aware Interrupt Routing */ enable_power_aware_intr(); @@ -57,6 +62,27 @@ mdelay(1); config = config_of_soc(); - soc_config = &config->power_limits_config; - set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + + /* Get System Agent PCI ID */ + sa_pci_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xFFFF; + + tdp = get_cpu_tdp(); + + /* Choose power limits configuration based on the CPU SA PCI ID and + * CPU TDP value. */ + for (i = 0; i < ARRAY_SIZE(cpuid_to_jsl); i++) { + if (sa_pci_id == cpuid_to_jsl[i].pci_did && + tdp == cpuid_to_jsl[i].cpu_tdp) { + soc_config = &config->power_limits_config[cpuid_to_jsl[i].limits]; + set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + break; + } + } + + if (i == ARRAY_SIZE(cpuid_to_jsl)) { + printk(BIOS_ERR, "unknown SA ID: 0x%4x, can't find its TDP." + " Skipped power limits configuration.\n", + sa_pci_id); + return; + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/75679?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd Gerrit-Change-Number: 75679 Gerrit-PatchSet: 1 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/common: Add PsysPl1 support
by ChiaLing (Code Review) 07 Jun '23

07 Jun '23

ChiaLing has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75678?usp=email ) Change subject: soc/intel/common: Add PsysPl1 support ...................................................................... soc/intel/common: Add PsysPl1 support Set PsysPL1 in set_power_limits in order to increase system performance for no battery design. More power budget for SOC may be released accordingly. BUG=b:281479111 TEST=emerge-dedede coreboot and check PsysPl1 value on DUT Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com> Change-Id: I0b2cf2c90ddef422c121e90edbe79dacb7e29320 --- M src/soc/intel/common/block/include/intelblocks/power_limit.h M src/soc/intel/common/block/power_limit/power_limit.c 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/75678/1 diff --git a/src/soc/intel/common/block/include/intelblocks/power_limit.h b/src/soc/intel/common/block/include/intelblocks/power_limit.h index 290a3a3..8648ac0 100644 --- a/src/soc/intel/common/block/include/intelblocks/power_limit.h +++ b/src/soc/intel/common/block/include/intelblocks/power_limit.h @@ -22,6 +22,8 @@ uint16_t tdp_pl1_override; /* PL2 Override value in Watts */ uint16_t tdp_pl2_override; + /* SysPL1 Value in Watts */ + uint16_t tdp_psyspl1; /* SysPL2 Value in Watts */ uint16_t tdp_psyspl2; /* SysPL3 Value in Watts */ @@ -34,6 +36,8 @@ uint16_t tdp_pl4; /* Estimated maximum platform power in Watts */ uint16_t psys_pmax; + /* Minimun ROP */ + uint16_t min_rop; }; /* Configure power limits for turbo mode */ diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c index adf391f..b5b4208 100644 --- a/src/soc/intel/common/block/power_limit/power_limit.c +++ b/src/soc/intel/common/block/power_limit/power_limit.c @@ -160,6 +160,18 @@ MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = limit.lo & (~(PKG_POWER_LIMIT_EN)); MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = limit.hi; + /* Set PsysPl1 */ + if (conf->tdp_psyspl1) { + limit = rdmsr(MSR_PLATFORM_POWER_LIMIT); + printk(BIOS_INFO, "CPU PsysPL1 = %u Watts\n", + conf->tdp_psyspl1); + limit.lo |= (conf->tdp_psyspl1 * power_unit) & + PKG_POWER_LIMIT_MASK; + limit.lo |= PKG_POWER_LIMIT_CLAMP; + limit.lo |= PKG_POWER_LIMIT_EN; + wrmsr(MSR_PLATFORM_POWER_LIMIT, limit); + } + /* Set PsysPl2 */ if (conf->tdp_psyspl2) { limit = rdmsr(MSR_PLATFORM_POWER_LIMIT); -- To view, visit https://review.coreboot.org/c/coreboot/+/75678?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b2cf2c90ddef422c121e90edbe79dacb7e29320 Gerrit-Change-Number: 75678 Gerrit-PatchSet: 1 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/nissa/var/joxer: Remove VBOOT_GSC_BOARD_ID config
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75641?usp=email ) Change subject: mb/google/nissa/var/joxer: Remove VBOOT_GSC_BOARD_ID config ...................................................................... mb/google/nissa/var/joxer: Remove VBOOT_GSC_BOARD_ID config Board IDs are now filled in as part of the signing process, so we don't need to set them in coreboot. BUG=b:240620735 TEST=Build and check VBOOT_GSC_BOARD_ID is set to ZZCR. Change-Id: I7dda8ad59046a1dd9a28595e037eda86e91c98df Signed-off-by: Reka Norman <rekanorman(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75641 Reviewed-by: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/Kconfig M src/security/vboot/Kconfig 2 files changed, 2 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Himanshu Sahdev: Looks good to me, but someone else must approve Julius Werner: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index ce10aa7..893ec6a 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -292,10 +292,6 @@ select VBOOT_EARLY_EC_SYNC if !BOARD_GOOGLE_BASEBOARD_NISSA select VBOOT_LID_SWITCH -config VBOOT_GSC_BOARD_ID - string - default "LBTV" if BOARD_GOOGLE_JOXER - config DIMM_SPD_SIZE default 512 diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index a998187..a2af5d2 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -336,6 +336,8 @@ help GSC board ID to be embedded in the GSCVD. Usually each specific mainboard variant has its own. Google engineers can find these in the go/cros-dlm database ("Products"). + The specific board IDs are filled in as part of the production signing process, so + this value is just a default and doesn't need to be set per-variant in coreboot. (Note: This is a completely separate thing from coreboot's `board_id()` function.) menu "GBB configuration" -- To view, visit https://review.coreboot.org/c/coreboot/+/75641?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7dda8ad59046a1dd9a28595e037eda86e91c98df Gerrit-Change-Number: 75641 Gerrit-PatchSet: 3 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: acpi: Add a debug option to print out tables in ACPICA compatible hex
by Lean Sheng Tan (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Arthur Heymans, Kyösti Mälkki, Lance Zhao, Nico Huber, Tim Wawrzynczak. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75677?usp=email ) Change subject: acpi: Add a debug option to print out tables in ACPICA compatible hex ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc Gerrit-Change-Number: 75677 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 08:59:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: acpi: Add a debug option to print out tables in ACPICA compatible hex
by Lean Sheng Tan (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Arthur Heymans, Kyösti Mälkki, Lance Zhao, Tim Wawrzynczak. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75677?usp=email ) Change subject: acpi: Add a debug option to print out tables in ACPICA compatible hex ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc Gerrit-Change-Number: 75677 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 08:59:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/nissa/var/uldren: Modify WWAN power sequence
by Derek Huang (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Dtrain Hsu, Shou-Chieh Hsu, Tarun Tuli. Derek Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75690?usp=email ) Change subject: mb/google/nissa/var/uldren: Modify WWAN power sequence ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75690/comment/f5b73994_c30c8906 : PS1, Line 9: WWAN power sequence IIUC, the modification is for warm reboot case. Probably you can mention it and explain why the reset type needs to be PWROK. -- To view, visit https://review.coreboot.org/c/coreboot/+/75690?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If59630dbd10e971c91e01f33a657c01d857bc0b9 Gerrit-Change-Number: 75690 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 08:54:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: acpi: Add a debug option to print out tables in ACPICA compatible hex
by Arthur Heymans (Code Review) 07 Jun '23

07 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75677?usp=email ) Change subject: acpi: Add a debug option to print out tables in ACPICA compatible hex ...................................................................... acpi: Add a debug option to print out tables in ACPICA compatible hex Sometimes systems don't boot to the OS due to wrong ACPI tables. Printing the tables in an ACPICA compatible format makes analysis of ACPI tables easier. To achieve this capture the coreboot log between "Printing ACPI in ACPICA compatible table" and "Done printing ACPI in ACPICA compatible table". Remove the prefix "[SPEW ] " and then call 'acpixtract -a dump' to extract all the tables. Then use iasl on the .dat files to decompile the tables. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc --- M src/Kconfig M src/acpi/acpi.c 2 files changed, 88 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/75677/1 diff --git a/src/Kconfig b/src/Kconfig index f8d7f76..0958fb4 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1294,6 +1294,13 @@ mainboard code supports this. On supported Intel platforms this works by changing the settings in the descriptor.bin file. +config DEBUG_ACPICA_COMPATIBLE + bool "Print out ACPI tables in ACPICA compatible format" + depends on HAVE_ACPI_TABLES + help + Select this to print out ACPI tables in an ACPICA compatible + format. + endmenu ############################################################################### diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 4fdbd6f..da55e92 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1822,23 +1822,79 @@ return coreboot_rsdp; } +static void acpixtract_compatible_hexdump(const void *memory, size_t length) +{ + size_t i, j; + uint8_t *line; + int all_zero = 0; + int all_one = 0; + size_t num_bytes; + + for (i = 0; i < length; i += 16) { + num_bytes = MIN(length - i, 16); + line = ((uint8_t *)memory) + i; + + all_zero++; + all_one++; + for (j = 0; j < num_bytes; j++) { + if (line[j] != 0) { + all_zero = 0; + break; + } + } + + for (j = 0; j < num_bytes; j++) { + if (line[j] != 0xff) { + all_one = 0; + break; + } + } + + if ((all_zero < 2) && (all_one < 2)) { + printk(BIOS_SPEW, " %04lX:", i); + for (j = 0; j < num_bytes; j++) + printk(BIOS_SPEW, " %02x", line[j]); + for (; j < 16; j++) + printk(BIOS_SPEW, " "); + printk(BIOS_SPEW, " "); + for (j = 0; j < num_bytes; j++) + printk(BIOS_SPEW, "%c", + isprint(line[j]) ? line[j] : '.'); + printk(BIOS_SPEW, "\n"); + } else if ((all_zero == 2) || (all_one == 2)) { + printk(BIOS_SPEW, "...\n"); + } + } +} + +static void acpidump_print(void *table_ptr) +{ + const acpi_header_t *header = (acpi_header_t *)table_ptr; + const size_t table_size = header->length; + char table_signature[5] = {}; + memcpy(table_signature, header->signature, sizeof(header->signature)); + printk(BIOS_SPEW, "%s @ 0x0000000000000000\n", table_signature); + acpixtract_compatible_hexdump(table_ptr, table_size); + printk(BIOS_SPEW, "\n"); +} + unsigned long write_acpi_tables(unsigned long start) { unsigned long current; acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_xsdt_t *xsdt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *slic_file, *slic; - acpi_header_t *ssdt; - acpi_header_t *dsdt_file, *dsdt; - acpi_mcfg_t *mcfg; - acpi_tcpa_t *tcpa; - acpi_tpm2_t *tpm2; - acpi_madt_t *madt; - acpi_lpit_t *lpit; - acpi_bert_t *bert; + acpi_rsdt_t *rsdt = NULL; + acpi_xsdt_t *xsdt = NULL; + acpi_fadt_t *fadt = NULL; + acpi_facs_t *facs = NULL; + acpi_header_t *slic_file, *slic = NULL; + acpi_header_t *ssdt = NULL; + acpi_header_t *dsdt_file, *dsdt = NULL; + acpi_mcfg_t *mcfg = NULL; + acpi_tcpa_t *tcpa = NULL; + acpi_tpm2_t *tpm2 = NULL; + acpi_madt_t *madt = NULL; + acpi_lpit_t *lpit = NULL; + acpi_bert_t *bert = NULL; struct device *dev; unsigned long fw; size_t slic_size, dsdt_size; @@ -2101,6 +2157,18 @@ } printk(BIOS_INFO, "ACPI: done.\n"); + + if (CONFIG(DEBUG_ACPICA_COMPATIBLE)) { + printk(BIOS_DEBUG, "Printing ACPI in ACPICA compatible table\n"); + void *acpi_tables[] = { rsdt, xsdt, fadt, facs, slic, ssdt, dsdt, mcfg, tcpa, tpm2, madt, lpit, bert }; + for (size_t i = 0; i < ARRAY_SIZE(acpi_tables); i++) { + if (acpi_tables[i] == NULL) + continue; + acpidump_print(acpi_tables[i]); + } + printk(BIOS_DEBUG, "Done printing ACPI in ACPICA compatible table\n"); + } + return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/75677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc Gerrit-Change-Number: 75677 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/smm: Sanity check the SMM TSEG size
by Bao Zheng (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Bao Zheng, Felix Held, Fred Reitberger, Himanshu Sahdev, Jason Glenesk, Matt DeVillier, Paul Menzel, Raul Rangel, Zheng Bao. Hello Arthur Heymans, Felix Held, Fred Reitberger, Himanshu Sahdev, Jason Glenesk, Matt DeVillier, Paul Menzel, Raul Rangel, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75405?usp=email to look at the new patch set (#7). Change subject: soc/amd/smm: Sanity check the SMM TSEG size ...................................................................... soc/amd/smm: Sanity check the SMM TSEG size As per AMD64 Architecture Programmer's Manual, section 10.2.5 SMRAM Protected Areas: The TSEG range must be aligned to a 128 Kbyte boundary and the minimum TSEG size is 128 Kbytes. The SMM TSEG size should be less than SMM reserved size. AMD TSEG mask works like an MTRR. It needs to be aligned to it's size and it's size needs to be a power of 2. Change-Id: Ic4f557c7b77db6fc5ab2783ca4e2ebe7a4476e85 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/common/block/include/amdblocks/smm.h 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/75405/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/75405?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4f557c7b77db6fc5ab2783ca4e2ebe7a4476e85 Gerrit-Change-Number: 75405 Gerrit-PatchSet: 7 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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