coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: security/intel/cbnt/Makefile: Fix invalid char '*'
by Lean Sheng Tan (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Elyes Haouas. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75638?usp=email ) Change subject: security/intel/cbnt/Makefile: Fix invalid char '*' ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I953e06f1ff70a2b61bc5f505f7df9936b7f9b55b Gerrit-Change-Number: 75638 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 07 Jun 2023 08:40:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: security/intel/cbnt: Remove unneeded go steps
by Lean Sheng Tan (Code Review) 07 Jun '23

07 Jun '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55845?usp=email ) Change subject: security/intel/cbnt: Remove unneeded go steps ...................................................................... security/intel/cbnt: Remove unneeded go steps This updates the go modules in the intel-sec-tools git submodule. This is not needed. Change-Id: I2012d519b07321317fef415df892bbb966512ee2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55845 Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/security/intel/cbnt/Makefile.inc 1 file changed, 0 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved diff --git a/src/security/intel/cbnt/Makefile.inc b/src/security/intel/cbnt/Makefile.inc index 9a29fa6..4959f01 100644 --- a/src/security/intel/cbnt/Makefile.inc +++ b/src/security/intel/cbnt/Makefile.inc @@ -34,8 +34,6 @@ $(CBNT_PROV): printf " CBNT_PROV building tool\n" cd 3rdparty/intel-sec-tools; \ - GO111MODULE=on go mod download; \ - GO111MODULE=on go mod verify; \ GO111MODULE=on go build -o $(abspath $@) cmd/cbnt-prov/*.go else $(CBNT_PROV): $(call strip_quotes, $(CONFIG_INTEL_CBNT_PROV_EXTERNAL_BIN_PATH)) -- To view, visit https://review.coreboot.org/c/coreboot/+/55845?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2012d519b07321317fef415df892bbb966512ee2 Gerrit-Change-Number: 55845 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: security/intel/cbnt: Remove unneeded go steps
by Lean Sheng Tan (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Arthur Heymans, Elyes Haouas. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55845?usp=email ) Change subject: security/intel/cbnt: Remove unneeded go steps ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/55845?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2012d519b07321317fef415df892bbb966512ee2 Gerrit-Change-Number: 55845 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 07 Jun 2023 08:40:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/amd/block/ivrs: Generalize IVRS table generation
by Naresh Solanki (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Felix Singer, Fred Reitberger, Jason Glenesk, Marvin Drees, Matt DeVillier, Raul Rangel. Naresh Solanki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75451?usp=email ) Change subject: soc/amd/block/ivrs: Generalize IVRS table generation ...................................................................... Patch Set 7: (1 comment) File src/soc/amd/common/block/acpi/ivrs.c: https://review.coreboot.org/c/coreboot/+/75451/comment/38928d37_6999b1c6 : PS7, Line 262: /* Find EMMC */ : if (!nb_dev->bus) : dev = pcidev_path_behind(nb_dev->bus, PCI_DEVFN(0x13, 1)); > > Previously, the entry was added without any conditions. […] Thanks for the input. In that case should this limited to 1st IOMMU domain? i.e., if (dev->link_list->secondary == 0) { /* Describe EMMC */ current = ivhd_describe_f0_device(current, PCI_DEVFN(0x13, 1), IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | IVHD_DTE_SYS_MGT_TRANS | IVHD_DTE_NMI_PASS | IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS); } -- To view, visit https://review.coreboot.org/c/coreboot/+/75451?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic471f05d6000c21081d70495b7dbd4350e68b774 Gerrit-Change-Number: 75451 Gerrit-PatchSet: 7 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 07 Jun 2023 08:11:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex/var/rex0: add HID over SPI ACPI driver
by Kapil Porwal (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Eran Mitrani, Matt DeVillier, Tarun Tuli. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74885?usp=email ) Change subject: mb/google/rex/var/rex0: add HID over SPI ACPI driver ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74885?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id51d385ce350cef23da4184b044c74569f4dd3f0 Gerrit-Change-Number: 74885 Gerrit-PatchSet: 16 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 08:05:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/amd/block/ivrs: Generalize IVRS table generation
by Arthur Heymans (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Felix Held, Felix Singer, Fred Reitberger, Jason Glenesk, Marvin Drees, Matt DeVillier, Naresh Solanki, Raul Rangel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75451?usp=email ) Change subject: soc/amd/block/ivrs: Generalize IVRS table generation ...................................................................... Patch Set 7: (1 comment) File src/soc/amd/common/block/acpi/ivrs.c: https://review.coreboot.org/c/coreboot/+/75451/comment/83c9cd0b_8e58769c : PS7, Line 262: /* Find EMMC */ : if (!nb_dev->bus) : dev = pcidev_path_behind(nb_dev->bus, PCI_DEVFN(0x13, 1)); > Previously, the entry was added without any conditions. > It seems that the assumption was made that it is always present. > However, based on my understanding, this entry should only be relevant if the device is present. > I'm uncertain if adding it without any conditions would be appropriate. > Please let me know your thoughts. Will align it accordingly. > Thanks. I don't see any 13.1 device present on any AMD devicetree. I'm not sure if D0x13,F0x1 has any meaning. I guess keeping the behavior to unconditionally add it is the way to go? -- To view, visit https://review.coreboot.org/c/coreboot/+/75451?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic471f05d6000c21081d70495b7dbd4350e68b774 Gerrit-Change-Number: 75451 Gerrit-PatchSet: 7 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 07 Jun 2023 07:55:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/amd/block/ivrs: Generalize IVRS table generation
by Naresh Solanki (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Felix Singer, Fred Reitberger, Jason Glenesk, Marvin Drees, Matt DeVillier, Raul Rangel. Naresh Solanki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75451?usp=email ) Change subject: soc/amd/block/ivrs: Generalize IVRS table generation ...................................................................... Patch Set 7: (1 comment) File src/soc/amd/common/block/acpi/ivrs.c: https://review.coreboot.org/c/coreboot/+/75451/comment/ef2cd2a0_a2effe68 : PS7, Line 262: /* Find EMMC */ : if (!nb_dev->bus) : dev = pcidev_path_behind(nb_dev->bus, PCI_DEVFN(0x13, 1)); > I guess you want this one unconditionally as it does not add a real PCI device? Previously, the entry was added without any conditions. It seems that the assumption was made that it is always present. However, based on my understanding, this entry should only be relevant if the device is present. I'm uncertain if adding it without any conditions would be appropriate. Please let me know your thoughts. Will align it accordingly. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/75451?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic471f05d6000c21081d70495b7dbd4350e68b774 Gerrit-Change-Number: 75451 Gerrit-PatchSet: 7 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 07 Jun 2023 07:47:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[L] Change in em100[master]: add target/download-RPMC/reset
by EvyLiu (Code Review) 07 Jun '23

07 Jun '23

EvyLiu has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/75675?usp=email ) Change subject: add target/download-RPMC/reset ...................................................................... add target/download-RPMC/reset Change-Id: Id470fb9022e6472d90f4a9d3b26076a7518803f3 --- M Makefile A StrToHex.c M chips.c M em100.c M em100.h M fpga.c A ini.c M sdram.c M spi.c M system.c M trace.c M usb.c 12 files changed, 386 insertions(+), 104 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/75/75675/1 diff --git a/Makefile b/Makefile index 1248780..aa7dc4b 100644 --- a/Makefile +++ b/Makefile @@ -37,7 +37,7 @@ PREFIX ?= /usr/local XZ = xz/xz_crc32.c xz/xz_crc64.c xz/xz_dec_bcj.c xz/xz_dec_lzma2.c xz/xz_dec_stream.c -SOURCES = em100.c firmware.c fpga.c hexdump.c sdram.c spi.c system.c trace.c usb.c +SOURCES = em100.c firmware.c fpga.c hexdump.c sdram.c spi.c system.c trace.c usb.c ini.c StrToHex.c SOURCES += image.c curl.c chips.c tar.c $(XZ) OBJECTS = $(SOURCES:.c=.o) diff --git a/StrToHex.c b/StrToHex.c new file mode 100644 index 0000000..f785081 --- /dev/null +++ b/StrToHex.c @@ -0,0 +1,21 @@ +/*StrToHex.c*/ +#include <stdio.h> +#include <string.h> +#include "em100.h" + +int StrToHex(const char *pbSrc) +{ + char h1,h2; + char s1,s2; + + h1 = pbSrc[0]; + h2 = pbSrc[1]; + + s1 = toupper(h1) - 0x30; + if (s1 > 9) + s1 -= 7; + s2 = toupper(h2) - 0x30; + if (s2 > 9) + s2 -= 7; + return (s1*16 + s2); +} diff --git a/chips.c b/chips.c index 52b01c9..7fa952e 100644 --- a/chips.c +++ b/chips.c @@ -196,7 +196,7 @@ } chip->init[entries][0] = 0x23; - chip->init[entries][1] = 0xc9; + chip->init[entries][1] = 0xc9; chip->init[entries][2] = 0x00; chip->init[entries][3] = 0x01; @@ -204,10 +204,11 @@ for (i = 0; i < DEDIPROG_CFG_PRO_SIZE_SFDP; i+=2) { chip->init[entries+len][0] = 0x23; - chip->init[entries+len][1] = 0xc1; + chip->init[entries+len][1] = 0xc1; chip->init[entries+len][2] = sfdp_buffer[i+1]; chip->init[entries+len][3] = sfdp_buffer[i]; len++; + printf("0x23, 0xc1, 0x%x, 0x%x\n",sfdp_buffer[i+1], sfdp_buffer[i]); } *ptr += DEDIPROG_CFG_PRO_SIZE_SFDP; diff --git a/em100.c b/em100.c index 5fd0291..c8365e0 100644 --- a/em100.c +++ b/em100.c @@ -22,8 +22,8 @@ #include <errno.h> #include <sys/stat.h> #include <wordexp.h> - -#include "em100.h" +#include <sys/timeb.h> +#include "em100.h" #define MAX_USB_ERRORS 10 @@ -31,10 +31,11 @@ char *database_version; int debug = 0; int address_mode = 3; +int target = 1; + volatile sig_atomic_t exit_requested = 0; -static struct em100 em100_state; - +static struct em100 em100_state; static void exit_handler(int sig __unused) { exit_requested = 1; @@ -52,6 +53,18 @@ { NULL, 0x0 }, }; +struct RPMC_table_name { + const char *Initialized; + const char *CountValue; + const char *Key; +}; + +static const struct RPMC_table_name table_name[] = { + { "Initialized1","CountValue1","Key1"}, + { "Initialized2","CountValue2","Key2"}, + { "Initialized3","CountValue3","Key3"}, + { "Initialized4","CountValue4","Key4"}, +}; /* High Level functions */ static int set_state(struct em100 *em100, int run) @@ -73,8 +86,63 @@ printf("EM100Pro state unknown\n"); } +static int set_Download_RPMC(struct em100 *em100, struct em100pro_rpmc *e_rpmc) +{// evy CliWriteRMC + + + int retval = 0; + e_rpmc->CMD[0] = 0x68; + uint8_t cmd[16]; + memset(cmd, 0, 16); + cmd[0] = e_rpmc->CMD[0]; + + if(!send_cmd(em100->dev,cmd,16)) + return 0; + + uint8_t cmd1[148]; + memset(cmd1, 0, 148); + memcpy(&cmd1[0], &e_rpmc->allrpmc[0].Status, 148); + if(!send_cmd(em100->dev,cmd1,sizeof(cmd1))) + return 0; + return retval; +} +static int set_reset(struct em100 *em100, unsigned long reset_time) +{// evy setResetPinLow + int retval = 0; + if(reset_time == 1) { + retval = write_fpga_register(em100, 0x10, 0x0C); + } else { + retval = write_fpga_register(em100, 0x10, 0x0E); + + if(retval) + printf("Set reset pin low for time(ms): %ld. \n", reset_time); + //time +#if 0 + struct timeval curtime , nowtime; + gettimeofday(&curtime,NULL); + unsigned long milli = ( (curtime.tv_sec*1000 + curtime.tv_usec/1000) + reset_time); + unsigned long nowmilli = 0; + do { + usleep(1); + gettimeofday(&nowtime,NULL); + nowmilli = (nowtime.tv_sec*1000 + nowtime.tv_usec/1000); + } while( nowmilli < milli); +#else + struct timeval tval; + tval.tv_sec = reset_time / 1000 ; + tval.tv_usec = reset_time % 1000 ; + select(0, NULL, NULL, NULL, &tval); +#endif + + retval = write_fpga_register(em100, 0x10, 0x0F); + if(retval) + printf("Reset operation stoped. \n"); + } + + return retval; +} static int set_address_mode(struct em100 *em100, int mode) -{ +{ int retval; if (mode < 3 || mode > 4) { @@ -90,6 +158,12 @@ return retval; } +static int set_cs(struct em100 *em100, int CSval) +{ + int retval; + retval = write_fpga_register(em100, 0xE0, CSval); + return retval; +} static const char *get_pin_string(int pin) { switch (pin) { @@ -553,15 +627,14 @@ printf("Configuring SPI flash chip emulation.\n"); memset(cmd, 0, 16); - - fpga_voltage = em100->fpga & 0x8000 ? 1800 : 3300; - - for (i = 0; i < desc->init_len; i++) { + + fpga_voltage = em100->fpga & 0x8000 ? 1800 : 3300; + for (i = 0; i < desc->init_len; i++) { if(desc->init[i][0] != 0x11 || desc->init[i][1] != 0x04) continue; - + chip_voltage = (desc->init[i][2] << 8) | desc->init[i][3]; - + switch (chip_voltage) { case 1601: /* 1.65V-2V */ case 1800: @@ -575,8 +648,7 @@ req_voltage = 33; } break; - } - + } if (req_voltage) { if (!set_fpga_voltage(em100, req_voltage)) { printf("Error: The current FPGA firmware (%.1fV) does " @@ -588,8 +660,9 @@ } for (i = 0; i < desc->init_len; i++) { - memcpy(&cmd[0], &desc->init[i][0], BYTES_PER_INIT_ENTRY); - result += !send_cmd(em100->dev, cmd); + memcpy(&cmd[0], &desc->init[i][0], BYTES_PER_INIT_ENTRY); + result += !send_cmd(em100->dev, cmd,16); + } /* @@ -693,7 +766,7 @@ } static chipdesc *setup_chips(const char *desiredchip) -{ +{ static chipdesc chip; char *configs_name = get_em100_file("configs.tar.xz"); configs = tar_load_compressed(configs_name); @@ -747,8 +820,8 @@ strncpy(directory, p.we_wordv[0], FILENAME_BUFFER_SIZE - 1); wordfree(&p); - - DIR *dir = opendir(directory); + + DIR *dir = opendir(directory); if (dir) { /* success */ closedir(dir); @@ -762,8 +835,7 @@ perror("EM100_HOME inaccessible"); directory[0]=0; return NULL; - } - + } return directory; } @@ -772,9 +844,10 @@ char file[FILENAME_BUFFER_SIZE + 1]; strncpy(file, get_em100_home(), FILENAME_BUFFER_SIZE); strncat(file, name, FILENAME_BUFFER_SIZE - strlen(file) - 1); + return strdup(file); } - + static const struct option longopts[] = { {"set", 1, 0, 'c'}, {"download", 1, 0, 'd'}, @@ -800,6 +873,9 @@ {"length", 1, 0, 'L'}, {"brief", 0, 0, 'b'}, {"compatible", 0, 0, 'C'}, + {"target", 1, 0, 'G'}, + {"reset", 1, 0, 'E'}, + {"download-RPMC", 1, 0, 'M'}, {NULL, 0, 0, 0} }; @@ -823,10 +899,10 @@ " -L|--length HEX_VAL: length of buffer for traceconsole mode\n" " -b|--brief: brief mode for traces\n" " -F|--firmware-update FILE|auto: update EM100pro firmware (dangerous)\n" - " -f|--firmware-dump FILE: export raw EM100pro firmware to file\n" + " -f|--firmware-dump FILE: GGGdesiredchip export raw EM100pro firmware to file\n" " -g|--firmware-write FILE: export EM100pro firmware to DPFW file\n" " -S|--set-serialno NUM: set serial number to NUM\n" - " -V|--set-voltage [1.8|3.3] switch FPGA voltage (obsolete)\n" + " -V|--set-voltage [1.8|3.3] switinit[ch FPGA voltage (obsolete)\n" " -p|--holdpin [LOW|FLOAT|INPUT]: set the hold pin state\n" " -x|--device BUS:DEV use EM100pro on USB bus/device\n" " -x|--device EMxxxxxx use EM100pro with serial no EMxxxxxx\n" @@ -834,6 +910,9 @@ " -U|--update-files update device (chip) and firmware database\n" " -C|--compatible enable compatibility mode (patch image for EM100Pro)\n" " -D|--debug: print debug information.\n" + " -G|--target [1|2] target options. \"target\" command must set first\n" + " -E|--reset: reset the target system. Work with -r\n" + " -M|--download-RPMC: download RPMC table to emulator.(Need to work with a file)\n" " -h|--help: this help text\n\n", name); } @@ -841,7 +920,8 @@ int main(int argc, char **argv) { int opt, idx; - const char *desiredchip = NULL; + struct em100pro_chip *desiredchip = malloc(sizeof(struct em100pro_chip)); + const char *desChip = NULL; const char *serialno = NULL; const char *filename = NULL, *read_filename = NULL; const char *firmware_in = NULL, *firmware_out = NULL; @@ -855,30 +935,35 @@ unsigned long address_offset = 0, address_length = 0; unsigned int spi_start_address = 0; const char *voltage = NULL; + //unsigned int target = 1; + unsigned long reset_time = 0; + const char *RPMC_table = NULL; struct sigaction signal_action; struct em100 *em100 = &em100_state; - - while ((opt = getopt_long(argc, argv, "c:d:a:m:u:rsvtO:F:f:g:S:V:p:DCx:lUhTRL:b", - longopts, &idx)) != -1) { + + while ((opt = getopt_long(argc, argv, "G:c:d:a:m:u:rsvtO:F:f:g:S:V:p:DCx:lUhTRL:b:E:M", + longopts, &idx)) != -1) { switch (opt) { - case 'c': - desiredchip = optarg; + case 'G'://evy target + sscanf(optarg, "%d", &target); break; - case 'd': - if(access(optarg, F_OK) == 0) - filename = optarg; + case 'c': + desChip = optarg; + break; + case 'd': + if(access(optarg, F_OK) == 0) + filename = optarg; else printf("Can't open '%s'.\n", optarg); break; case 'a': - sscanf(optarg, "%x", &spi_start_address); - printf("SPI address: 0x%08x\n", spi_start_address); + sscanf(optarg, "%x", &spi_start_address); break; case 'm': sscanf(optarg, "%d", &address_mode); break; case 'u': - read_filename = optarg; + read_filename = optarg; break; case 'V': voltage = optarg; @@ -899,8 +984,7 @@ trace = 1; break; case 'O': - sscanf(optarg, "%lx", &address_offset); - printf("Address offset: 0x%08lx\n", address_offset); + sscanf(optarg, "%lx", &address_offset); break; case 'T': terminal = 1; @@ -942,6 +1026,19 @@ break; case 'b': trace_brief = 1; + break; + case 'E'://evy reset + sscanf(optarg, "%ld", &reset_time); + break; + case 'M'://evy download-RPMC + if(access(optarg, F_OK) == 0) + { + RPMC_table = optarg; + } + else + printf("Can't open '%s'.\n", optarg); + + break; case 'C': compatibility = 1; @@ -952,17 +1049,15 @@ return 0; } } - - if (!em100_attach(em100, bus, device, serial_number)) { + if (!em100_attach(em100, bus, device, serial_number)) { return 1; } - - const chipdesc *chip = setup_chips(desiredchip); - if (desiredchip && !chip) { + + const chipdesc *chip = setup_chips(desChip); + if (desChip && !chip) { em100_detach(em100); return 1; - } - + } /* Set up signal handler. This is used for two reasons: * 1) to create a way to cleanly exit trace mode. * 2) to make sure that the em100 is not left in an improper state @@ -1011,7 +1106,7 @@ get_current_state(em100); get_current_pin_state(em100); printf("\n"); - + if (debug) { em100_debug(em100); } @@ -1049,8 +1144,20 @@ if (do_stop) { set_state(em100, 0); } + if (target) { + if((target == 1) || (target ==2)) { + printf("Now is emulating on CS%d.\n",target); + set_cs(em100, (target == 1) ? 0 : 1); + } + else { + printf("Failed configuring target.\n"); + em100_detach(em100); + return 0; + } + } + if (desChip) { + desiredchip->chip[target-1].chipName = desChip; - if (desiredchip) { if (!set_chip_type(em100, chip)) { printf("Failed configuring chip type.\n"); em100_detach(em100); @@ -1061,12 +1168,13 @@ /* Automatically enable 4 byte address mode for chips >16MB * unless specified by the user on the command line. */ + if (!address_mode && chip->size > (16 * 1024 * 1024)) { set_address_mode(em100, 4); } } - if (address_mode) { + if (address_mode) { if (set_address_mode(em100, address_mode) < 0) { em100_detach(em100); return 1; @@ -1082,7 +1190,7 @@ } if (holdpin) { - if (!set_hold_pin_state_from_str(em100, holdpin)) { + if (!set_hold_pin_state_from_str(em100, holdpin)) { printf("Failed configuring hold pin state.\n"); em100_detach(em100); return 0; @@ -1092,7 +1200,7 @@ if (read_filename) { int maxlen = 0x4000000; /* largest size - 64MB */ - if (!desiredchip) { + if (!desiredchip->chip[target-1].chipName) { /* Read configured SPI emulation from EM100 */ chipdesc emulated_chip; @@ -1132,7 +1240,7 @@ } if (filename) { - unsigned int maxlen = desiredchip ? chip->size : 0x4000000; /* largest size - 64MB */ + unsigned int maxlen = desiredchip->chip[target-1].chipName ? chip->size : 0x4000000; /* largest size - 64MB */ void *data = malloc(maxlen); int done; void *readback = NULL; @@ -1172,7 +1280,7 @@ return 1; } - if (desiredchip && (length != (chip->size - spi_start_address)) ) + if (desiredchip->chip[target-1].chipName && (length != (chip->size - (spi_start_address & ~(0x80000000))))) { printf("FATAL: file size does not match to chip size.\n"); free(data); @@ -1193,7 +1301,7 @@ } done = read_sdram(em100, readback, 0, maxlen); if (done) { - memcpy((unsigned char*)readback + spi_start_address, data, length); + memcpy((unsigned char*)readback + (spi_start_address & ~(0x80000000)), data, length); write_sdram(em100, (unsigned char*)readback, 0x00000000, maxlen); } else { printf("Error: sdram readback failed\n"); @@ -1211,7 +1319,7 @@ em100_detach(em100); return 1; } - done = read_sdram(em100, readback, spi_start_address, length); + done = read_sdram(em100, readback, spi_start_address & ~(0x80000000), length); if (done && (memcmp(data, readback, length) == 0)) printf("Verify: PASS\n"); else { @@ -1226,9 +1334,18 @@ free(data); } - + if (reset_time) { + if(!do_start) { + printf("'Reset' have to work with 'Start'. \n"); + } + } if (do_start) { + if (reset_time) { + printf("Enable reset pin\n"); + set_reset(em100,reset_time); + } set_state(em100, 1); + } if (trace || terminal || traceconsole) { @@ -1251,10 +1368,10 @@ } if (terminal) { + init_spi_terminal(em100); - printf("terminal"); - } - + printf("terminal"); + } printf(". Press CTRL-C to exit.\n\n"); fflush(stdout); @@ -1265,9 +1382,10 @@ ret = read_spi_trace_console(em100, address_offset, address_length); else if (trace) ret = read_spi_trace(em100, terminal, address_offset); - else if (terminal) + else if (terminal) { ret = read_spi_terminal(em100, 0); - + } + if (ret == 0) usb_errors++; if (ret < 0) @@ -1287,7 +1405,44 @@ em100_detach(em100); return 1; } + } + if(RPMC_table){ + + printf("Downloading RPMC table to EM100Pro, please wait...\n"); + FILE *fdata = fopen(RPMC_table, "r+"); + if (!fdata) { + perror("Could not open upload file"); + free(fdata); + em100_detach(em100); + return 1; + } + struct em100pro_rpmc *e_rpmc = malloc(sizeof(struct em100pro_rpmc)); //struct rpmc init + char DesInt[2]; + int ret; + + for(int i = 0 ; i < 4 ; i++) + { + char buff[64] = {0}; + ret = GetIniKeyString("DediProg RPMC",table_name[i].Initialized,RPMC_table,buff); + + e_rpmc->allrpmc[i].Status = atoi(buff); + + for(int j = 0 ; j < 4 ; j++) + { + ret = GetIniKeyString("DediProg RPMC",table_name[i].CountValue,RPMC_table,buff); + strncpy(DesInt,&buff[j*2],2); + e_rpmc->allrpmc[i].CountValue[j] = StrToHex(DesInt); + } + + for(int j = 0 ; j < 32 ; j++) + { + ret = GetIniKeyString("DediProg RPMC",table_name[i].Key,RPMC_table,buff); + strncpy(DesInt,&buff[j*2],2); + e_rpmc->allrpmc[i].Key[j] = StrToHex(DesInt); + } + } + set_Download_RPMC(em100,e_rpmc); + printf("Download complete\n"); } - return em100_detach(em100); -} +} diff --git a/em100.h b/em100.h index 4ba78a9..227a023 100644 --- a/em100.h +++ b/em100.h @@ -16,6 +16,7 @@ #include <libusb.h> #include <signal.h> +#include <ctype.h> #define __unused __attribute__((unused)) #define __packed __attribute__((packed)) @@ -39,6 +40,24 @@ int init_len; } chipdesc; +struct rpmc{ + uint8_t Status; + uint8_t CountValue[4]; + uint8_t Key[32]; +} __attribute__ ((packed)); + +struct em100pro_rpmc{ + uint8_t CMD[16]; + struct rpmc allrpmc[4]; +} __attribute__ ((packed)); + +struct chip_name{ + const char *chipName; +}__attribute__ ((packed)); + +struct em100pro_chip{ + struct chip_name chip[2]; +}__attribute__ ((packed)); /* Hardware versions */ #define HWVERSION_EM100PRO_EARLY 0xff #define HWVERSION_EM100PRO 0x04 @@ -47,7 +66,7 @@ #define BULK_SEND_TIMEOUT 5000 /* sentinel value */ /* usb.c */ -int send_cmd(libusb_device_handle *dev, void *data); +int send_cmd(libusb_device_handle *dev, void *data, int length); int get_response(libusb_device_handle *dev, void *data, int length); /* firmware.c */ @@ -158,6 +177,11 @@ uint8_t data[255]; } __attribute__ ((packed)); + +struct em100_chip{ + const char *chipType; +} __attribute__ ((packed)); + typedef enum { ht_checkpoint_1byte = 0x01, ht_checkpoint_2bytes = 0x02, @@ -209,4 +233,10 @@ /* Images */ int autocorrect_image(struct em100 *em100, char *image, size_t size); +/*ini*/ +int GetIniKeyString(const char *title,const char *key,const char *filename,char *buf); + +/*StrToHex*/ +int StrToHex(const char *pbSrc); + #endif diff --git a/fpga.c b/fpga.c index 301427c..4e33528 100644 --- a/fpga.c +++ b/fpga.c @@ -29,7 +29,7 @@ unsigned char cmd[16]; memset(cmd, 0, 16); cmd[0] = 0x20; /* reconfig FPGA */ - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { return 0; } /* Specification says to wait 2s before @@ -53,7 +53,7 @@ printf("FPGA configuration status: "); memset(cmd, 0, 16); cmd[0] = 0x21; /* Check FPGA status */ - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { printf("Unknown\n"); return 0; } @@ -83,7 +83,7 @@ memset(cmd, 0, 16); cmd[0] = 0x22; /* Read FPGA register */ cmd[1] = reg; - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { return 0; } int len = get_response(em100->dev, data, 3); @@ -108,7 +108,7 @@ cmd[1] = reg; cmd[2] = val >> 8; cmd[3] = val & 0xff; - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { return 0; } return 1; @@ -124,7 +124,7 @@ cmd[2] = 7; cmd[3] = 0x80; } - if (!send_cmd(em100->dev, cmd)) + if (!send_cmd(em100->dev, cmd, 16)) return 0; return 1; @@ -146,7 +146,7 @@ memset(cmd, '\0', 16); cmd[0] = 0x20; /* Switch FPGA */ - if (!send_cmd(em100->dev, cmd)) + if (!send_cmd(em100->dev, cmd, 16)) return 0; return 1; diff --git a/ini.c b/ini.c new file mode 100644 index 0000000..d24b309 --- /dev/null +++ b/ini.c @@ -0,0 +1,73 @@ +/*ini.c*/ +#include <stdio.h> +#include <string.h> +#include "em100.h" + +int GetIniKeyString(const char *title,const char *key,const char *filename,char *buf) +{ + FILE *fp; + int flag = 0; + char sTitle[64], *wTmp; + char sLine[1024]; + sprintf(sTitle, "[%s]", title); + + if(NULL == (fp = fopen(filename, "r"))) { + perror("fopen"); + return -1; + } + while (NULL != fgets(sLine, 1024, fp)) { + if (0 == strncmp("//", sLine, 2)) continue; + if ('#' == sLine[0]) continue; + wTmp = strchr(sLine, '='); + if ((NULL != wTmp) && (1 == flag)) { + if (0 == strncmp(key, sLine, strlen(key))) { + sLine[strlen(sLine) - 1] = '\0'; + fclose(fp); + while(*(wTmp + 1) == ' '){ + wTmp++; + } + strcpy(buf,wTmp + 1); + return 0; + } + } else { + if (0 == strncmp(sTitle, sLine, strlen(sTitle))) { + flag = 1; + } + } + } + fclose(fp); + return -1; +} + +int PutIniKeyString(char *title,char *key,char *val,char *filename) +{ + FILE *fpr, *fpw; + int flag = 0; + char sLine[1024], sTitle[32], *wTmp; + sprintf(sTitle, "[%s]", title); + if (NULL == (fpr = fopen(filename, "r"))) + return -1; + sprintf(sLine, "%s.tmp", filename); + if (NULL == (fpw = fopen(sLine, "w"))) + return -1; + while (NULL != fgets(sLine, 1024, fpr)) { + if (2 != flag) { + wTmp = strchr(sLine, '='); + if ((NULL != wTmp) && (1 == flag)) { + if (0 == strncmp(key, sLine, strlen(key))) { + flag = 2; + sprintf(wTmp + 1, " %s\n", val); + } + } else { + if (0 == strncmp(sTitle, sLine, strlen(sTitle))) { + flag = 1; + } + } + } + fputs(sLine, fpw); + } + fclose(fpr); + fclose(fpw); + sprintf(sLine, "%s.tmp", filename); + return rename(sLine, filename); +} diff --git a/sdram.c b/sdram.c index 408afd8..7daa13c 100644 --- a/sdram.c +++ b/sdram.c @@ -37,7 +37,7 @@ cmd[7] = (length >> 8) & 0xff; cmd[8] = length & 0xff; - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { printf("error initiating host-to-em100 transfer.\n"); return 0; } @@ -87,7 +87,7 @@ cmd[7] = (length >> 8) & 0xff; cmd[8] = length & 0xff; - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { printf("error initiating host-to-em100 transfer.\n"); return 0; } diff --git a/spi.c b/spi.c index c088a11..c26325d 100644 --- a/spi.c +++ b/spi.c @@ -24,7 +24,7 @@ unsigned char data[512]; memset(cmd, 0, 16); cmd[0] = 0x30; /* Get SPI flash ID */ - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { return 0; } int len = get_response(em100->dev, data, 512); @@ -40,7 +40,7 @@ unsigned char cmd[16]; memset(cmd, 0, 16); cmd[0] = 0x31; /* Erase SPI flash */ - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { return 0; } /* Specification says to wait 5s before @@ -56,7 +56,7 @@ unsigned char data[1]; memset(cmd, 0, 16); cmd[0] = 0x32; /* Poll SPI flash status */ - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { return 0; } int len = get_response(em100->dev, data, 1); @@ -84,7 +84,7 @@ cmd[1] = (address >> 16) & 0xff; cmd[2] = (address >> 8) & 0xff; cmd[3] = address & 0xff; - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { return 0; } int len = get_response(em100->dev, data, 256); @@ -109,7 +109,7 @@ cmd[2] = (address >> 8) & 0xff; cmd[3] = address & 0xff; - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { printf("Error: Could not initiate host-to-EM100 transfer.\n"); return 0; } @@ -141,7 +141,7 @@ unsigned char cmd[16]; memset(cmd, 0, 16); cmd[0] = 0x36; /* Unlock SPI flash */ - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { return 0; } /* Specification says to wait 5s before @@ -166,7 +166,7 @@ memset(cmd, 0, 16); cmd[0] = 0x37; /* Erase SPI flash sector */ cmd[1] = sector; - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { return 0; } /* Specification says to wait 5s before @@ -210,7 +210,7 @@ memset(cmd, 0, 16); cmd[0] = 0x50; /* read fpga register */ cmd[1] = reg; - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { return 0; } int len = get_response(em100->dev, data, 2); @@ -234,7 +234,7 @@ cmd[0] = 0x51; /* write fpga registers */ cmd[1] = reg; cmd[2] = val; - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { return 0; } return 1; @@ -263,7 +263,7 @@ cmd[3] = (timeout >> 8) & 0xff; cmd[4] = timeout & 0xff; - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { printf("Error: Could not initiate host-to-EM100 transfer.\n"); return 0; } @@ -301,7 +301,7 @@ int read_ufifo(struct em100 *em100, size_t length, unsigned int timeout, unsigned char *blk) -{ +{ unsigned char cmd[16]; unsigned char data[512]; unsigned char data2[2]; @@ -310,24 +310,24 @@ printf("Error: Length of data to be read from uFIFO can't be" " > 512\n"); return 0; - } + } memset(cmd, 0, 16); cmd[0] = 0x53; /* read uFIFO */ cmd[1] = (length >> 8) & 0xff; cmd[2] = length & 0xff; cmd[3] = (timeout >> 8) & 0xff; cmd[4] = timeout & 0xff; - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { return 0; - } + } size_t len = get_response(em100->dev, data, 512); /* get second response from read ufifo command */ get_response(em100->dev, data2, 2); if (len == length) { - memcpy(blk, data, length); + memcpy(blk, data, length); return 1; - } + } return 0; } diff --git a/system.c b/system.c index 9286118..b707e02 100644 --- a/system.c +++ b/system.c @@ -30,7 +30,7 @@ unsigned char data[512]; memset(cmd, 0, 16); cmd[0] = 0x10; /* version */ - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { return 0; } int len = get_response(em100->dev, data, 512); @@ -58,7 +58,7 @@ cmd[1] = channel; cmd[2] = mV >> 8; cmd[3] = mV & 0xff; - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { return 0; } return 1; @@ -73,7 +73,7 @@ memset(cmd, 0, 16); cmd[0] = 0x12; /* measure voltage */ cmd[1] = channel; - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { return 0; } int len = get_response(em100->dev, data, 512); @@ -103,7 +103,7 @@ memset(cmd, 0, 16); cmd[0] = 0x13; /* set LED */ cmd[1] = led_state; - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { return 0; } return 1; diff --git a/trace.c b/trace.c index 038488a..d8b3cb4 100644 --- a/trace.c +++ b/trace.c @@ -4,7 +4,7 @@ * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. - * + *do_write * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the @@ -30,7 +30,7 @@ unsigned char cmd[16]; memset(cmd, 0, 16); cmd[0] = 0xbd; /* reset SPI trace buffer*/ - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { return 0; } return 1; @@ -86,7 +86,7 @@ */ cmd[9] = 0x15; - if (!send_cmd(em100->dev, cmd)) { + if (!send_cmd(em100->dev, cmd, 16)) { printf("sending trace command failed\n"); return 0; } @@ -464,12 +464,12 @@ else do_write = 0; } - + if (do_write == 0 || (spi_cmd_vals->address_type == ADDR_NONE || address < addr_offset || address > (addr_offset + addr_len))) { - curpos = data[2 + i*8 + 1] + 0x10; + curpos = data[2 + i*8 + 1] + 0x10; continue; } @@ -501,7 +501,7 @@ * the data looking for the signature. */ int read_spi_terminal(struct em100 *em100, int show_counter) -{ +{ unsigned char data[UFIFO_SIZE] = { 0 }; static unsigned int msg_counter = 1; /* Number of messages */ uint16_t data_length; @@ -511,7 +511,7 @@ if (!read_ufifo(em100, UFIFO_SIZE, UFIFO_TIMEOUT, &data[0])) return 0; - + /* the first two bytes are the amount of valid data */ data_length = (data[0] << 8) + data[1]; if (data_length == 0) @@ -524,9 +524,9 @@ for (j = 0; j < data_length && j < UFIFO_SIZE - sizeof(struct em100_msg_header); j++) { - msg = (struct em100_msg *)(data_start + j); + msg = (struct em100_msg *)(data_start + j); if (msg->header.signature == EM100_MSG_SIGNATURE) { - + if (show_counter) printf("\nHT%06d: ", msg_counter); diff --git a/usb.c b/usb.c index 4fd3df5..7492557 100644 --- a/usb.c +++ b/usb.c @@ -16,10 +16,12 @@ /* USB communication */ -int send_cmd(libusb_device_handle *dev, void *data) +int send_cmd(libusb_device_handle *dev, void *data, int length) { int actual; - int length = 16; /* haven't seen any other length yet */ + + //int length = 16; /* haven't seen any other length yet */ + /*length of RPMC is 148*/ int ret = libusb_bulk_transfer(dev, 1 | LIBUSB_ENDPOINT_OUT, data, length, &actual, BULK_SEND_TIMEOUT); if (LIBUSB_SUCCESS != ret) -- To view, visit https://review.coreboot.org/c/em100/+/75675?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: master Gerrit-Change-Id: Id470fb9022e6472d90f4a9d3b26076a7518803f3 Gerrit-Change-Number: 75675 Gerrit-PatchSet: 1 Gerrit-Owner: EvyLiu <evy.liu(a)dediprog.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/nissa/var/uldren: Modify WWAN power sequence
by Dtrain Hsu (Code Review) 07 Jun '23

07 Jun '23

Dtrain Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75690?usp=email ) Change subject: mb/google/nissa/var/uldren: Modify WWAN power sequence ...................................................................... mb/google/nissa/var/uldren: Modify WWAN power sequence Follow spec[1] to modify WWAN power sequence. [1]: [JDB10] FC ADL-N_WWAN sequence_FM101-GL SDX12 Power Timing Review_V1.6_20230602.xlsx BUG=b:285065375 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot chromeos-bootimage 2. power sequence meets spec. Change-Id: If59630dbd10e971c91e01f33a657c01d857bc0b9 Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/uldren/gpio.c 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/75690/1 diff --git a/src/mainboard/google/brya/variants/uldren/gpio.c b/src/mainboard/google/brya/variants/uldren/gpio.c index c0c43814..0ea14cd 100644 --- a/src/mainboard/google/brya/variants/uldren/gpio.c +++ b/src/mainboard/google/brya/variants/uldren/gpio.c @@ -20,7 +20,7 @@ /* C1 : SMBDA==> TCHSCR_RST_L */ PAD_CFG_GPO(GPP_C1, 1, DEEP), /* D6 : SRCCLKREQ1# ==> WWAN_EN */ - PAD_CFG_GPO(GPP_D6, 1, DEEP), + PAD_CFG_GPO(GPP_D6, 1, PWROK), /* D7 : SRCCLKREQ2# ==> NC */ PAD_NC(GPP_D7, NONE), /* D8 : SRCCLKREQ3# ==> NC */ @@ -61,8 +61,6 @@ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), /* B15 : HP_RST_ODL */ PAD_CFG_GPO(GPP_B15, 0, DEEP), - /* D6 : SRCCLKREQ1# ==> WWAN_EN */ - PAD_CFG_GPO(GPP_D6, 1, DEEP), /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), /* F12 : GSXDOUT ==> WWAN_RST_L */ -- To view, visit https://review.coreboot.org/c/coreboot/+/75690?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If59630dbd10e971c91e01f33a657c01d857bc0b9 Gerrit-Change-Number: 75690 Gerrit-PatchSet: 1 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/amd/stoneyridge/acpi/northbridge: drop _STA method from PCI0 scope
by Arthur Heymans (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Felix Held, Matt DeVillier. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75671?usp=email ) Change subject: soc/amd/stoneyridge/acpi/northbridge: drop _STA method from PCI0 scope ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75671?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I663c7bcba89ffe25d0819d83461cb95e10f49028 Gerrit-Change-Number: 75671 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 07 Jun 2023 07:11:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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