coreboot-gerrit June 2023

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[M] Change in coreboot[master]: WIP acpi: Add SPCR table
by Arthur Heymans (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Benjamin Doron, Lance Zhao, Tim Wawrzynczak. Hello Benjamin Doron, Lance Zhao, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75685?usp=email to look at the new patch set (#2). Change subject: WIP acpi: Add SPCR table ...................................................................... WIP acpi: Add SPCR table TESTED works on IO and MMIO console. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I64e624c17a27b9215a8ba83bd6cbb2c0a7aa1dfc --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 87 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/75685/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75685?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64e624c17a27b9215a8ba83bd6cbb2c0a7aa1dfc Gerrit-Change-Number: 75685 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: soc/amd/phoenix: Hook up xhci ops in chipset.cb
by Eric Lai (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Jon Murphy, Martin L Roth, Martin Roth, Matt DeVillier, Paul Menzel. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75659?usp=email ) Change subject: soc/amd/phoenix: Hook up xhci ops in chipset.cb ...................................................................... Patch Set 6: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75659/comment/44e33232_4e743836 : PS5, Line 9: Add hook up > Hook up Done https://review.coreboot.org/c/coreboot/+/75659/comment/7df1147f_841f7f01 : PS5, Line 9: Add hook up xhci ops for Phoenix xHCI device. > Add the motivation? Maybe: … so they are properly configured. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75659?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib59874948725966b04b54def3f6de463afeda709 Gerrit-Change-Number: 75659 Gerrit-PatchSet: 6 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 12:15:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/phoenix: Hook up xhci ops in chipset.cb
by Eric Lai (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Eric Lai, Fred Reitberger, Jason Glenesk, Jon Murphy, Martin L Roth, Martin Roth, Matt DeVillier. Hello Felix Held, Fred Reitberger, Jason Glenesk, Jon Murphy, Karthik Ramasubramanian, Martin Roth, Matt DeVillier, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75659?usp=email to look at the new patch set (#6). Change subject: soc/amd/phoenix: Hook up xhci ops in chipset.cb ...................................................................... soc/amd/phoenix: Hook up xhci ops in chipset.cb Hook up xhci ops for Phoenix xHCI device. Benefit is we don't have to bother by adding xhci DID. BUG=b:285981912 TEST=check coreboot log shows below. [INFO ] \_SB.PCI0.GP41.XHC0.RHUB.SS01: USB3 Type-A Port A0 (MLB) Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: Ib59874948725966b04b54def3f6de463afeda709 --- M src/drivers/usb/pci_xhci/pci_xhci.c M src/soc/amd/phoenix/chipset.cb 2 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/75659/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/75659?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib59874948725966b04b54def3f6de463afeda709 Gerrit-Change-Number: 75659 Gerrit-PatchSet: 6 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: drivers/uart: Add ACPI SPCR table generation
by Arthur Heymans (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Martin L Roth. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49317?usp=email ) Change subject: drivers/uart: Add ACPI SPCR table generation ...................................................................... Patch Set 4: (1 comment) File src/drivers/uart/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/49317/comment/cc509645_1a870e09 : PS4, Line 264: return current; > So we filled in the entire SPCR inside ACPI CBMEM region, but decide here to abandon it? There's no real harm, but I feel it would be cleaner to abandon early.. > > If I ananlyzed correctly that dev_update_spcr() is no-op in this commit, and update_spcr_data() is the only place setting spcr>base_address.addrl, seems to me the entire uart_acpi_write_spcr() call should be conditional on CONSOLE_SERIAL. > > I don't see what prevents creation of multiple SPCR entries in the case of multiple UARTs. All would have same uart_platform_base(CONFIG_UART_FOR_CONSOLE)? Linux only looks for the first SPCR table. -- To view, visit https://review.coreboot.org/c/coreboot/+/49317?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1e7c17adcf5b2a8206a8308e057855819ec413a Gerrit-Change-Number: 49317 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 11:51:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: src/: Cache ISH version in CMOS memory for cold boots
by Dinesh Gehlot (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Subrata Banik. Hello Kapil Porwal, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75689?usp=email to look at the new patch set (#3). Change subject: src/: Cache ISH version in CMOS memory for cold boots ...................................................................... src/: Cache ISH version in CMOS memory for cold boots This patch stores the ISH version in CMOS memory. During a cold reboot, it updates the CBMEM stored ISH version using the CMOS stored ISH version. Previously, the ISH version was updated using CSE during a cold reboot, which was time-consuming. This change will improve the performance of cold reboots by approximately ~200ms. Additionally it removes unused variables for the CBMEM firmware version data structure. BUG=b:280722061 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I2ea03298ae239c4597de9fd23a88c23f21e2f224 --- M src/drivers/intel/ish/ish.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_cmos.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/common/block/include/intelblocks/cse_cmos.h 7 files changed, 93 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/75689/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/75689?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ea03298ae239c4597de9fd23a88c23f21e2f224 Gerrit-Change-Number: 75689 Gerrit-PatchSet: 3 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/cmd/blk: Implement an API to get ISH version
by Dinesh Gehlot (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Kapil Porwal, Subrata Banik. Hello Kapil Porwal, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75689?usp=email to look at the new patch set (#2). Change subject: soc/intel/cmd/blk: Implement an API to get ISH version ...................................................................... soc/intel/cmd/blk: Implement an API to get ISH version This patch stores the ISH version in CMOS memory. During a cold reboot, it updates the CBMEM stored ISH version using the CMOS stored ISH version. Previously, the ISH version was updated using CSE during a cold reboot, which was time-consuming. This change will improve the performance of cold reboots by approximately ~200ms. Additionally it removes unused variables for the CBMEM firmware version data structure. BUG=b:280722061 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I2ea03298ae239c4597de9fd23a88c23f21e2f224 --- M src/drivers/intel/ish/ish.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_cmos.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/common/block/include/intelblocks/cse_cmos.h 7 files changed, 93 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/75689/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75689?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ea03298ae239c4597de9fd23a88c23f21e2f224 Gerrit-Change-Number: 75689 Gerrit-PatchSet: 2 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/cmd/blk: Implement an API to get CSE version
by Dinesh Gehlot (Code Review) 07 Jun '23

07 Jun '23

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75689?usp=email ) Change subject: soc/intel/cmd/blk: Implement an API to get CSE version ...................................................................... soc/intel/cmd/blk: Implement an API to get CSE version This patch stores the ISH version in CMOS memory. During a cold reboot, it updates the CBMEM stored ISH version using the CMOS stored ISH version. Previously, the ISH version was updated using CSE during a cold reboot, which was time-consuming. This change will improve the performance of cold reboots by approximately ~200ms. Additionally it removes unused variables for the CBMEM firmware version data structure. BUG=b:280722061 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I2ea03298ae239c4597de9fd23a88c23f21e2f224 --- M src/drivers/intel/ish/ish.c M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/cse/cse_cmos.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/common/block/include/intelblocks/cse_cmos.h 7 files changed, 93 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/75689/1 diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index 0415af0..3608b20 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -55,10 +55,10 @@ return; printk(BIOS_DEBUG, "ISH version: %d.%d.%d.%d\n", - version->ish_partition_info.cur_ish_fw_version.major, - version->ish_partition_info.cur_ish_fw_version.minor, - version->ish_partition_info.cur_ish_fw_version.hotfix, - version->ish_partition_info.cur_ish_fw_version.build); + version->ish_version.major, + version->ish_version.minor, + version->ish_version.hotfix, + version->ish_version.build); } static void intel_ish_final(struct device *dev) diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 4426d5a..ea3d8ca 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -54,10 +54,17 @@ CMOS memory. The offset should be byte aligned and must leave enough memory to store required firmware partition versions. +config SOC_INTEL_STORE_ISH_VERSION + bool + default y + depends on DRIVERS_INTEL_ISH && SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION + help + This configuration option stores ISH version in CMOS and CBMEM memory. This information + can be used to identify the currently running ISH firmware partition version. + config SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION bool - default n - depends on DRIVERS_INTEL_ISH + default y help This configuration option stores CSE FPT partitions' version in CMOS and CBMEM memory. This information can be used to identify the currently running firmware partition diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 40489c7..18a36f9 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1222,10 +1222,10 @@ return; printk(BIOS_DEBUG, "CSE version: %d.%d.%d.%d\n", - version->cur_cse_fw_version.major, - version->cur_cse_fw_version.minor, - version->cur_cse_fw_version.hotfix, - version->cur_cse_fw_version.build); + version->cse_version.major, + version->cse_version.minor, + version->cse_version.hotfix, + version->cse_version.build); } #if ENV_RAMSTAGE diff --git a/src/soc/intel/common/block/cse/cse_cmos.c b/src/soc/intel/common/block/cse/cse_cmos.c index 0f8c96a..151ab69 100644 --- a/src/soc/intel/common/block/cse/cse_cmos.c +++ b/src/soc/intel/common/block/cse/cse_cmos.c @@ -40,7 +40,7 @@ struct cse_fw_table { uint32_t signature; - struct fw_version cse_version; + struct cse_fw_partition_info partition_info; uint16_t checksum; } __packed; @@ -87,7 +87,10 @@ { u8 i, *p, offset = PARTITION_FW_CMOS_OFFSET; version->signature = PARTITION_FW_SIGNATURE; - memset(&version->cse_version, 0, sizeof(struct fw_version)); + memset(&version->partition_info.cse_version, 0, sizeof(struct fw_version)); +#if CONFIG_SOC_INTEL_STORE_ISH_VERSION + memset(&version->partition_info.ish_version, 0, sizeof(struct fw_version)); +#endif version->checksum = compute_ip_checksum(version, offsetof(struct cse_fw_table, checksum)); for (p = (u8 *)version, i = 0; i < sizeof(*version); i++, p++) @@ -105,7 +108,7 @@ */ init_cmos_partition_version(&version); } - memcpy(cse_version, &version.cse_version, sizeof(struct fw_version)); + memcpy(cse_version, &version.partition_info.cse_version, sizeof(struct fw_version)); } /* API that allows users to update CSE version stored in CMOS memory. */ @@ -119,6 +122,35 @@ */ init_cmos_partition_version(&version); } - memcpy(&version.cse_version, cse_version, sizeof(struct fw_version)); + memcpy(&version.partition_info.cse_version, cse_version, sizeof(struct fw_version)); write_cmos_partition_version(&version); } + +#if CONFIG_SOC_INTEL_STORE_ISH_VERSION + +/* API that allows users to read ISH version stored in CMOS memory. */ +void get_cmos_ish_version(struct fw_version *ish_version) +{ + struct cse_fw_table version; + if (read_cmos_partition_version(&version)) { + /* CMOS failed to read the ISH version. Possibly CMOS area has corrupted. */ + printk(BIOS_WARNING, "CMOS fw version corrupted, initiating memory re-init\n"); + init_cmos_partition_version(&version); + } + memcpy(ish_version, &version.partition_info.ish_version, sizeof(struct fw_version)); +} + +/* API that allows users to update ISH version stored in CMOS memory. */ +void set_cmos_ish_version(const struct fw_version *ish_version) +{ + struct cse_fw_table version; + if (read_cmos_partition_version(&version)) { + /* CMOS failed to read the ISH version. Possibly CMOS area has corrupted. */ + printk(BIOS_WARNING, "CMOS fw version corrupted, initiating memory re-init\n"); + init_cmos_partition_version(&version); + } + memcpy(&version.partition_info.ish_version, ish_version, sizeof(struct fw_version)); + write_cmos_partition_version(&version); +} + +#endif /* SOC_INTEL_STORE_ISH_VERSION */ diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index cf1df2b..a8d3f66 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1172,6 +1172,7 @@ timestamp_add_now(TS_CSE_FW_SYNC_END); } +#if CONFIG_SOC_INTEL_STORE_ISH_VERSION static enum cb_err send_get_fpt_partition_info_cmd(enum fpt_partition_id id, struct fw_version_resp *resp) { @@ -1229,52 +1230,7 @@ return send_get_fpt_partition_info_cmd(id, resp); } - -/* - * Helper function to read ISH version from CSE FPT using HECI command. - * - * The HECI command only be executed after memory has been initialized. - * This is because the command relies on resources that are not available - * until DRAM initialization command has been sent. - */ -static void store_ish_version(void) -{ - if (!ENV_RAMSTAGE) - return; - - if (vboot_recovery_mode_enabled()) - return; - - struct cse_fw_partition_info *version; - size_t size = sizeof(struct fw_version); - version = cbmem_find(CBMEM_ID_CSE_PARTITION_VERSION); - if (version == NULL) - return; - - /* - * Compare if stored cse version (from the previous boot) is same as current - * running cse version. - */ - if (memcmp(&version->ish_partition_info.prev_cse_fw_version, - &version->cur_cse_fw_version, sizeof(struct fw_version))) { - /* - * Current running CSE version is different than previous stored CSE version - * which could be due to CSE update or rollback, hence, need to send ISHC - * partition info cmd to know the currently running ISH version. - */ - - struct fw_version_resp resp; - if (cse_get_fpt_partition_info(FPT_PARTITION_NAME_ISHC, &resp) == CB_SUCCESS) { - /* Update stored cse version with current version */ - memcpy(&(version->ish_partition_info.prev_cse_fw_version), - &(version->cur_cse_fw_version), size); - - /* Since cse version has been updated, ish version needs to be updated. */ - memcpy(&(version->ish_partition_info.cur_ish_fw_version), - &(resp.manifest_data.version), size); - } - } -} +#endif /* * Helper function that stores current CSE firmware version and ISH version to @@ -1319,16 +1275,39 @@ set_cmos_cse_version(&(cse_bp->fw_ver)); /* write cse rw fw version to CBMEM */ - memcpy(&(cbmem_fw->cur_cse_fw_version), &(cse_bp->fw_ver), sizeof(struct fw_version)); + memcpy(&(cbmem_fw->cse_version), &(cse_bp->fw_ver), sizeof(struct fw_version)); +#if CONFIG_SOC_INTEL_STORE_ISH_VERSION + /* Get current ISH firmware version from CSE */ + struct fw_version_resp resp; + if (cse_get_fpt_partition_info(FPT_PARTITION_NAME_ISHC, &resp) == CB_SUCCESS) { + /* + * Since cse version has been updated, ish version needs to be updated in + * both CMOS and CBMEM memory. + */ + set_cmos_ish_version(&(resp.manifest_data.version)); + memcpy(&(cbmem_fw->ish_version), + &(resp.manifest_data.version), vers_size); + } +#endif } else { /* Current running CSE version is same as previous stored CSE version */ - if (memcmp(&(cbmem_fw->cur_cse_fw_version), &(cse_bp->fw_ver), vers_size)) { + if (memcmp(&(cbmem_fw->cse_version), &(cse_bp->fw_ver), vers_size)) { /* * The CBMEM memory was reset during cold reboot, so the CSE version in * CBMEM needs to be updated to the version stored in CMOS. */ - memcpy(&(cbmem_fw->cur_cse_fw_version), &(cse_bp->fw_ver), sizeof(struct fw_version)); + memcpy(&(cbmem_fw->cse_version), &(cse_bp->fw_ver), sizeof(struct fw_version)); +#if CONFIG_SOC_INTEL_STORE_ISH_VERSION + struct fw_version cmos_ish_version; + get_cmos_ish_version(&cmos_ish_version); + /* + * The CBMEM memory was reset during cold reboot, so the ISH version in + * CBMEM needs to be updated to the version stored in CMOS. + */ + memcpy(&(cbmem_fw->ish_version), + &cmos_ish_version, vers_size); +#endif } } } @@ -1348,7 +1327,6 @@ if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) && soc_is_ish_partition_enabled()) { store_cse_fw_partition_version_info(); - store_ish_version(); } } diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index e23796a..568cb10 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -148,16 +148,12 @@ struct flash_partition_data manifest_data; }; -/* ISHC version */ -struct cse_fw_ish_version_info { - struct fw_version prev_cse_fw_version; - struct fw_version cur_ish_fw_version; -}; - /* CSE and ISHC version */ struct cse_fw_partition_info { - struct fw_version cur_cse_fw_version; - struct cse_fw_ish_version_info ish_partition_info; + struct fw_version cse_version; +#if CONFIG_SOC_INTEL_STORE_ISH_VERSION + struct fw_version ish_version; +#endif }; /* CSE RX and TX error status */ diff --git a/src/soc/intel/common/block/include/intelblocks/cse_cmos.h b/src/soc/intel/common/block/include/intelblocks/cse_cmos.h index 8026a19..1bc2b51 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse_cmos.h +++ b/src/soc/intel/common/block/include/intelblocks/cse_cmos.h @@ -1,14 +1,18 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ +/* SPDX-License-Identifier: GPL-2.0-only */ #ifndef SOC_INTEL_COMMON_BLOCK_CSE_CMOS_H #define SOC_INTEL_COMMON_BLOCK_CSE_CMOS_H - #include <intelblocks/cse.h> - /* Function to get the cse version stored in CMOS memory */ void get_cmos_cse_version(struct fw_version *cse_version); - /* Function to update the cse version stored in CMOS memory */ void set_cmos_cse_version(const struct fw_version *cse_version); +#if CONFIG_SOC_INTEL_STORE_ISH_VERSION +/* Function to get the ish version stored in CMOS memory */ +void get_cmos_ish_version(struct fw_version *ish_version); +/* Function to update the ish version stored in CMOS memory */ +void set_cmos_ish_version(const struct fw_version *ish_version); +#endif /* SOC_INTEL_STORE_ISH_VERSION */ + #endif /* SOC_INTEL_COMMON_BLOCK_CSE_CMOS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/75689?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2ea03298ae239c4597de9fd23a88c23f21e2f224 Gerrit-Change-Number: 75689 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/cmd/blk: Implement an API to get CSE version
by Dinesh Gehlot (Code Review) 07 Jun '23

07 Jun '23

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75688?usp=email ) Change subject: soc/intel/cmd/blk: Implement an API to get CSE version ...................................................................... soc/intel/cmd/blk: Implement an API to get CSE version This patch adds an API that will display the current CSE version. BUG=b:280722061 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I361d34589124ecf4f7cf70010ecc63d0cd8e6ddc --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/75688/1 diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 990e106..40489c7 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1213,6 +1213,21 @@ } } +void cse_get_version(void) +{ + if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION)) + return; + struct cse_fw_partition_info *version = cbmem_find(CBMEM_ID_CSE_PARTITION_VERSION); + if (version == NULL) + return; + + printk(BIOS_DEBUG, "CSE version: %d.%d.%d.%d\n", + version->cur_cse_fw_version.major, + version->cur_cse_fw_version.minor, + version->cur_cse_fw_version.hotfix, + version->cur_cse_fw_version.build); +} + #if ENV_RAMSTAGE /* diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 23a4490..e23796a 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -565,4 +565,7 @@ */ enum cb_err cse_get_fw_feature_state(uint32_t *feature_state); +/* Displays current CSE version */ +void cse_get_version(void); + #endif // SOC_INTEL_COMMON_CSE_H -- To view, visit https://review.coreboot.org/c/coreboot/+/75688?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I361d34589124ecf4f7cf70010ecc63d0cd8e6ddc Gerrit-Change-Number: 75688 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/cmd/blk/cse: Update CBMEM stored CSE version
by Dinesh Gehlot (Code Review) 07 Jun '23

07 Jun '23

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75687?usp=email ) Change subject: soc/intel/cmd/blk/cse: Update CBMEM stored CSE version ...................................................................... soc/intel/cmd/blk/cse: Update CBMEM stored CSE version This patch updates the CBMEM stored CSE version to the current version. BUG=b:280722061 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I97fc7a693bdb9dd67e711fd3d478b4e04f966e68 --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 16 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/75687/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 2b4ec7a..cf1df2b 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -1172,26 +1172,6 @@ timestamp_add_now(TS_CSE_FW_SYNC_END); } -/* - * Helper function that stores current CSE firmware version to CBMEM memory, - * except during recovery mode. - */ -static void store_cse_rw_fw_version(void) -{ - if (vboot_recovery_mode_enabled()) - return; - - struct get_bp_info_rsp cse_bp_info; - if (cse_get_bp_info(&cse_bp_info) != CB_SUCCESS) { - printk(BIOS_ERR, "cse_lite: Failed to get CSE boot partition info\n"); - return; - } - const struct cse_bp_entry *cse_bp = cse_get_bp_entry(RW, &cse_bp_info.bp_info); - struct cse_fw_partition_info *version; - version = cbmem_add(CBMEM_ID_CSE_PARTITION_VERSION, sizeof(*version)); - memcpy(&(version->cur_cse_fw_version), &(cse_bp->fw_ver), sizeof(struct fw_version)); -} - static enum cb_err send_get_fpt_partition_info_cmd(enum fpt_partition_id id, struct fw_version_resp *resp) { @@ -1323,10 +1303,13 @@ return; } const struct cse_bp_entry *cse_bp = cse_get_bp_entry(RW, &cse_bp_info.bp_info); + struct cse_fw_partition_info *cbmem_fw; size_t vers_size = sizeof(struct fw_version); struct fw_version prev_cse_fw_version; get_cmos_cse_version(&prev_cse_fw_version); + cbmem_fw = cbmem_add(CBMEM_ID_CSE_PARTITION_VERSION, sizeof(*cbmem_fw)); + /* * Compare if stored cse version (from the previous boot) is same as current * running cse version. @@ -1334,6 +1317,19 @@ if (memcmp(&prev_cse_fw_version, &(cse_bp->fw_ver), vers_size)) { /* write cse rw fw version to CMOS */ set_cmos_cse_version(&(cse_bp->fw_ver)); + + /* write cse rw fw version to CBMEM */ + memcpy(&(cbmem_fw->cur_cse_fw_version), &(cse_bp->fw_ver), sizeof(struct fw_version)); + } else { + /* Current running CSE version is same as previous stored CSE version */ + + if (memcmp(&(cbmem_fw->cur_cse_fw_version), &(cse_bp->fw_ver), vers_size)) { + /* + * The CBMEM memory was reset during cold reboot, so the CSE version in + * CBMEM needs to be updated to the version stored in CMOS. + */ + memcpy(&(cbmem_fw->cur_cse_fw_version), &(cse_bp->fw_ver), sizeof(struct fw_version)); + } } } @@ -1352,7 +1348,6 @@ if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) && soc_is_ish_partition_enabled()) { store_cse_fw_partition_version_info(); - store_cse_rw_fw_version(); store_ish_version(); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/75687?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97fc7a693bdb9dd67e711fd3d478b4e04f966e68 Gerrit-Change-Number: 75687 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/cmd/blk/cse: Cache CSE version in CMOS memory for cold boots
by Dinesh Gehlot (Code Review) 07 Jun '23

07 Jun '23

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75686?usp=email ) Change subject: soc/intel/cmd/blk/cse: Cache CSE version in CMOS memory for cold boots ...................................................................... soc/intel/cmd/blk/cse: Cache CSE version in CMOS memory for cold boots This patch stores the current CSE version in CMOS memory and provide API's to access the version. BUG=b:280722061 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I9c3ff2aa7cbc02750ff0256a16c02578f507db06 --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc A src/soc/intel/common/block/cse/cse_cmos.c M src/soc/intel/common/block/cse/cse_lite.c A src/soc/intel/common/block/include/intelblocks/cse_cmos.h 5 files changed, 202 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/75686/1 diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 26c623f..4426d5a 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -45,26 +45,34 @@ Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented) to make `HECI1` device disable using private configuration register (PCR) write. +config SOC_INTEL_PARTITION_FW_CMOS_OFFSET + int + default 72 + depends on SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION + help + This configuration option stores the starting offset of firmware partition versions in + CMOS memory. The offset should be byte aligned and must leave enough memory to store + required firmware partition versions. + config SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION bool default n depends on DRIVERS_INTEL_ISH help - This configuration option stores CSE FPT partitions' version in CBMEM memory. + This configuration option stores CSE FPT partitions' version in CMOS and CBMEM memory. This information can be used to identify the currently running firmware partition version. - The cost of sending HECI command to read the CSE FPT is significant (~200ms) - hence, the idea is to read the CSE RW version on every cold reset (to cover - the CSE update scenarios) and store into CBMEM to avoid the cost of resending - the HECI command in all consecutive warm boots. + The cost of sending HECI command to read the CSE FPT is significant (~200ms) hence, + the idea is to read the CSE RW version on CSE firmware update and store into CMOS to + avoid the cost of resending the HECI command in subsequent reboots. The CBMEM memory + stored version is updated with CMOS memory stored version on each cold reboot. - Later boot stages can just read the CBMEM ID to retrieve the ISH version if - required. + Later boot stages can just read the CBMEM ID to retrieve the ISH version if required. - Additionally, ensure this feature is platform specific hence, only enabled - for the platform that would like to store the ISH version into the CBMEM and - parse to perform some additional work. + Additionally, ensure this feature is platform specific hence, only enabled for the + platform that would like to store the ISH version into the CMOS and CBMEM and parse to + perform some additional work. config SOC_INTEL_CSE_SEND_EOP_EARLY bool "CSE send EOP early" diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 3e11279..679c4f7 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -1,13 +1,14 @@ ## SPDX-License-Identifier: GPL-2.0-only romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c romstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c ramstage-$(CONFIG_SOC_INTEL_CSE_HAVE_SPEC_SUPPORT) += cse_spec.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c -smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c ramstage-$(CONFIG_SOC_INTEL_CSE_SET_EOP) += cse_eop.c romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += telemetry.c +ramstage-$(CONFIG_SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) += cse_cmos.c +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += disable_heci.c ifeq ($(CONFIG_STITCH_ME_BIN),y) diff --git a/src/soc/intel/common/block/cse/cse_cmos.c b/src/soc/intel/common/block/cse/cse_cmos.c new file mode 100644 index 0000000..0f8c96a --- /dev/null +++ b/src/soc/intel/common/block/cse/cse_cmos.c @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <intelblocks/cse_cmos.h> +#include <ip_checksum.h> +#include <pc80/mc146818rtc.h> + +#define PARTITION_FW_SIGNATURE 0x46575054 /* 'FWPT' */ + +/* + * We need a region in CMOS to store the firmware versions. + * + * This can either be declared as part of the option + * table or statically defined in the board config. + */ +#if CONFIG(USE_OPTION_TABLE) +# include "option_table.h" + +#ifndef CMOS_VSTART_partition_fw +#error "The `ramtop` CMOS entry is missing, please add it to your cmos.layout." +#endif + +#if CMOS_VSTART_partition_fw % 8 != 0 +#error "The `partition firmware` CMOS entry needs to be byte aligned, check your cmos.layout." +#endif // CMOS_VSTART_partition_fw % 8 != 0 + +#if CMOS_VLEN_partition_fw != (24 * 8) +#error "The partition firmware entry needs to be 24 bytes long, check your cmos.layout." +#endif + +# define PARTITION_FW_CMOS_OFFSET (CMOS_VSTART_partition_fw >> 3) + +#else +# if (CONFIG_SOC_INTEL_PARTITION_FW_CMOS_OFFSET != 0) +# define PARTITION_FW_CMOS_OFFSET CONFIG_SOC_INTEL_PARTITION_FW_CMOS_OFFSET +# else +# error "Must configure CONFIG_SOC_INTEL_PARTITION_FW_CMOS_OFFSET" +# endif +#endif + +struct cse_fw_table { + uint32_t signature; + struct fw_version cse_version; + uint16_t checksum; +} __packed; + +/* Helper function to read firmware version from cmos memory. */ +static uint32_t read_cmos_partition_version(struct cse_fw_table *version) +{ + u8 i, *p, offset = PARTITION_FW_CMOS_OFFSET; + u16 csum; + + for (p = (u8 *)version, i = 0; i < sizeof(*version); i++, p++) + *p = cmos_read(offset + i); + + /* Verify signature */ + if (version->signature != PARTITION_FW_SIGNATURE) { + printk(BIOS_DEBUG, "cse firmware partition invalid signature\n"); + return -1; + } + + /* Verify checksum over signature and firmware versions only */ + csum = compute_ip_checksum(version, offsetof(struct cse_fw_table, checksum)); + + if (csum != version->checksum) { + printk(BIOS_DEBUG, "cse firmware partition checksum mismatch\n"); + return -1; + } + + return 0; +} + +/* Helper function to write firmware version to cmos memory. */ +static void write_cmos_partition_version(struct cse_fw_table *version) +{ + u8 i, *p, offset = PARTITION_FW_CMOS_OFFSET; + + /* Checksum over signature and firmware versions only */ + version->checksum = compute_ip_checksum(version, offsetof(struct cse_fw_table, checksum)); + + for (p = (u8 *)version, i = 0; i < sizeof(*version); i++, p++) + cmos_write(*p, offset + i); +} + +/* Helper function to initialize cmos firmware version. */ +static void init_cmos_partition_version(struct cse_fw_table *version) +{ + u8 i, *p, offset = PARTITION_FW_CMOS_OFFSET; + version->signature = PARTITION_FW_SIGNATURE; + memset(&version->cse_version, 0, sizeof(struct fw_version)); + version->checksum = compute_ip_checksum(version, offsetof(struct cse_fw_table, checksum)); + + for (p = (u8 *)version, i = 0; i < sizeof(*version); i++, p++) + cmos_write(*p, offset + i); +} + +/* API that allows users to read CSE version stored in CMOS memory. */ +void get_cmos_cse_version(struct fw_version *cse_version) +{ + struct cse_fw_table version; + if (read_cmos_partition_version(&version)) { + /* + * CMOS failed to read the CSE version. This may be because the firmware version at + * cmos has not yet been initialized. + */ + init_cmos_partition_version(&version); + } + memcpy(cse_version, &version.cse_version, sizeof(struct fw_version)); +} + +/* API that allows users to update CSE version stored in CMOS memory. */ +void set_cmos_cse_version(const struct fw_version *cse_version) +{ + struct cse_fw_table version; + if (read_cmos_partition_version(&version)) { + /* + * CMOS failed to read the CSE version. This may be because the firmware version at + * cmos has not yet been initialized. + */ + init_cmos_partition_version(&version); + } + memcpy(&version.cse_version, cse_version, sizeof(struct fw_version)); + write_cmos_partition_version(&version); +} diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 733f68b..2b4ec7a 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -10,6 +10,7 @@ #include <intelbasecode/debug_feature.h> #include <intelblocks/cse.h> #include <intelblocks/cse_layout.h> +#include <intelblocks/cse_cmos.h> #include <intelblocks/spi.h> #include <security/vboot/misc.h> #include <security/vboot/vboot_common.h> @@ -1295,6 +1296,47 @@ } } +/* + * Helper function that stores current CSE firmware version and ISH version to + * CMOS memory, except during recovery mode. Also updates the current ISH version + * in CBMEM memory. + * + * To get the current ISH version, it first checks if the CMOS stored ISH version + * needs to be updated. If it does, the system then reads the ISH version from the + * CSE FPT using the HECI command. + * + * ISH IP is patched after DRAM is available so GEN_GET_IMAGE_FW_VERSION command + * has to be issued to CSE after DRAM Init to get ISH FW Version. + * + */ +static void store_cse_fw_partition_version_info(void) +{ + if (vboot_recovery_mode_enabled()) + return; + + if (!ENV_RAMSTAGE) + return; + + struct get_bp_info_rsp cse_bp_info; + if (cse_get_bp_info(&cse_bp_info) != CB_SUCCESS) { + printk(BIOS_ERR, "cse_lite: Failed to get CSE boot partition info\n"); + return; + } + const struct cse_bp_entry *cse_bp = cse_get_bp_entry(RW, &cse_bp_info.bp_info); + size_t vers_size = sizeof(struct fw_version); + struct fw_version prev_cse_fw_version; + get_cmos_cse_version(&prev_cse_fw_version); + + /* + * Compare if stored cse version (from the previous boot) is same as current + * running cse version. + */ + if (memcmp(&prev_cse_fw_version, &(cse_bp->fw_ver), vers_size)) { + /* write cse rw fw version to CMOS */ + set_cmos_cse_version(&(cse_bp->fw_ver)); + } +} + static void ramstage_cse_misc_ops(void *unused) { if (acpi_get_sleep_type() == ACPI_S3) @@ -1309,6 +1351,7 @@ */ if (CONFIG(SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION) && soc_is_ish_partition_enabled()) { + store_cse_fw_partition_version_info(); store_cse_rw_fw_version(); store_ish_version(); } diff --git a/src/soc/intel/common/block/include/intelblocks/cse_cmos.h b/src/soc/intel/common/block/include/intelblocks/cse_cmos.h new file mode 100644 index 0000000..8026a19 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/cse_cmos.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_CSE_CMOS_H +#define SOC_INTEL_COMMON_BLOCK_CSE_CMOS_H + +#include <intelblocks/cse.h> + +/* Function to get the cse version stored in CMOS memory */ +void get_cmos_cse_version(struct fw_version *cse_version); + +/* Function to update the cse version stored in CMOS memory */ +void set_cmos_cse_version(const struct fw_version *cse_version); + +#endif /* SOC_INTEL_COMMON_BLOCK_CSE_CMOS_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/75686?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c3ff2aa7cbc02750ff0256a16c02578f507db06 Gerrit-Change-Number: 75686 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit June 2023