coreboot-gerrit June 2023

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[L] Change in coreboot[master]: mb/purism/librem_l1um_v2: Add support for Purism Librem L1UM v2
by Jonathon Hall (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Angel Pons, Felix Singer, Matt DeVillier, Michael Niewöhner, Tim Wawrzynczak. Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75090?usp=email ) Change subject: mb/purism/librem_l1um_v2: Add support for Purism Librem L1UM v2 ...................................................................... Patch Set 4: (14 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75090/comment/7f35c010_84897e91 : PS1, Line 24: - VGA BIOS > I did not know there was native VGA for AST2500! Thanks, I will look into this! Done File src/mainboard/purism/librem_l1um_v2/Kconfig: https://review.coreboot.org/c/coreboot/+/75090/comment/d7c8a30d_8805c38e : PS1, Line 3: select SOC_INTEL_COFFEELAKE : select BOARD_ROMSIZE_KB_32768 : select DRIVERS_UART_8250IO : select GENERATE_SMBIOS_TABLES : select HAVE_ACPI_TABLES : select IPMI_KCS : select MEMORY_MAPPED_TPM : select SOC_INTEL_CANNONLAKE_PCH_H : select SUPERIO_ASPEED_COMMON_PRE_RAM : select SUPERIO_ASPEED_AST2400 : select DRIVERS_ASPEED_AST_COMMON : select DRIVERS_ASPEED_AST2050 : select SUPERIO_NUVOTON_NCT6791D # This board has two SuperIOs : select DRIVERS_GENERIC_CBFS_SERIAL : select DRIVERS_USB_ACPI : select MAINBOARD_HAS_TPM2 : select SMBIOS_TYPE41_PROVIDED_BY_DEVTREE > Ack Done File src/mainboard/purism/librem_l1um_v2/board_info.txt: https://review.coreboot.org/c/coreboot/+/75090/comment/d25e26e0_e4d6ceac : PS1, Line 3: misc > Ack Done File src/mainboard/purism/librem_l1um_v2/bootblock.c: https://review.coreboot.org/c/coreboot/+/75090/comment/f755d15d_4502cee0 : PS1, Line 17: int64_t bmc_ready_elapsed = 0; > Ack Done File src/mainboard/purism/librem_l1um_v2/devicetree.cb: https://review.coreboot.org/c/coreboot/+/75090/comment/a291add2_c1624f7d : PS1, Line 3: register "SataSalpSupport" = "0" > Ack Done https://review.coreboot.org/c/coreboot/+/75090/comment/dbdd1cd9_021d205e : PS1, Line 4: register "satapwroptimize" = "1" > Ack Done https://review.coreboot.org/c/coreboot/+/75090/comment/92beb401_a1ac7b87 : PS1, Line 8: register "SataPortsEnable[0]" = "1" : register "SataPortsEnable[1]" = "1" : register "SataPortsEnable[2]" = "1" : register "SataPortsEnable[3]" = "1" : register "SataPortsEnable[4]" = "1" : register "SataPortsEnable[5]" = "1" : register "SataPortsEnable[6]" = "1" : register "SataPortsEnable[7]" = "1" : : register "SataPortsHotPlug[0]" = "1" : register "SataPortsHotPlug[1]" = "1" : register "SataPortsHotPlug[2]" = "1" : register "SataPortsHotPlug[3]" = "1" : register "SataPortsHotPlug[4]" = "1" : register "SataPortsHotPlug[5]" = "1" : register "SataPortsHotPlug[6]" = "1" : register "SataPortsHotPlug[7]" = "1" > Ack Done https://review.coreboot.org/c/coreboot/+/75090/comment/d2042f8c_7fbe8fbc : PS1, Line 26: register "PchHdaDspEnable" = "0" : register "PchHdaAudioLinkHda" = "0" > Ack Done https://review.coreboot.org/c/coreboot/+/75090/comment/1e2e022e_e23deea5 : PS1, Line 46: register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 front left : register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 front right : register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB_1_2 header port A : register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB_1_2 header port B : register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 rear top-right : register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 rear bottom-right : register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # BMC port A : register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 rear bottom-left : register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BMC port B (seems to be unused) : register "usb2_ports[10]" = "USB2_PORT_MID(OC_SKIP)" # USB 3.1 rear top-left : : register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 rear bottom-right : register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 rear top-right : register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 rear bottom-left : register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 rear top-left : register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 front left : register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 front right > Ack Done https://review.coreboot.org/c/coreboot/+/75090/comment/af3dd749_6a78c5d6 : PS1, Line 69: [PchSerialIoIndexI2C0] = PchSerialIoPci, : [PchSerialIoIndexI2C1] = PchSerialIoPci, > If `PchSerialIoDisabled` equalz 0, you can remove the entire array from the devicetree. It doesn't, 0 is `PchSerialIoNotInitialized`, so we need to keep this. https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… https://review.coreboot.org/c/coreboot/+/75090/comment/5e62fb48_e0441ff2 : PS1, Line 82: # This board has a lot of SuperIO LDNs with I/O BARs, the LPC generic : # I/O ranges must be configured manually. : register "gen1_dec" = "0x000c0ca1" # IPMI: ca0-caf : register "gen2_dec" = "0x007c0a01" # ASpeed SuperIO SWC and mailbox: a00-a7f : register "gen3_dec" = "0x00040291" # Nuvoton SuperIO HW monitor: 290-297 : : # AST2500 Super IO UART1 requires continuous mode : register "serirq_mode" = "SERIRQ_CONTINUOUS" > Ack Done https://review.coreboot.org/c/coreboot/+/75090/comment/e96b42ca_f9050d6c : PS1, Line 216: device pci 15.0 on end # I2C #0 : device pci 15.1 on end # I2C #1 > Ack Done https://review.coreboot.org/c/coreboot/+/75090/comment/9c662c17_ea504ab5 : PS1, Line 273: register "bmc_boot_timeout" = "90" > I just borrowed this value from ocp/tiogapass IIRC, the bootblock wait came much later in developmen […] Done File src/mainboard/purism/librem_l1um_v2/ramstage.c: https://review.coreboot.org/c/coreboot/+/75090/comment/1bdff424_14827fc1 : PS1, Line 30: BIOS_INFO > Ack Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75090?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I990f6024d65098a9553d7d1fe7f36614cc55ea19 Gerrit-Change-Number: 75090 Gerrit-PatchSet: 4 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Comment-Date: Wed, 07 Jun 2023 20:15:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Tim Wawrzynczak <inforichland(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2
by Jonathon Hall (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Felix Held, Paul Menzel. Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74363?usp=email ) Change subject: mb/purism/librem_cnl: Define CMOS layout for Librem Mini v1/v2 ...................................................................... Patch Set 10: (5 comments) Patchset: PS2: > Looks like if I enable HAVE_OPTION_TABLE, USE_OPTION_TABLE, and STATIC_OPTION_TABLE it is quite clos […] Done Patchset: PS10: Resolved the remaining comments since these changes were moved to the earlier patches, which are now merged File src/mainboard/purism/librem_cnl/Kconfig.name: https://review.coreboot.org/c/coreboot/+/74363/comment/ac5372da_6c69108c : PS9, Line 7: select HAVE_CMOS_DEFAULT > Ack Done File src/mainboard/purism/librem_cnl/variants/librem_mini/mainboard.c: https://review.coreboot.org/c/coreboot/+/74363/comment/5b06269b_599d38e5 : PS2, Line 7: /* Create a cbfs file called 'board_settings' to configure settings: : * Byte 0: EC automatic power on (EC_POWER_ON_*) : */ > Please use the recommended multi-line comment styles from the coding style. Done https://review.coreboot.org/c/coreboot/+/74363/comment/48cec385_6a70f135 : PS2, Line 21: uint8_t ec_power_on = 0; > It's reading a 1-byte field from the board settings file with memcpy. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74363?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0a4ea02d71f6f99e344484726a629e0552e4941 Gerrit-Change-Number: 74363 Gerrit-PatchSet: 10 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 07 Jun 2023 20:07:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/var/redrix: Add new GFX device with custom _PLD
by Nick Vaccaro (Code Review) 07 Jun '23

07 Jun '23

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75509?usp=email ) Change subject: mb/google/brya/var/redrix: Add new GFX device with custom _PLD ...................................................................... mb/google/brya/var/redrix: Add new GFX device with custom _PLD Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot BRANCH=firmware-brya-14505.B Change-Id: Ia083617c58d6b7ebc108e07e29a1c8061580eae5 Signed-off-by: Won Chung <wonchung(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75509 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb 2 files changed, 56 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index f8619c9..cdea071 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -98,6 +98,7 @@ device ref igpu on chip drivers/gfx/generic register "device_count" = "1" + # DDIA for eDP register "device[0].name" = ""LCD"" # Use ChromeOS privacy screen _HID register "device[0].hid" = ""GOOG0010"" @@ -109,6 +110,33 @@ probe EPS PRIVACY_SCREEN end end + chip drivers/gfx/generic + register "device_count" = "1" + # DDIA for eDP + register "device[0].name" = ""LCD"" + device generic 0 on + probe EPS PRIVACY_SCREEN_ABSENT + end + end + chip drivers/gfx/generic + register "device_count" = "5" + # eDP already added, so skipped + # DDIB for HDMI + register "device[0].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[1].name" = ""DD02"" + register "device[1].use_pld" = "true" + register "device[1].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) unused + register "device[2].name" = ""DD03"" + # TCP2 (DP-3) for port C2 + register "device[3].name" = ""DD04"" + register "device[3].use_pld" = "true" + register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + # TCP3 (DP-4) unused + register "device[4].name" = ""DD05"" + device generic 0 on end + end end # Integrated Graphics Device device ref dtt on chip drivers/intel/dptf diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 81a808f..37ddbc7 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -84,6 +84,7 @@ device ref igpu on chip drivers/gfx/generic register "device_count" = "1" + # DDIA for eDP register "device[0].name" = ""LCD"" # Use ChromeOS privacy screen _HID register "device[0].hid" = ""GOOG0010"" @@ -95,6 +96,33 @@ probe EPS PRIVACY_SCREEN end end + chip drivers/gfx/generic + register "device_count" = "1" + # DDIA for eDP + register "device[0].name" = ""LCD"" + device generic 0 on + probe EPS PRIVACY_SCREEN_ABSENT + end + end + chip drivers/gfx/generic + register "device_count" = "5" + # eDP already added, so skipped + # DDIB for HDMI + register "device[0].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[1].name" = ""DD02"" + register "device[1].use_pld" = "true" + register "device[1].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) unused + register "device[2].name" = ""DD03"" + # TCP2 (DP-3) for port C2 + register "device[3].name" = ""DD04"" + register "device[3].use_pld" = "true" + register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + # TCP3 (DP-4) unused + register "device[4].name" = ""DD05"" + device generic 0 on end + end end # Integrated Graphics Device device ref dtt on chip drivers/intel/dptf -- To view, visit https://review.coreboot.org/c/coreboot/+/75509?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia083617c58d6b7ebc108e07e29a1c8061580eae5 Gerrit-Change-Number: 75509 Gerrit-PatchSet: 5 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/brya/var/redrix: Add new GFX device with custom _PLD
by Nick Vaccaro (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Tarun Tuli, Won Chung. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75509?usp=email ) Change subject: mb/google/brya/var/redrix: Add new GFX device with custom _PLD ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75509?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia083617c58d6b7ebc108e07e29a1c8061580eae5 Gerrit-Change-Number: 75509 Gerrit-PatchSet: 4 Gerrit-Owner: Won Chung <wonchung(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Won Chung <wonchung(a)google.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 20:06:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd: add ops xhci_pci_ops to XHCI controllers in devicetree
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Felix Held, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier, Raul Rangel. Hello Fred Reitberger, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier, Raul Rangel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75713?usp=email to look at the new patch set (#2). Change subject: soc/amd: add ops xhci_pci_ops to XHCI controllers in devicetree ...................................................................... soc/amd: add ops xhci_pci_ops to XHCI controllers in devicetree Instead of adding the new PCI IDs of the XHCI controllers in every new chip generation to the pci_xhci driver, bind the driver to the internal PCI devices of the XHCI controllers via the device ops statement in the chipset devicetree. The PCI device function of the XHCI2 controller in Mendocino can be either a dummy device or the XHCI controller, so the device ops are attached to that device in the mainboard devicetree instead. The Glinda code is right now just a copy of the Mendocino code, so it'll change in the future, but for consistency the equivalent changes to those in Mendocino are applied there too. Since the device ops are now attached to the devices via the static devicetree entry, also remove both the xhci_pci_driver struct and the amd_pci_device_ids array from drivers/usb/pci_xhci/pci_xhci.c. TEST=SSDT entries for the XHCI controllers are still generated on Mandolin. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I9c455002c6d2aac576fe24eee0c31744b4507bb0 --- M src/drivers/usb/pci_xhci/pci_xhci.c M src/mainboard/amd/birman/devicetree_glinda.cb M src/mainboard/amd/chausie/devicetree.cb M src/mainboard/google/skyrim/variants/baseboard/devicetree.cb M src/soc/amd/cezanne/chipset.cb M src/soc/amd/glinda/chipset.cb M src/soc/amd/mendocino/chipset_mendocino.cb M src/soc/amd/mendocino/chipset_rembrandt.cb M src/soc/amd/picasso/chipset.cb 9 files changed, 20 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/75713/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75713?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c455002c6d2aac576fe24eee0c31744b4507bb0 Gerrit-Change-Number: 75713 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[NoOp] Change in blobs[master]: mb/google/skyrim/var/markarth: Add custom ABL
by Jon Murphy (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Karthik Ramasubramanian, Tim Van Patten. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/75693?usp=email ) Change subject: mb/google/skyrim/var/markarth: Add custom ABL ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Ensure that the submodule is updated after this merges -- To view, visit https://review.coreboot.org/c/blobs/+/75693?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I3e48a16e0a46b2948260fd427b76a2ed88303996 Gerrit-Change-Number: 75693 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 19:34:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/markarth: Add amdfw.cfg
by Jon Murphy (Code Review) 07 Jun '23

07 Jun '23

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75694?usp=email ) Change subject: mb/google/skyrim/var/markarth: Add amdfw.cfg ...................................................................... mb/google/skyrim/var/markarth: Add amdfw.cfg Copy the baseboard amdfw.cfg and apply markarth specific customizations - eg ABL. BUG=b:281614369 BRANCH=skyrim TEST=Build Skyrim and Markarth BIOS image. Ensure that the right ABL binary is getting picked up. Change-Id: I9237c5dddda25da84e2578495a3b5ed7983d6e63 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- M src/mainboard/google/skyrim/Kconfig A src/mainboard/google/skyrim/variants/markarth/amdfw.cfg 2 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/75694/1 diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index 14ef71b..fd151ad 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -62,6 +62,7 @@ config AMDFW_CONFIG_FILE string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/amdfw.cfg" if BOARD_GOOGLE_MARKARTH default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/amdfw.cfg" help Custom firmware list excluding the fwTPM binary. diff --git a/src/mainboard/google/skyrim/variants/markarth/amdfw.cfg b/src/mainboard/google/skyrim/variants/markarth/amdfw.cfg new file mode 100644 index 0000000..68efe7e --- /dev/null +++ b/src/mainboard/google/skyrim/variants/markarth/amdfw.cfg @@ -0,0 +1,39 @@ +# PSP fw config file + +FIRMWARE_LOCATION 3rdparty/amd_blobs/mendocino/PSP +SOC_NAME Mendocino + +# type file +# PSP +AMD_PUBKEY_FILE TypeId0x00_MendocinoRoot.tkn +PSPBTLDR_AB_STAGE1_FILE TypeId0x01_PspBootLoader1_MDN.sbin +PSPSECUREOS_FILE TypeId0x02_PspOS_MDN.sbin +PSP_SMUFW1_SUB0_FILE TypeId0x08_SmuFirmware_MDN.sbin +PSPSECUREDEBUG_FILE TypeId0x09_Mendocino-SDU.stkn +PSP_SMUFW2_SUB0_FILE TypeId0x12_SmuFirmware2_MDN.sbin +PSP_SEC_DEBUG_FILE TypeId0x13_PspEarlyUnlock_MDN.sbin +PSP_HW_IPCFG_FILE_SUB0 TypeId0x20_HwIpCfg_MDN.sbin +PSP_IKEK_FILE TypeId0x21_PspiKek_MDN.bin +PSP_SECG0_FILE TypeId0x24_SecPolicy_MDN.sbin +AMD_DRIVER_ENTRIES TypeId0x28_PspSystemDriver_MDN.sbin +PSP_S0I3_FILE TypeId0x2D_AgesaRunTimeDrv_MDN.sbin +PSP_ABL0_FILE 3rdparty/blobs/mainboard/google/skyrim/variants/markarth/TypeId0x30_AgesaBootloaderU_MDN_LPDDR5.sbin +VBIOS_BTLOADER_FILE TypeId0x3C_VbiosBootLoader_MDN.sbin +SECURE_POLICY_L1_FILE TypeId0x45_SecPolicytOS_MDN.sbin +UNIFIEDUSB_FILE TypeId0x44_UnifiedUsb_MDN.sbin +KEYDBBL_FILE TypeId0x50_KeyDbBl_MDN.sbin +KEYDB_TOS_FILE TypeId0x51_KeyDbTos_MDN.sbin +SPL_TABLE_FILE TypeId0x55_SplTableBl_MDN.sbin +MSMU_FILE TypeId0x5A_Msmu_MDN.sbin +SPIROM_CONFIG_FILE TypeId0x5C_SpiRomConfig_MDN_Dual66.sbin +DMCUB_FILE TypeId0x71_DmcubFw_MDN.sbin +PSPBTLDR_AB_FILE TypeId0x73_PspBootLoader2_MDN.sbin +TA_IKEK_FILE TypeId0x8D_IkekTa_MDN.bin +PSP_MP2FW0_FILE 3rdparty/blobs/mainboard/google/skyrim/TypeId0x25_Mp2Fw_MDN_AD03.sbin + +# BDT +PSP_PMUI_FILE_SUB0_INS1 TypeId0x64_Appb_MDN_Lpddr5Imem1.csbin +PSP_PMUD_FILE_SUB0_INS1 TypeId0x65_Appb_MDN_Lpddr5Dmem1.csbin +PSP_PMUI_FILE_SUB0_INS2 TypeId0x64_Appb_MDN_Lpddr5Imem2.csbin +PSP_PMUD_FILE_SUB0_INS2 TypeId0x65_Appb_MDN_Lpddr5Dmem2.csbin +PSP_MP2CFG_FILE 3rdparty/blobs/mainboard/google/skyrim/TypeId0x6A_ConfigFile.sbin -- To view, visit https://review.coreboot.org/c/coreboot/+/75694?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9237c5dddda25da84e2578495a3b5ed7983d6e63 Gerrit-Change-Number: 75694 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newchange

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[NoOp] Change in blobs[master]: mb/google/skyrim/var/markarth: Add custom ABL
by Jon Murphy (Code Review) 07 Jun '23

07 Jun '23

Jon Murphy has uploaded this change for review. ( https://review.coreboot.org/c/blobs/+/75693?usp=email ) Change subject: mb/google/skyrim/var/markarth: Add custom ABL ...................................................................... mb/google/skyrim/var/markarth: Add custom ABL Add custom ABL to resolve boot issues during reset. BUG=b:281614369 TEST=Build Skyrim and Markarth BIOS image. Ensure that the right ABL binary is getting picked up. Change-Id: I3e48a16e0a46b2948260fd427b76a2ed88303996 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> --- A mainboard/google/skyrim/variants/markarth/TypeId0x30_AgesaBootloaderU_MDN_LPDDR5.sbin 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/93/75693/1 diff --git a/mainboard/google/skyrim/variants/markarth/TypeId0x30_AgesaBootloaderU_MDN_LPDDR5.sbin b/mainboard/google/skyrim/variants/markarth/TypeId0x30_AgesaBootloaderU_MDN_LPDDR5.sbin new file mode 100644 index 0000000..1dd1b30 --- /dev/null +++ b/mainboard/google/skyrim/variants/markarth/TypeId0x30_AgesaBootloaderU_MDN_LPDDR5.sbin Binary files differ -- To view, visit https://review.coreboot.org/c/blobs/+/75693?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: I3e48a16e0a46b2948260fd427b76a2ed88303996 Gerrit-Change-Number: 75693 Gerrit-PatchSet: 1 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd: add ops xhci_pci_ops to XHCI controllers in devicetree
by Fred Reitberger (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Felix Held, Jason Glenesk, Jason Nien, Martin Roth, Matt DeVillier, Raul Rangel. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75713?usp=email ) Change subject: soc/amd: add ops xhci_pci_ops to XHCI controllers in devicetree ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75713?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c455002c6d2aac576fe24eee0c31744b4507bb0 Gerrit-Change-Number: 75713 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 07 Jun 2023 19:20:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/phoenix: Hook up xhci ops in chipset.cb
by Fred Reitberger (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Eric Lai, Jason Glenesk, Jon Murphy, Martin L Roth, Martin Roth, Matt DeVillier, Paul Menzel. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75659?usp=email ) Change subject: soc/amd/phoenix: Hook up xhci ops in chipset.cb ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75659?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib59874948725966b04b54def3f6de463afeda709 Gerrit-Change-Number: 75659 Gerrit-PatchSet: 6 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 19:18:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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