coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: mb/google/brya/variants/hades: Abort power on sequence if any rails P...
by Tarun Tuli (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Eran Mitrani, Eric Lai. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75534?usp=email ) Change subject: mb/google/brya/variants/hades: Abort power on sequence if any rails PG signal fails to assert ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/75534?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0865e6bdb5db1815ad5509306637308e98c15d7 Gerrit-Change-Number: 75534 Gerrit-PatchSet: 2 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 21:24:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/brya/acpi: NV12 enable signal should be off on GCOFF entry
by Tarun Tuli (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Eran Mitrani, Eric Lai. Hello Eran Mitrani, Eric Lai, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75533?usp=email to look at the new patch set (#4). Change subject: mb/google/brya/acpi: NV12 enable signal should be off on GCOFF entry ...................................................................... mb/google/brya/acpi: NV12 enable signal should be off on GCOFF entry Properly shutdown NV12 rail in the off sequence (current implementation leaves it asserted). Change-Id: I7d338fc4a96f119617aff558413a5a9ac44c27d7 Signed-off-by: Tarun Tuli <taruntuli(a)google.com> --- M src/mainboard/google/brya/acpi/power.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/75533/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/75533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d338fc4a96f119617aff558413a5a9ac44c27d7 Gerrit-Change-Number: 75533 Gerrit-PatchSet: 4 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/google/brya/acpi: NV12 enable signal should be off on GCOFF entry
by Tarun Tuli (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Eran Mitrani, Eric Lai. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75533?usp=email ) Change subject: mb/google/brya/acpi: NV12 enable signal should be off on GCOFF entry ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/75533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d338fc4a96f119617aff558413a5a9ac44c27d7 Gerrit-Change-Number: 75533 Gerrit-PatchSet: 3 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 21:16:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [TEST ONLY] add VPRO features control by fw config
by Wonkyu Kim (Code Review) 07 Jun '23

07 Jun '23

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75714?usp=email ) Change subject: [TEST ONLY] add VPRO features control by fw config ...................................................................... [TEST ONLY] add VPRO features control by fw config Define keylocker, tme fw_config bits(24-25) field KEYLOCKER 24 option KEYLOCKER_EN 0 option KEYLOCKER_DIS 1 end field TME 25 option TME_EN 0 option TME_DIS 1 end Vpro features Disable: 3XXXXXX (XXXXXX is existing fw_config value) Vpro features Enable : XXXXXX (XXXXXX is existing fw_config value) ex)proto1 SKU1 fw_config: 0x1561 0x1561 => Vpro features(keylocker/tme) are enabled 0x3001561 => Vpro features(keylocker/tme) are disabled localhost ~ # cbmem -c | grep fw_config ... [DEBUG] keylocker is disabled by fw_config ... [DEBUG] TME is disabled by fw config How to read FW config From EC console, type "cbi" to read FW config ex) 23-05-17 23:33:33.229 ec:~$ cbi ... 23-05-17 23:41:33.248 FW_CONFIG: 5473 (0x1561) ... How to write FW config From EC consone, type "cbi set 6 <FW config value> 4 ex) 23-05-17 23:43:42.320 ec:~$ cbi set 6 0x3001561 4 Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: I746ba80279dc69d06ac9e06bfeae068e31d23694 --- M src/mainboard/google/rex/variants/rex0/Makefile.inc A src/mainboard/google/rex/variants/rex0/cpulib.c M src/mainboard/google/rex/variants/rex0/overridetree.cb M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h 5 files changed, 72 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/75714/1 diff --git a/src/mainboard/google/rex/variants/rex0/Makefile.inc b/src/mainboard/google/rex/variants/rex0/Makefile.inc index cdbf407..63a665c 100644 --- a/src/mainboard/google/rex/variants/rex0/Makefile.inc +++ b/src/mainboard/google/rex/variants/rex0/Makefile.inc @@ -3,3 +3,6 @@ ramstage-y += gpio.c ramstage-y += variant.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c diff --git a/src/mainboard/google/rex/variants/rex0/cpulib.c b/src/mainboard/google/rex/variants/rex0/cpulib.c new file mode 100644 index 0000000..cf0edcd --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0/cpulib.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <intelblocks/cpulib.h> +#include <fw_config.h> + +/* override function according to fw_config */ +bool is_tme_enabled(void) +{ + if(fw_config_probe(FW_CONFIG(TME, TME_DIS))) { + printk(BIOS_DEBUG, "TME is disabled by fw_config\n"); + return false; + } + return true; +} + +/* override function according to fw_config */ +bool is_keylocker_enabled(void) +{ + if(fw_config_probe(FW_CONFIG(KEYLOCKER, KEYLOCKER_DIS))) { + printk(BIOS_DEBUG, "keylocker is disabled by fw_config\n"); + return false; + } + return true; +} diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 4619cba..ca49696 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -54,6 +54,14 @@ option ISH_DISABLE 0 option ISH_ENABLE 1 end + field KEYLOCKER 24 + option KEYLOCKER_EN 0 + option KEYLOCKER_DIS 1 + end + field TME 25 + option TME_EN 0 + option TME_DIS 1 + end end chip soc/intel/meteorlake diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index c317e05..c29061f 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -405,9 +405,19 @@ return ((cpuid_regs.ecx & KEYLOCKER_SUPPORTED) && (msr.lo & MTRR_CAP_PRMRR)); } +/* + * This weak function can be overried for early SOC testing purpose. + * The functions can be implemented with fw_config or menu + * to enable/disable the features. + */ +bool __weak is_keylocker_enabled(void) +{ + return true; +} + static bool is_keylocker_configured_and_supported(void) { - return CONFIG(INTEL_KEYLOCKER) && is_keylocker_supported(); + return CONFIG(INTEL_KEYLOCKER) && is_keylocker_supported() && is_keylocker_enabled(); } static bool check_prm_features_enabled(void) @@ -485,13 +495,23 @@ sync_core_prmrr(); } +/* + * This weak function can be overried for early SOC testing purpose. + * The functions can be implemented with fw_config or menu + * to enable/disable the features. + */ +bool __weak is_tme_enabled(void) +{ + return true; +} + bool is_tme_supported(void) { struct cpuid_result cpuid_regs; /* ECX[13] is feature capability */ cpuid_regs = cpuid_ext(CPUID_STRUCT_EXTENDED_FEATURE_FLAGS, 0x0); - return (cpuid_regs.ecx & TME_SUPPORTED); + return (cpuid_regs.ecx & TME_SUPPORTED) && is_tme_enabled(); } void set_tme_core_activate(void) diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index cbc9e44..f33b3f5 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -225,4 +225,18 @@ */ void disable_three_strike_error(void); +/* + * This weak function can be overried for early SOC testing purpose. + * The functions can be implemented with fw_config or menu + * to enable/disable the features. + */ +bool is_tme_enabled(void); + +/* + * This weak function can be overried for early SOC testing purpose. + * The functions can be implemented with fw_config or menu + * to enable/disable the features. + */ +bool is_keylocker_enabled(void); + #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/75714?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I746ba80279dc69d06ac9e06bfeae068e31d23694 Gerrit-Change-Number: 75714 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: util: Use common ARRAY_SIZE define
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74474?usp=email ) Change subject: util: Use common ARRAY_SIZE define ...................................................................... Patch Set 4: (1 comment) Patchset: PS2: > other parts of src/commonlib being used in util/ is another very strong argument for this. […] had a brief discussion about this in the last coreboot leadership meeting and the idea of commonlib was about being able to easily share header files between src/ and the utilities in util/, so the utils should use commonlib instead of having their own definitions. at least now i know for sure -- To view, visit https://review.coreboot.org/c/coreboot/+/74474?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29b776586b4f0548d4026b2ac77095791fc9f3a3 Gerrit-Change-Number: 74474 Gerrit-PatchSet: 4 Gerrit-Owner: Konrad Adamczyk <konrada(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Grzegorz Bernacki Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 21:06:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Konrad Adamczyk <konrada(a)google.com> Comment-In-Reply-To: Robert Zieba <robertzieba(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/phoenix/Kconfig: temporary drop VGA_BIOS_FILE
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75484?usp=email ) Change subject: soc/amd/phoenix/Kconfig: temporary drop VGA_BIOS_FILE ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/phoenix/Kconfig: https://review.coreboot.org/c/coreboot/+/75484/comment/52ced224_a4e654bf : PS1, Line 257: config VGA_BIOS_FILE > I'd leave the entry and add a TODO so it doesn't get forgotten Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75484?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbc6cbe1e371d8d247f86555a5361ed237897dea Gerrit-Change-Number: 75484 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 20:53:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: soc/amd/phoenix/Kconfig: temporary drop VGA_BIOS_FILE
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75484?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/phoenix/Kconfig: temporary drop VGA_BIOS_FILE ...................................................................... soc/amd/phoenix/Kconfig: temporary drop VGA_BIOS_FILE The file VGA_BIOS_FILE points to is right now the Mendocino VBIOS. Since the default value probably shouldn't point to a location in site-local, drop this for now, but leave a TODO to put that back once the correct VBIOS files are available in 3rdparty/amd_blobs. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifbc6cbe1e371d8d247f86555a5361ed237897dea --- M src/soc/amd/phoenix/Kconfig 1 file changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/75484/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75484?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbc6cbe1e371d8d247f86555a5361ed237897dea Gerrit-Change-Number: 75484 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/*/root_complex: reserve IOMMU MMIO area
by Arthur Heymans (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75611?usp=email ) Change subject: soc/amd/*/root_complex: reserve IOMMU MMIO area ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File src/soc/amd/common/block/include/amdblocks/iomap.h: https://review.coreboot.org/c/coreboot/+/75611/comment/76e69bfd_3955eb19 : PS4, Line 15: 0xfd00000000 That's typically where the full SPI flash is mapped too right (ROM3 register)? Would it make sense to read that back from hardware rather than hardcoding it? I was told it's a setting in APCB. -- To view, visit https://review.coreboot.org/c/coreboot/+/75611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a8150873cb019ca1d903ed269e18d6f9fabb871 Gerrit-Change-Number: 75611 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 07 Jun 2023 20:39:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/*/root_complex: reserve IOMMU MMIO area
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75611?usp=email ) Change subject: soc/amd/*/root_complex: reserve IOMMU MMIO area ...................................................................... Patch Set 4: (1 comment) File src/soc/amd/picasso/root_complex.c: https://review.coreboot.org/c/coreboot/+/75611/comment/5762f93b_3edcdf19 : PS3, Line 151: 0xfd00000000 > i'll push an update that has defines for this and adds the reservation to all socs. […] added defines for this and added the mmio reservation to all socs from picasso on -- To view, visit https://review.coreboot.org/c/coreboot/+/75611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a8150873cb019ca1d903ed269e18d6f9fabb871 Gerrit-Change-Number: 75611 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 20:26:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/*/root_complex: reserve IOMMU MMIO area
by Felix Held (Code Review) 07 Jun '23

07 Jun '23

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75611?usp=email ) Change subject: soc/amd/*/root_complex: reserve IOMMU MMIO area ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/75611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5a8150873cb019ca1d903ed269e18d6f9fabb871 Gerrit-Change-Number: 75611 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 07 Jun 2023 20:25:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit June 2023