Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75533?usp=email )
Change subject: mb/google/brya/acpi: Turn NV12 enable signal off on GCOFF entry
......................................................................
mb/google/brya/acpi: Turn NV12 enable signal off on GCOFF entry
Properly shutdown NV12 rail in the off sequence (current
implementation leaves it asserted).
BUG=b:286287940
TEST=NV12 now shuts down on GCOFF entry
Change-Id: I7d338fc4a96f119617aff558413a5a9ac44c27d7
Signed-off-by: Tarun Tuli <taruntuli(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75533
Reviewed-by: Eran Mitrani <mitrani(a)google.com>
Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/mainboard/google/brya/acpi/power.asl
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Eran Mitrani: Looks good to me, approved
build bot (Jenkins): Verified
Eric Lai: Looks good to me, approved
Nick Vaccaro: Looks good to me, approved
diff --git a/src/mainboard/google/brya/acpi/power.asl b/src/mainboard/google/brya/acpi/power.asl
index c4a8495..5638e18 100644
--- a/src/mainboard/google/brya/acpi/power.asl
+++ b/src/mainboard/google/brya/acpi/power.asl
@@ -312,7 +312,7 @@
GPPL (GPIO_1V8_PG, 0, 20)
/* Ramp down 1.2V rail on boards with support */
- STXS (GPIO_NV12_PWR_EN)
+ CTXS (GPIO_NV12_PWR_EN)
GPPL (GPIO_NV12_PG, 0, 5)
GCOT = Timer
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Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75533?usp=email )
Change subject: mb/google/brya/acpi: Turn NV12 enable signal off on GCOFF entry
......................................................................
Patch Set 6: Code-Review+2
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Change subject: (not tested)payloads/U-Boot: Upgrade from U-Boot "v2021.07" to "v2023.04"
......................................................................
Patch Set 6: Code-Review+1
(1 comment)
Patchset:
PS6:
> Would be good to merge, can you test it?
I mainly requested testing because there are almost 2 years in between and I am not familiar well enough with U-Boot to just approve this.
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Change subject: mb/google/rex/rex0: Enable Fast Vmode for rex0
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> as per fsp upd description, if icclimit is set to 0 then reactive protection feature remains disable.
>
> ```
> A value of 0 corresponds to feature disabled (no reactive protection). This value represents the current threshold where the VR would initiate reactive protection if Fast Vmode is enabled.
> ```
>
> we need to perform icclimit override as well as below
>
> VccCORE 72
> VccSA 35
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Hello Eric Lai, Karthik Ramasubramanian, Martin Roth, Tim Van Patten, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75700?usp=email
to look at the new patch set (#4).
Change subject: mb/google/myst: Update PCIE_RST_L drive
......................................................................
mb/google/myst: Update PCIE_RST_L drive
PCIE_RST_L is attached to a pull down, change the init to output low.
BUG=None
TEST=Boot to OS
Change-Id: I3f7a548a33eb18327139f033d7c0d6a1843f1639
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
---
M src/mainboard/google/myst/variants/baseboard/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/75700/4
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Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75700?usp=email )
Change subject: mb/google/myst: Update PCIE_RST_L drive
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/75700/comment/96dbabf1_4c9ea01c :
PS2, Line 55: PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
> It was an intended change, but leaving it as an output low is likely equivalent. […]
Done
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Change subject: mb/google/myst: Update PCIE_RST_L drive
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/75700/comment/7d1fccbb_767e7830 :
PS2, Line 55: PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE),
> maybe also give the reason why in romstage is output here is NF.
It was an intended change, but leaving it as an output low is likely equivalent. I can put that back.
I don't understand your second comment. This is the only place that we modify GPIO_27. If you look at the schematic, it's actually just attached to an external pull down
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