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Change subject: TPM: Add option to read PCRs after TPM initialization
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Change subject: facebook/watson: Adjust resource allocation for PCIe bridge
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Change subject: security/vboot: Replace all region device and map functions
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Change subject: soc|vc/amd/phoenix: Prepare for PSP verstage
......................................................................
Patch Set 3:
(2 comments)
File src/soc/amd/phoenix/psp_verstage/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/75584/comment/6c7f627e_7f12a510 :
PS1, Line 3: ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y)
> vboot_separate_verstage can also run on the x86, and we don't want this included there. […]
Done. Kept it similar to Mendocino. The only difference is this is including src/vendorcode/amd/fsp/common/include
File src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_errorcodes_public.h:
https://review.coreboot.org/c/coreboot/+/75584/comment/2e5a211d_fba9ef17 :
PS1, Line 1: *
> Use the version in vendorcode/amd/fsp/common/bl_uapp instead?
Done
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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75584?usp=email
to look at the new patch set (#3).
Change subject: soc|vc/amd/phoenix: Prepare for PSP verstage
......................................................................
soc|vc/amd/phoenix: Prepare for PSP verstage
Update all the required sources to lay the ground work to enable PSP
verstage.
BUG=b:284984667
TEST=Build Myst BIOS image with PSP verstage enabled.
Change-Id: I6fbb1f835ac2ad6ff47f843321e1bd380af7ce33
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/phoenix/include/soc/psp_verstage_addr.h
M src/soc/amd/phoenix/psp_verstage/Makefile.inc
M src/soc/amd/phoenix/psp_verstage/chipset.c
M src/soc/amd/phoenix/psp_verstage/svc.c
M src/soc/amd/phoenix/psp_verstage/svc.h
M src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h
6 files changed, 117 insertions(+), 23 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/75584/3
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Change subject: payloads/external/seabios: Scan all PCI domains on Xeon-SP platforms
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/49461/comment/e4a670ce_cfab8ab9 :
PS2, Line 7: PCI domains
> There is no such thing as a "PCI domain". The term is sometimes wrongly […]
Done
https://review.coreboot.org/c/coreboot/+/49461/comment/0e03262c_8593671b :
PS2, Line 10: domain 0
> `the first host bridge`?
Done
File payloads/external/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/49461/comment/6d565c45_20c67511 :
PS2, Line 117: domains
> I tried to explain this below. It controls the maximum number of […]
Done
https://review.coreboot.org/c/coreboot/+/49461/comment/b88e9883_3dd562db :
PS2, Line 118: $(CBFSTOOL) $< add-int -i 255 -n etc/extra-pci-roots
> Can you add "$(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/extra-pci-roots 2>/dev/null)" […]
Christian, are you interested in fixing this one? Or should we abandon?
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Change subject: payloads/external/seabios: Scan all PCI domains on Xeon-SP platforms
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File payloads/external/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/49461/comment/7f375e87_951c6adf :
PS2, Line 118: 255
> > On my Xeon-SP there are devices on bus 0xff. […]
Given that this is not enabled on Thinkpads, it is somewhat irrelevant. If you want to add support for your Thinkpad, this should be done in an incremental patch.
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Change subject: util/inteltool: Add support for GLK
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Should this be abandoned?
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Hello Felix Held, Fred Reitberger, Jason Glenesk, Jon Murphy, Matt DeVillier, Raul Rangel, Tim Van Patten, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75584?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Code-Review+1 by Tim Van Patten, Verified+1 by build bot (Jenkins)
Change subject: soc|vc/amd/phoenix: Prepare for PSP verstage
......................................................................
soc|vc/amd/phoenix: Prepare for PSP verstage
Update all the required sources to lay the ground work to enable PSP
verstage.
BUG=b:284984667
TEST=Build Myst BIOS image with PSP verstage enabled.
Change-Id: I6fbb1f835ac2ad6ff47f843321e1bd380af7ce33
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/amd/phoenix/include/soc/psp_verstage_addr.h
M src/soc/amd/phoenix/psp_verstage/Makefile.inc
M src/soc/amd/phoenix/psp_verstage/chipset.c
M src/soc/amd/phoenix/psp_verstage/svc.c
M src/soc/amd/phoenix/psp_verstage/svc.h
M src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h
6 files changed, 117 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/75584/2
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