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Change subject: drivers/pc80/pc/i8254.c: Initialize timer 1 in mode 2
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
Petr, how did you test this patch?
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Change subject: payloads: FILO: Configure libpayload for LLVM/clang when selected in coreboot
......................................................................
Patch Set 1:
(1 comment)
This change is ready for review.
Patchset:
PS1:
Did you do some tests with llvm built libpayload? Any insights on size and compatibility of the binaries?
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Change subject: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG
......................................................................
Patch Set 9:
(2 comments)
File src/mainboard/google/rex/variants/rex0/fw_config.c:
https://review.coreboot.org/c/coreboot/+/75525/comment/c30a0d4b_18ecda8d :
PS8, Line 104: 1
> > I assumed that this CBI should be the mechanism to determine if Proto1 or Proto2. […]
Done. Supporting Proto 1.
https://review.coreboot.org/c/coreboot/+/75525/comment/bad8d359_1c7db658 :
PS8, Line 111: printk(BIOS_ERR, "Unknown Board Version for ISH.\n");
> > I assumed that it would not configure any GPIO pin if board was not determined. […]
Acknowledged
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Hello Harsha B R, Jamie Ryu, Jay Patel, Kapil Porwal, Subrata Banik, Tarun Tuli, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75525?usp=email
to look at the new patch set (#9).
The following approvals got outdated and were removed:
Code-Review-1 by Subrata Banik, Verified+1 by build bot (Jenkins)
Change subject: mb/google/rex: Configure ISH GPIO's based on FW_CONFIG
......................................................................
mb/google/rex: Configure ISH GPIO's based on FW_CONFIG
Configures ISH related GPIO's based on FW_CONFIG obtained from CBI.
BUG=b:280329972,b:283023296
TEST= Set bit 21 of FW_CONFIG with CBI
Boot rex board
Check that ISH is enabled, loaded, and functional
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>
Change-Id: I3f0f9a7c8318fa9ae59b6f613eafdacbfa07c749
---
M src/mainboard/google/rex/variants/rex0/fw_config.c
1 file changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/75525/9
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Change subject: mb/google/myst: Update PCIe romstage gpios
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/75699/comment/3d3002c5_61db2b34 :
PS2, Line 207: CLK_REQ3_L
Why only CLK_REQ for SSD and not WLAN, SD.
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Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
......................................................................
Patch Set 82:
(1 comment)
Patchset:
PS82:
ok
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Change subject: mb/google/brya/variants/hades: Set WP signal to GPP_E12
......................................................................
Set Ready For Review
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Change subject: mb/google/skyrim: Use CMOS bit to toggle ABL WA for Hynix DRAM
......................................................................
Patch Set 2:
(3 comments)
File src/mainboard/google/skyrim/bootblock.c:
https://review.coreboot.org/c/coreboot/+/75698/comment/d0f8ae1a_a56b3cae :
PS2, Line 17: 18
> It looks like the part name is 18 characters, so should this be 19 for the terminating 0x00?
I'm not sure that matters for strncmp
https://review.coreboot.org/c/coreboot/+/75698/comment/a26f2a15_c1b8b8d6 :
PS2, Line 41: strncmp
> strnicmp? I don't know if we care.
we don't seem to have the case-insensitive version in coreboot currently
https://review.coreboot.org/c/coreboot/+/75698/comment/2fc96d82_43c336d8 :
PS2, Line 94: hynix_dram_cmos_check();
> We can probably restrict this some more. […]
Karthik requested that we not restrict to FF, in case another variant picked up the same memory part. Same reasoning would apply to not restrict based on RAM ID.
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Change subject: mb/google/skyrim: Use CMOS bit to toggle ABL WA for Hynix DRAM
......................................................................
Patch Set 2:
(3 comments)
File src/mainboard/google/skyrim/bootblock.c:
https://review.coreboot.org/c/coreboot/+/75698/comment/13be8c45_cd32dd55 :
PS2, Line 17: 18
It looks like the part name is 18 characters, so should this be 19 for the terminating 0x00?
https://review.coreboot.org/c/coreboot/+/75698/comment/fac82743_15ece9aa :
PS2, Line 41: strncmp
strnicmp? I don't know if we care.
https://review.coreboot.org/c/coreboot/+/75698/comment/e5a16206_2bebf9f5 :
PS2, Line 94: hynix_dram_cmos_check();
We can probably restrict this some more. I believe it's only relevant to frostflow, so that's an easy check, and the linker would exclude it from other mainboards.
We could also restrict when it runs based on the memory ID settings. I'm not completely sure that's worthwhile though.
We can just make sure the cmos bits are clear on other boards/memory IDs.
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