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Change subject: src/soc/intel/meteorlake: disable acpi timer for xtal shutdown
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/meteorlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/75814/comment/da4d5f85_16f574fd :
PS1, Line 619: 0
> IOE.PMC address extracted from PCI device bdf 0/19/2 bar address; and load at runtime from SSRAM.
> a) looks this address is not available in coreboot today.
> b) let me check how BIOS configure this IOE-PMC disable ACPI timer
> NOTE: use itp debugger to verify the IOE/SOC PMC ACPI timer settings.
if we could get the offset and register bit definition. I can give a try and share an image with you.
Looking inside the FSP code, i don't see anything other than SOC.PMC register being programmed under that UPD
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Change subject: src/soc/intel/meteorlake: disable acpi timer for xtal shutdown
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/meteorlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/75814/comment/adaa0e86_d94da6c2 :
PS1, Line 619: 0
> > PMC MMIO + offset 0x18FC : disable ACPI driver is working fine for SoC-PMC. […]
IOE.PMC address extracted from PCI device bdf 0/19/2 bar address; and load at runtime from SSRAM.
a) looks this address is not available in coreboot today.
b) let me check how BIOS configure this IOE-PMC disable ACPI timer
NOTE: use itp debugger to verify the IOE/SOC PMC ACPI timer settings.
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Change subject: mb/google/rex: LZ4 compress ramstage instead of LZMA
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS4:
> > > > `dev` build is failing due to insufficient size. […]
Can you specify build command which has build error?
I tried FSP debug build but I did not see build error. I'm wondering if there is any build command difference and how much size can be issue.
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Change subject: mb/google/myst: Update WWAN usb entry
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/75819/comment/c77b6826_cd355dcc :
PS2, Line 258: probe DAUGHTERBOARD DB_B
Is this change required also?
Has it been tested on a SKU-B to verify the DB is still configured correctly?
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