coreboot-gerrit June 2023

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[XS] Change in coreboot[master]: mb/google/myst: Add additional memory configurations
by Martin Roth (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Karthik Ramasubramanian, Rob Barnes. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75821?usp=email ) Change subject: mb/google/myst: Add additional memory configurations ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75821?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b3b8c9ffcf81bbd2d6ecfad1b612fbf793857c8 Gerrit-Change-Number: 75821 Gerrit-PatchSet: 2 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 19:01:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [WIP] program IOE.PMC to disable ACPI PM timer
by Sukumar Ghorai (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75822?usp=email ) Change subject: [WIP] program IOE.PMC to disable ACPI PM timer ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: IOE PMC: ACPI_TIMER is disabled as expected -- To view, visit https://review.coreboot.org/c/coreboot/+/75822?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6e145f67dba7270e0a322ef414bf1cb09c5eda Gerrit-Change-Number: 75822 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 18:48:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: src/soc/intel/meteorlake: disable acpi timer for xtal shutdown
by Subrata Banik (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Kapil Porwal, Sukumar Ghorai, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75814?usp=email ) Change subject: src/soc/intel/meteorlake: disable acpi timer for xtal shutdown ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/meteorlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/75814/comment/6825ceec_090138eb : PS1, Line 619: 0 > > > IOE.PMC address extracted from PCI device bdf 0/19/2 bar address; and load at runtime from SSRAM. > > > a) looks this address is not available in coreboot today. > > > b) let me check how BIOS configure this IOE-PMC disable ACPI timer > > > NOTE: use itp debugger to verify the IOE/SOC PMC ACPI timer settings. > > > > if we could get the offset and register bit definition. I can give a try and share an image with you. > > > > Looking inside the FSP code, i don't see anything other than SOC.PMC register being programmed under that UPD > > now i understood how this programming is getting handled between SOC.PMC and IOE.PMC. > > I will share a CL with you sooner, can you please try this cl: https://review.coreboot.org/c/coreboot/+/75822 w/o this cl: > iotools mmio_read32 0xfe4018fc 0x0 w this cl: > iotools mmio_read32 0xfe4018fc 0x2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75814?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b5f8f6647364d967ed96c45fe5a9d55fdc8a2c7 Gerrit-Change-Number: 75814 Gerrit-PatchSet: 1 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 18:21:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/myst: Add additional memory configurations
by Jon Murphy (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Karthik Ramasubramanian, Martin Roth, Rob Barnes. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75821?usp=email ) Change subject: mb/google/myst: Add additional memory configurations ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75821?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b3b8c9ffcf81bbd2d6ecfad1b612fbf793857c8 Gerrit-Change-Number: 75821 Gerrit-PatchSet: 2 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 18:17:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [WIP] program IOE.PMC to disable ACPI PM timer
by Subrata Banik (Code Review) 14 Jun '23

14 Jun '23

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75822?usp=email ) Change subject: [WIP] program IOE.PMC to disable ACPI PM timer ...................................................................... [WIP] program IOE.PMC to disable ACPI PM timer Change-Id: Ibb6e145f67dba7270e0a322ef414bf1cb09c5eda Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/meteorlake/include/soc/iomap.h M src/soc/intel/meteorlake/include/soc/pm.h M src/soc/intel/meteorlake/pmc.c M src/soc/intel/meteorlake/pmutil.c 4 files changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/75822/1 diff --git a/src/soc/intel/meteorlake/include/soc/iomap.h b/src/soc/intel/meteorlake/include/soc/iomap.h index a2df40c..3efe400 100644 --- a/src/soc/intel/meteorlake/include/soc/iomap.h +++ b/src/soc/intel/meteorlake/include/soc/iomap.h @@ -25,6 +25,9 @@ #define HPET_BASE_ADDRESS 0xfed00000 +#define IOE_PWRM_BASE_ADDRESS 0xfe400000 +#define IOE_PWRM_BASE_SIZE 0x10000 + #define PCH_PWRM_BASE_ADDRESS 0xfe000000 #define PCH_PWRM_BASE_SIZE 0x10000 diff --git a/src/soc/intel/meteorlake/include/soc/pm.h b/src/soc/intel/meteorlake/include/soc/pm.h index c486232..7474cdd 100644 --- a/src/soc/intel/meteorlake/include/soc/pm.h +++ b/src/soc/intel/meteorlake/include/soc/pm.h @@ -150,6 +150,9 @@ /* Get base address PMC memory mapped registers. */ uint8_t *pmc_mmio_regs(void); +/* Get base address IOE.PMC memory mapped registers. */ +uint8_t *ioe_pmc_mmio_regs(void); + /* Get base address of TCO I/O registers. */ uint16_t smbus_tco_regs(void); diff --git a/src/soc/intel/meteorlake/pmc.c b/src/soc/intel/meteorlake/pmc.c index bdd7a3b..9a2c982 100644 --- a/src/soc/intel/meteorlake/pmc.c +++ b/src/soc/intel/meteorlake/pmc.c @@ -157,8 +157,10 @@ * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. * Disabling ACPI PM timer also switches off TCO */ - if (!CONFIG(USE_PM_ACPI_TIMER)) + if (!CONFIG(USE_PM_ACPI_TIMER)) { setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); + setbits8(ioe_pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); + } } static void pm1_enable_pwrbtn_smi(void *unused) diff --git a/src/soc/intel/meteorlake/pmutil.c b/src/soc/intel/meteorlake/pmutil.c index 8b377c0..abe9550 100644 --- a/src/soc/intel/meteorlake/pmutil.c +++ b/src/soc/intel/meteorlake/pmutil.c @@ -134,6 +134,11 @@ return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS; } +uint8_t *ioe_pmc_mmio_regs(void) +{ + return (void *)(uintptr_t)IOE_PWRM_BASE_ADDRESS; +} + uintptr_t soc_read_pmc_base(void) { return (uintptr_t)pmc_mmio_regs(); -- To view, visit https://review.coreboot.org/c/coreboot/+/75822?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6e145f67dba7270e0a322ef414bf1cb09c5eda Gerrit-Change-Number: 75822 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/myst: Add additional memory configurations
by Rob Barnes (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Jon Murphy, Karthik Ramasubramanian, Rob Barnes. Hello Jon Murphy, Karthik Ramasubramanian, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75821?usp=email to look at the new patch set (#2). Change subject: mb/google/myst: Add additional memory configurations ...................................................................... mb/google/myst: Add additional memory configurations Add additional ram parts and generate strapping ids. BUG=b:285216975 TEST=Build myst image Change-Id: I2b3b8c9ffcf81bbd2d6ecfad1b612fbf793857c8 Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/myst/variants/myst/memory/Makefile.inc M src/mainboard/google/myst/variants/myst/memory/dram_id.generated.txt M src/mainboard/google/myst/variants/myst/memory/mem_parts_used.txt 3 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/75821/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75821?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b3b8c9ffcf81bbd2d6ecfad1b612fbf793857c8 Gerrit-Change-Number: 75821 Gerrit-PatchSet: 2 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: mb/google/myst: Add additional memory configurations
by Rob Barnes (Code Review) 14 Jun '23

14 Jun '23

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75821?usp=email ) Change subject: mb/google/myst: Add additional memory configurations ...................................................................... mb/google/myst: Add additional memory configurations Add additional ram parts and generate strapping ids. BUG=b:285216975 TEST=Build myst image Change-Id: I2b3b8c9ffcf81bbd2d6ecfad1b612fbf793857c8 --- M src/mainboard/google/myst/variants/myst/memory/Makefile.inc M src/mainboard/google/myst/variants/myst/memory/dram_id.generated.txt M src/mainboard/google/myst/variants/myst/memory/mem_parts_used.txt 3 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/75821/1 diff --git a/src/mainboard/google/myst/variants/myst/memory/Makefile.inc b/src/mainboard/google/myst/variants/myst/memory/Makefile.inc index 146ffe8..80510d7 100644 --- a/src/mainboard/google/myst/variants/myst/memory/Makefile.inc +++ b/src/mainboard/google/myst/variants/myst/memory/Makefile.inc @@ -6,3 +6,5 @@ SPD_SOURCES = SPD_SOURCES += spd/lp5/set-1/spd-2.hex # ID = 0(0b0000) Parts = H9JCNNNCP3MLYR-N6E SPD_SOURCES += spd/lp5/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT62F512M32D2DR-031 WT:B +SPD_SOURCES += spd/lp5/set-1/spd-7.hex # ID = 2(0b0010) Parts = MT62F1G32D2DS-026 WT:B +SPD_SOURCES += spd/lp5/set-1/spd-9.hex # ID = 3(0b0011) Parts = K3KL6L60GM-MGCT diff --git a/src/mainboard/google/myst/variants/myst/memory/dram_id.generated.txt b/src/mainboard/google/myst/variants/myst/memory/dram_id.generated.txt index d764f73..91c2c58 100644 --- a/src/mainboard/google/myst/variants/myst/memory/dram_id.generated.txt +++ b/src/mainboard/google/myst/variants/myst/memory/dram_id.generated.txt @@ -6,3 +6,5 @@ DRAM Part Name ID to assign H9JCNNNCP3MLYR-N6E 0 (0000) MT62F512M32D2DR-031 WT:B 1 (0001) +MT62F1G32D2DS-026 WT:B 2 (0010) +K3KL6L60GM-MGCT 3 (0011) diff --git a/src/mainboard/google/myst/variants/myst/memory/mem_parts_used.txt b/src/mainboard/google/myst/variants/myst/memory/mem_parts_used.txt index 5f171de..c9cb401 100644 --- a/src/mainboard/google/myst/variants/myst/memory/mem_parts_used.txt +++ b/src/mainboard/google/myst/variants/myst/memory/mem_parts_used.txt @@ -1,2 +1,4 @@ H9JCNNNCP3MLYR-N6E, MT62F512M32D2DR-031 WT:B, +MT62F1G32D2DS-026 WT:B, +K3KL6L60GM-MGCT, -- To view, visit https://review.coreboot.org/c/coreboot/+/75821?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b3b8c9ffcf81bbd2d6ecfad1b612fbf793857c8 Gerrit-Change-Number: 75821 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: src/soc/intel/meteorlake: disable acpi timer for xtal shutdown
by Subrata Banik (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Kapil Porwal, Sukumar Ghorai, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75814?usp=email ) Change subject: src/soc/intel/meteorlake: disable acpi timer for xtal shutdown ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/meteorlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/75814/comment/688e1ff5_8a50ae27 : PS1, Line 619: 0 > > IOE.PMC address extracted from PCI device bdf 0/19/2 bar address; and load at runtime from SSRAM. > > a) looks this address is not available in coreboot today. > > b) let me check how BIOS configure this IOE-PMC disable ACPI timer > > NOTE: use itp debugger to verify the IOE/SOC PMC ACPI timer settings. > > if we could get the offset and register bit definition. I can give a try and share an image with you. > > Looking inside the FSP code, i don't see anything other than SOC.PMC register being programmed under that UPD now i understood how this programming is getting handled between SOC.PMC and IOE.PMC. I will share a CL with you sooner, -- To view, visit https://review.coreboot.org/c/coreboot/+/75814?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b5f8f6647364d967ed96c45fe5a9d55fdc8a2c7 Gerrit-Change-Number: 75814 Gerrit-PatchSet: 1 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 17:57:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex/var/screebo: rp2 change to rp1 and rp3
by Subrata Banik (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Kapil Porwal, Rui Zhou, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75832?usp=email ) Change subject: mb/google/rex/var/screebo: rp2 change to rp1 and rp3 ...................................................................... Patch Set 1: (2 comments) File src/mainboard/google/rex/variants/screebo/overridetree.cb: https://review.coreboot.org/c/coreboot/+/75832/comment/a44c747f_dc3b33f4 : PS1, Line 245: device ref tbt_pcie_rp1 on end : device ref tbt_pcie_rp3 on end i thought screebo has two type-c ports as tbt_pcie_rp1 and tbt_pcie_rp3 are you making tbt_pcie_rp0 (0: 7.0) being enabled for PCI multiple function device to be enabled ? https://review.coreboot.org/c/coreboot/+/75832/comment/0e088062_fff35689 : PS1, Line 246: use tab -- To view, visit https://review.coreboot.org/c/coreboot/+/75832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1013d26c705f2a3f9378d944bd863d94f319d36c Gerrit-Change-Number: 75832 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 17:46:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/rex: LZ4 compress ramstage instead of LZMA
by Subrata Banik (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Jamie Ryu, Kapil Porwal, Paul Menzel, Raj Astekar, Tarun Tuli, Wonkyu Kim. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75769?usp=email ) Change subject: mb/google/rex: LZ4 compress ramstage instead of LZMA ...................................................................... Patch Set 5: (1 comment) Patchset: PS4: > Can you specify build command which has build error? > I tried FSP debug build but I did not see build error. I'm wondering if there is any build command difference and how much size can be issue. regular emerge-rex is failing (not special steps req) There is marginal and we are afraid it might fail even on CPFE. because there are less than 1KB space left adding this CL -- To view, visit https://review.coreboot.org/c/coreboot/+/75769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded Gerrit-Change-Number: 75769 Gerrit-PatchSet: 5 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 17:00:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2023