coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: soc/intel/cmd/blk/cse: Implement APIs to access CSE version in CMOS
by Dinesh Gehlot (Code Review) 14 Jun '23

14 Jun '23

Dinesh Gehlot has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/75751?usp=email ) Change subject: soc/intel/cmd/blk/cse: Implement APIs to access CSE version in CMOS ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/75751?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d5d895ab00766e0f1964d06e58738a2addb911f Gerrit-Change-Number: 75751 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[XS] Change in coreboot[master]: soc/intel/cmd/blk/cse: Add a kconfig option to store CSE version
by Dinesh Gehlot (Code Review) 14 Jun '23

14 Jun '23

Dinesh Gehlot has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/75746?usp=email ) Change subject: soc/intel/cmd/blk/cse: Add a kconfig option to store CSE version ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/75746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If8a62d00e6ed15fbe595f3729d921df8cef42fdb Gerrit-Change-Number: 75746 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: abandon

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[XS] Change in coreboot[master]: soc/intel/cmd/blk/cse: Perform cse version store under pertinent option
by Dinesh Gehlot (Code Review) 14 Jun '23

14 Jun '23

Dinesh Gehlot has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/75748?usp=email ) Change subject: soc/intel/cmd/blk/cse: Perform cse version store under pertinent option ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/75748?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebe27d3277bb6343cc818069bcbb2dc2e8ef0413 Gerrit-Change-Number: 75748 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: mb/google/rex/var/rex0: add HID over SPI ACPI driver
by Elyes Haouas (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Eran Mitrani, Kapil Porwal, Matt DeVillier, Paul Menzel, Subrata Banik, Tarun Tuli. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74885?usp=email ) Change subject: mb/google/rex/var/rex0: add HID over SPI ACPI driver ...................................................................... Patch Set 18: Code-Review+1 (1 comment) File src/mainboard/google/rex/variants/rex0/include/variant/acpi/hid_spi_elan.asl: https://review.coreboot.org/c/coreboot/+/74885/comment/e6be4950_611948c6 : PS17, Line 56: (LEqual(Arg0,ToUUID("6E2AC436-0FC > please use ASL2. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/74885?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id51d385ce350cef23da4184b044c74569f4dd3f0 Gerrit-Change-Number: 74885 Gerrit-PatchSet: 18 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 14 Jun 2023 16:31:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: src/soc/intel/meteorlake: disable acpi timer for xtal shutdown
by Subrata Banik (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Kapil Porwal, Sukumar Ghorai, Tarun Tuli. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75814?usp=email ) Change subject: src/soc/intel/meteorlake: disable acpi timer for xtal shutdown ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/meteorlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/75814/comment/42b9f3e1_a1e8bd3c : PS1, Line 619: 0 > PMC MMIO + offset 0x18FC : disable ACPI driver is working fine for SoC-PMC. > We need the similar settings for IOE-PMC. > Hence best solution is to disable from FSP parameter. I don't see anywhere inside FSP code even does TCO disablement on the IOE.PMC Appreciate if you can point me the register details which we can even program inside coreboot. -- To view, visit https://review.coreboot.org/c/coreboot/+/75814?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b5f8f6647364d967ed96c45fe5a9d55fdc8a2c7 Gerrit-Change-Number: 75814 Gerrit-PatchSet: 1 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 16:28:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: arch/x86/smbios: Add weak function for BIOS Vendor in SMBIOS Type0
by Martin Roth (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Angel Pons, Arthur Heymans, Eric Lai, Felix Held, Jeff Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nill Ge, Subrata Banik, TangYiwei, Ziang Wang, niehaitao(a)bytedance.com. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75737?usp=email ) Change subject: arch/x86/smbios: Add weak function for BIOS Vendor in SMBIOS Type0 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I want to check the spec before deciding on this... Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75737?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6dfcca338ffc48b150c966b9aefcefe928704d24 Gerrit-Change-Number: 75737 Gerrit-PatchSet: 1 Gerrit-Owner: TangYiwei Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeff Li <lijinfeng01(a)inspur.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: niehaitao(a)bytedance.com Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: niehaitao(a)bytedance.com Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Jeff Li <lijinfeng01(a)inspur.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 14 Jun 2023 16:23:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: arch/x86/smbios: Add weak function for BIOS Vendor in SMBIOS Type0
by Martin Roth (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Angel Pons, Arthur Heymans, Eric Lai, Felix Held, Jeff Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nill Ge, Subrata Banik, TangYiwei, Ziang Wang, niehaitao(a)bytedance.com. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75737?usp=email ) Change subject: arch/x86/smbios: Add weak function for BIOS Vendor in SMBIOS Type0 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > I think "vendor" in SMBIOS type 0 specifies the BIOS image provider on the mother board not the code […] The SMBIOS specification isn't clear on what they mean by "BIOS Vendor's Name", but it seems reasonable to me that this would be who built the firmware. Based on that, I think this should be patch should changed to use a Kconfig option that defaults to 'coreboot', and that the default for all platforms in the coreboot tree should remain coreboot. Using weak function like this will update the ID to a new fixed value regardless of who builds and provides the image. Anyone wanting to change the value on a firmware image they build can do so for all images they build by adding a Kconfig in the site-local directory that updates the string to the new value. -- To view, visit https://review.coreboot.org/c/coreboot/+/75737?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6dfcca338ffc48b150c966b9aefcefe928704d24 Gerrit-Change-Number: 75737 Gerrit-PatchSet: 1 Gerrit-Owner: TangYiwei Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeff Li <lijinfeng01(a)inspur.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: niehaitao(a)bytedance.com Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: niehaitao(a)bytedance.com Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Jeff Li <lijinfeng01(a)inspur.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 14 Jun 2023 16:23:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Comment-In-Reply-To: TangYiwei Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/myst: Update PCIe romstage gpios
by Felix Held (Code Review) 14 Jun '23

14 Jun '23

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75699?usp=email ) Change subject: mb/google/myst: Update PCIe romstage gpios ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75699?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24ad6c1addedb414afade2512b6628022d000a47 Gerrit-Change-Number: 75699 Gerrit-PatchSet: 5 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 16:16:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/skyrim: Use CMOS bit to toggle ABL WA for Hynix DRAM
by Matt DeVillier (Code Review) 14 Jun '23

14 Jun '23

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75698?usp=email ) Change subject: mb/google/skyrim: Use CMOS bit to toggle ABL WA for Hynix DRAM ...................................................................... mb/google/skyrim: Use CMOS bit to toggle ABL WA for Hynix DRAM One specific Hynix LPDDR5x DRAM part requires an ABL workaround to eliminate DRAM-related failures during a FAFT test, but due to the use of generic/common SPDs, there is no way for the ABL to determine the DRAM part # itself. Consequently, we will have coreboot check the DRAM part #, and set/clear a CMOS bit as appropriate, which the ABL will check in order to apply (or not apply) the workaround. The ABL already uses byte 0xD of the extended CMOS ports 72/73 for memory context related toggles, so we will use a spare bit there. BUG=b:270499009, b:281614369, b:286338775 BRANCH=skyrim TEST=run FAFT bios tests on frostflow, markarth, and whiterun without any failures. Change-Id: Ibb6e145f6cdba7270e0a322ef414bf1cb09c5eaa Signed-off-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75698 Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> --- M src/mainboard/google/skyrim/bootblock.c 1 file changed, 56 insertions(+), 0 deletions(-) Approvals: Jason Glenesk: Looks good to me, approved build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/bootblock.c b/src/mainboard/google/skyrim/bootblock.c index 4128090..d285d7f 100644 --- a/src/mainboard/google/skyrim/bootblock.c +++ b/src/mainboard/google/skyrim/bootblock.c @@ -1,9 +1,63 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <amdblocks/espi.h> +#include <amdblocks/reset.h> #include <bootblock_common.h> #include <baseboard/variants.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <pc80/mc146818rtc.h> #include <soc/espi.h> +#include <string.h> + +#define CMOS_EXTENDED_ADDR(x) (128 + (x)) +#define CMOS_MEM_RESTORE_OFFSET 0x0D +#define CMOS_BITMAP_SKIP_RESET_TOGGLE 0x10 +#define HYNIX_PART_NAME "H9JCNNNCP3MLYR-N6E" +#define HYNIX_PART_LEN 18 + +/* Ensure SKIP_RESET_TOGGLE CMOS bit set for specific Hynix part on Frostflow, cleared otherwise */ +static void hynix_dram_cmos_check(void) +{ + char cbi_part_number[DIMM_INFO_PART_NUMBER_SIZE]; + bool skip_reset_toggle, cmos_bit_set; + unsigned char byte_value; + + byte_value = cmos_read(CMOS_EXTENDED_ADDR(CMOS_MEM_RESTORE_OFFSET)); + cmos_bit_set = (byte_value & CMOS_BITMAP_SKIP_RESET_TOGGLE) != 0; + + if (CONFIG(BOARD_GOOGLE_FROSTFLOW)) { + + printk(BIOS_SPEW, "Checking DRAM part #\n"); + if (google_chromeec_cbi_get_dram_part_num( + cbi_part_number, sizeof(cbi_part_number)) == 0) { + + skip_reset_toggle = strncmp(cbi_part_number, HYNIX_PART_NAME, HYNIX_PART_LEN) == 0; + if (skip_reset_toggle) { + printk(BIOS_SPEW, "SKIP_RESET_TOGGLE needed, checking CMOS bit is set\n"); + if (!cmos_bit_set) { + printk(BIOS_SPEW, "Bit is unset; setting and rebooting\n"); + cmos_write((byte_value | CMOS_BITMAP_SKIP_RESET_TOGGLE), + CMOS_EXTENDED_ADDR(CMOS_MEM_RESTORE_OFFSET)); + warm_reset(); + } + printk(BIOS_SPEW, "Bit already set; nothing to do.\n"); + return; + } + } else { + printk(BIOS_ERR, "Unable to read DRAM part # from CBI; CMOS bit will be cleared if set\n"); + } + } + /* Ensure SKIP_RESET_TOGGLE bit cleared if not FF, not bad DRAM part, or error reading part # */ + if (cmos_bit_set) { + printk(BIOS_SPEW, "CMOS SKIP_RESET_TOGGLE bit is set; clearing and rebooting\n"); + cmos_write((byte_value & ~CMOS_BITMAP_SKIP_RESET_TOGGLE), + CMOS_EXTENDED_ADDR(CMOS_MEM_RESTORE_OFFSET)); + warm_reset(); + } else { + printk(BIOS_SPEW, "No change to CMOS SKIP_RESET_TOGGLE bit is needed\n"); + } +} void mb_set_up_early_espi(void) { @@ -34,6 +88,8 @@ size_t num_gpios; const struct soc_amd_gpio *gpios; + hynix_dram_cmos_check(); + variant_bootblock_gpio_table(&gpios, &num_gpios); gpio_configure_pads(gpios, num_gpios); } -- To view, visit https://review.coreboot.org/c/coreboot/+/75698?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6e145f6cdba7270e0a322ef414bf1cb09c5eaa Gerrit-Change-Number: 75698 Gerrit-PatchSet: 5 Gerrit-Owner: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/cmd/blk/cse: Hook get CSE RW version into `.final`
by Nick Vaccaro (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Dinesh Gehlot, Tarun Tuli. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75749?usp=email ) Change subject: soc/intel/cmd/blk/cse: Hook get CSE RW version into `.final` ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75749?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdb82c180b64fbb4575932427be54f544e1c98d4 Gerrit-Change-Number: 75749 Gerrit-PatchSet: 7 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 16:05:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit June 2023