coreboot-gerrit June 2023

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[L] Change in coreboot[master]: mb/bytedance: Add 2 SPR sockets server board bd_egs
by Lean Sheng Tan (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Felix Singer, Jonathan Zhang, Nico Huber, Nill Ge, Patrick Rudolph, Paul Menzel, TangYiwei, niehaitao(a)bytedance.com. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75722?usp=email ) Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d Gerrit-Change-Number: 75722 Gerrit-PatchSet: 7 Gerrit-Owner: TangYiwei Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: niehaitao(a)bytedance.com Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: niehaitao(a)bytedance.com Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Wed, 14 Jun 2023 20:23:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/common/psp_verstage: move post codes to own header
by Matt DeVillier (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Raul Rangel, Yuchen He. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75809?usp=email ) Change subject: soc/amd/common/psp_verstage: move post codes to own header ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75809?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28a932ce071488e90000e1bbd30b4d739a4bae43 Gerrit-Change-Number: 75809 Gerrit-PatchSet: 1 Gerrit-Owner: Yuchen He <yuchenhe126(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Yuchen He <yuchenhe126(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 14 Jun 2023 19:55:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Add configs for TME exclusion range and new key gen
by Pratikkumar V Prajapati (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Paul Menzel, Subrata Banik. Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75625?usp=email ) Change subject: soc/intel/common: Add configs for TME exclusion range and new key gen ...................................................................... Patch Set 6: (13 comments) File src/soc/intel/common/block/cpu/Kconfig: https://review.coreboot.org/c/coreboot/+/75625/comment/7614454b_d505c283 : PS4, Line 146: reboot > boot Done https://review.coreboot.org/c/coreboot/+/75625/comment/6e1dca10_73b83573 : PS4, Line 150: reboot > boot Done https://review.coreboot.org/c/coreboot/+/75625/comment/cf1c2ffc_d1d567b7 : PS4, Line 151: reboot > boot Done https://review.coreboot.org/c/coreboot/+/75625/comment/7eab1f13_25718c21 : PS4, Line 152: reboot > same Done https://review.coreboot.org/c/coreboot/+/75625/comment/853ae4f3_774bb690 : PS4, Line 153: reboot > same Done https://review.coreboot.org/c/coreboot/+/75625/comment/acd691a7_433ab199 : PS4, Line 160: CBMEM > not: this option allow to exclude the CBMEM region from being encrypted by the Intel TME. Done https://review.coreboot.org/c/coreboot/+/75625/comment/7304d218_85b6dd66 : PS4, Line 166: reboot > boot Done https://review.coreboot.org/c/coreboot/+/75625/comment/bf61c0ca_69dcad2c : PS4, Line 168: reboot > boot Done https://review.coreboot.org/c/coreboot/+/75625/comment/f1ae3d6a_6da72cdf : PS4, Line 169: and > hence, Done https://review.coreboot.org/c/coreboot/+/75625/comment/8a9e99e7_ebe79999 : PS4, Line 169: reboot > boot Done https://review.coreboot.org/c/coreboot/+/75625/comment/65c2f23d_8d6367fd : PS4, Line 171: CBMEM > CBMEM region Done https://review.coreboot.org/c/coreboot/+/75625/comment/5ef30eea_c02a4597 : PS4, Line 172: reboot > boot Done https://review.coreboot.org/c/coreboot/+/75625/comment/8a84b6c9_66a9757e : PS4, Line 172: in warm reboot case also. > nit: can be accessible irrespective of the type of the platform reset. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5008fee07b97faadc7dd585f445295425173782 Gerrit-Change-Number: 75625 Gerrit-PatchSet: 6 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 14 Jun 2023 19:44:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/common: Add configs for TME exclusion range and new key gen
by Pratikkumar V Prajapati (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Paul Menzel, Pratikkumar V Prajapati. Hello Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75625?usp=email to look at the new patch set (#6). Change subject: soc/intel/common: Add configs for TME exclusion range and new key gen ...................................................................... soc/intel/common: Add configs for TME exclusion range and new key gen Add following config options. 1. TME_GENERATE_NEW_KEY_ON_WARM_BOOT Program Intel TME to generate a new key for each warm boot. TME always generates a new key on each cold boot. With this option enabled TME generates a new key even in warm boot. Without this option TME reuses the key for warm boot. 2. TME_EXCLUDE_CBMEM_ENCRYPTION This option allows to exclude the CBMEM region from being encrypted by Intel TME. When TME is enabled it encrypts whole DRAM. TME provides option to carve out a region of physical memory to get excluded from encryption. With this config enabled, CBMEM region does not get encrypted by TME. If TME is not programmed to generate a new key in warm boot, exclusion range does not need be programmed due to the fact that TME uses same key in warm boot if TME_GENERATE_NEW_KEY_ON_WARM_BOOT is not set. But if TME is programmed to generate a new key in warm boot, contents of the CBMEM get encrypted with a new key in each warm boot case hence, that leads to loss of CBMEM data from previous warm boot. So enabling this config allows CBMEM region to get excluded from being encrypted and can be accessible irrespective of the type of the platform reset. Bug=b:276120526 TEST=Able to build rex Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Change-Id: Id5008fee07b97faadc7dd585f445295425173782 --- M src/soc/intel/common/block/cpu/Kconfig 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/75625/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/75625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5008fee07b97faadc7dd585f445295425173782 Gerrit-Change-Number: 75625 Gerrit-PatchSet: 6 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/common: Introduce configs for TME exclusion range and new k...
by Pratikkumar V Prajapati (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Paul Menzel, Pratikkumar V Prajapati. Hello Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75625?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common: Introduce configs for TME exclusion range and new key generation ...................................................................... soc/intel/common: Introduce configs for TME exclusion range and new key generation Add following config options. 1. TME_GENERATE_NEW_KEY_ON_WARM_BOOT Program Intel TME to generate a new key for each warm boot. TME always generates a new key on each cold boot. With this option enabled TME generates a new key even in warm boot. Without this option TME reuses the key for warm boot. 2. TME_EXCLUDE_CBMEM_ENCRYPTION This option allows to exclude the CBMEM region from being encrypted by Intel TME. When TME is enabled it encrypts whole DRAM. TME provides option to carve out a region of physical memory to get excluded from encryption. With this config enabled, CBMEM region does not get encrypted by TME. If TME is not programmed to generate a new key in warm boot, exclusion range does not need be programmed due to the fact that TME uses same key in warm boot if TME_GENERATE_NEW_KEY_ON_WARM_BOOT is not set. But if TME is programmed to generate a new key in warm boot, contents of the CBMEM get encrypted with a new key in each warm boot case hence, that leads to loss of CBMEM data from previous warm boot. So enabling this config allows CBMEM region to get excluded from being encrypted and can be accessible irrespective of the type of the platform reset. Bug=b:276120526 TEST=Able to build rex Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com> Change-Id: Id5008fee07b97faadc7dd585f445295425173782 --- M src/soc/intel/common/block/cpu/Kconfig 1 file changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/75625/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/75625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5008fee07b97faadc7dd585f445295425173782 Gerrit-Change-Number: 75625 Gerrit-PatchSet: 5 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: src/soc/intel/meteorlake: disable acpi timer for xtal shutdown
by Sukumar Ghorai (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli. Sukumar Ghorai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75814?usp=email ) Change subject: src/soc/intel/meteorlake: disable acpi timer for xtal shutdown ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/meteorlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/75814/comment/2e9beeaf_bc3734a6 : PS1, Line 619: 0 > > > > IOE. […] https://review.coreboot.org/c/coreboot/+/75822 patch looks good, verified! -- To view, visit https://review.coreboot.org/c/coreboot/+/75814?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b5f8f6647364d967ed96c45fe5a9d55fdc8a2c7 Gerrit-Change-Number: 75814 Gerrit-PatchSet: 1 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 19:29:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-MessageType: comment

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[NoOp] Change in blobs[main]: mb/google/skyrim/var/markarth: Add custom ABL
by Matt DeVillier (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Jon Murphy, Karthik Ramasubramanian, Martin Roth, Paul Menzel, Tim Van Patten. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/blobs/+/75693?usp=email ) Change subject: mb/google/skyrim/var/markarth: Add custom ABL ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > Hi Matt, […] hi Tim, yes, Karthik agreed we'd merge it only to the fw branch, not upstream or ToT. The LT fix is CB:75698 plus an updated ABL for all skyrim boards, which is currently undergoing regression testing. Hopefully that will be done this week, and then we can revert these two temporary CLs. -- To view, visit https://review.coreboot.org/c/blobs/+/75693?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I3e48a16e0a46b2948260fd427b76a2ed88303996 Gerrit-Change-Number: 75693 Gerrit-PatchSet: 4 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 19:27:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: acpi: Add a debug option to print out tables in ACPICA compatible hex
by Felix Held (Code Review) 14 Jun '23

14 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75677?usp=email ) Change subject: acpi: Add a debug option to print out tables in ACPICA compatible hex ...................................................................... acpi: Add a debug option to print out tables in ACPICA compatible hex Sometimes systems don't boot to the OS due to wrong ACPI tables. Printing the tables in an ACPICA compatible format makes analysis of ACPI tables easier. The ACPICA format (acpidump, acpixtract) is the following: " FACS @ 0x0000000000000000 0000: 46 41 43 53 40 00 00 00 E8 24 00 00 00 00 00 00 FACS@....$...... 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ " To achieve analyze ACPI tables capture the coreboot log between "Printing ACPI in ACPICA compatible table" and "Done printing ACPI in ACPICA compatible table". Remove the prefix "[SPEW ] " and then call 'acpixtract -a dump' to extract all the tables. Then use 'iasl -d' on the .dat files to decompile the tables. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/75677 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/Kconfig M src/acpi/acpi.c 2 files changed, 71 insertions(+), 13 deletions(-) Approvals: Lean Sheng Tan: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/Kconfig b/src/Kconfig index f8d7f76..8e72f2d 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1294,6 +1294,19 @@ mainboard code supports this. On supported Intel platforms this works by changing the settings in the descriptor.bin file. +config DEBUG_ACPICA_COMPATIBLE + bool "Print out ACPI tables in ACPICA compatible format" + depends on HAVE_ACPI_TABLES + help + Select this to print out ACPI tables in an ACPICA compatible + format. Set the console loglevel to verbosity 'SPEW'. + To analyze ACPI tables capture the coreboot log between + "Printing ACPI in ACPICA compatible table" and "Done printing + ACPI in ACPICA compatible table". + Remove the prefix "[SPEW ] " and then issue 'acpixtract -a dump' + to extract all the tables. Then use 'iasl -d' on the .dat files + to decompile the tables. + endmenu ############################################################################### diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 6ee5cf4..aa1cd1c 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1822,23 +1822,55 @@ return coreboot_rsdp; } +static void acpixtract_compatible_hexdump(const void *memory, size_t length) +{ + size_t i, j; + uint8_t *line; + size_t num_bytes; + + for (i = 0; i < length; i += 16) { + num_bytes = MIN(length - i, 16); + line = ((uint8_t *)memory) + i; + + printk(BIOS_SPEW, " %04zX:", i); + for (j = 0; j < num_bytes; j++) + printk(BIOS_SPEW, " %02x", line[j]); + for (; j < 16; j++) + printk(BIOS_SPEW, " "); + printk(BIOS_SPEW, " "); + for (j = 0; j < num_bytes; j++) + printk(BIOS_SPEW, "%c", + isprint(line[j]) ? line[j] : '.'); + printk(BIOS_SPEW, "\n"); + } +} + +static void acpidump_print(void *table_ptr) +{ + const acpi_header_t *header = (acpi_header_t *)table_ptr; + const size_t table_size = header->length; + printk(BIOS_SPEW, "%.4s @ 0x0000000000000000\n", header->signature); + acpixtract_compatible_hexdump(table_ptr, table_size); + printk(BIOS_SPEW, "\n"); +} + unsigned long write_acpi_tables(unsigned long start) { unsigned long current; acpi_rsdp_t *rsdp; - acpi_rsdt_t *rsdt; - acpi_xsdt_t *xsdt; - acpi_fadt_t *fadt; - acpi_facs_t *facs; - acpi_header_t *slic_file, *slic; - acpi_header_t *ssdt; - acpi_header_t *dsdt_file, *dsdt; - acpi_mcfg_t *mcfg; - acpi_tcpa_t *tcpa; - acpi_tpm2_t *tpm2; - acpi_madt_t *madt; - acpi_lpit_t *lpit; - acpi_bert_t *bert; + acpi_rsdt_t *rsdt = NULL; + acpi_xsdt_t *xsdt = NULL; + acpi_fadt_t *fadt = NULL; + acpi_facs_t *facs = NULL; + acpi_header_t *slic_file, *slic = NULL; + acpi_header_t *ssdt = NULL; + acpi_header_t *dsdt_file, *dsdt = NULL; + acpi_mcfg_t *mcfg = NULL; + acpi_tcpa_t *tcpa = NULL; + acpi_tpm2_t *tpm2 = NULL; + acpi_madt_t *madt = NULL; + acpi_lpit_t *lpit = NULL; + acpi_bert_t *bert = NULL; struct device *dev; unsigned long fw; size_t slic_size, dsdt_size; @@ -2101,6 +2133,19 @@ } printk(BIOS_INFO, "ACPI: done.\n"); + + if (CONFIG(DEBUG_ACPICA_COMPATIBLE)) { + printk(BIOS_DEBUG, "Printing ACPI tables in ACPICA compatible format\n"); + void *acpi_tables[] = { rsdt, xsdt, fadt, facs, slic, ssdt, dsdt, + mcfg, tcpa, tpm2, madt, lpit, bert }; + for (size_t i = 0; i < ARRAY_SIZE(acpi_tables); i++) { + if (acpi_tables[i] == NULL) + continue; + acpidump_print(acpi_tables[i]); + } + printk(BIOS_DEBUG, "Done printing ACPI tables in ACPICA compatible format\n"); + } + return current; } -- To view, visit https://review.coreboot.org/c/coreboot/+/75677?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b5d879014563f7a2e1f70c45cf871ba72f142dc Gerrit-Change-Number: 75677 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: util/abuild: Improve elapsed time measurement
by Felix Held (Code Review) 14 Jun '23

14 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75802?usp=email ) Change subject: util/abuild: Improve elapsed time measurement ...................................................................... util/abuild: Improve elapsed time measurement Time elapsed for a single board build with ccache typically measures well below 10 seconds. Improve the measurements to milliseconds resolution using bash EPOCHREALTIME (pseudo) environment variable. Change-Id: Iaedc470bb45cf9bb6f14ff8b37cd6f7ae3818a08 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75802 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/abuild/abuild 1 file changed, 54 insertions(+), 9 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved build bot (Jenkins): Verified diff --git a/util/abuild/abuild b/util/abuild/abuild index d103fce..fb2fbaf 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -94,6 +94,10 @@ # Skip builds with this Kconfig value notset skipconfig_unset="" +# EPOCHTIME +ts_exec_shell=$(printf "%(%s)T" -2) +ts_basetime_str=$(date -u --date=@${ts_exec_shell}) + trap interrupt INT function interrupt @@ -364,6 +368,42 @@ return 0 } +# Counting microseconds since start of shell +function add_timestamp +{ + local now=${EPOCHREALTIME} + local seconds=$(echo $now | cut -f 1 -d '.') + local usecs=$(echo $now | cut -f 2 -d '.') + seconds=$(( seconds - ts_exec_shell )) + usecs=$(( seconds * 1000 * 1000 + 10#$usecs )) + printf "%s" $usecs +} + +function ts_delta_seconds +{ + local delta=$(( ($2 - $1) / (1000 * 1000) )) + printf "%s" $delta +} + +function ts_delta_string +{ + local ts_minutes + local ts_seconds + local delta + + delta=$(( ($2 - $1) / 1000 )) + ts_minutes=$(( delta / (60 * 1000) )) + delta=$(( delta % (60 * 1000) )) + ts_seconds=$(( delta / 1000)) + delta=$(( delta % 1000 )) + + if [ $ts_minutes -ne 0 ] ; then + printf "%d min %d sec" $ts_minutes $ts_seconds + else + printf "%d.%03d seconds" $ts_seconds $delta + fi +} + function compile_target { local BUILD_NAME=$1 @@ -371,14 +411,18 @@ if [ "$quiet" == "false" ]; then echo " Compiling $MAINBOARD image$cpuconfig..."; fi CURR=$( pwd ) - #stime=`perl -e 'print time();' 2>/dev/null || date +%s` + + ts_1=$(add_timestamp) eval "$BUILDPREFIX" "$MAKE" "$verboseopt" DOTCONFIG="${build_dir}/config.build" obj="${build_dir}" objutil="$TARGET/sharedutils" BUILD_TIMELESS=$TIMELESS \ &> "${build_dir}/make.log" ; \ MAKE_FAILED=$? + ts_2=$(add_timestamp) + cd "${build_dir}" || return $? - etime=$(perl -e 'print time();' 2>/dev/null || date +%s) - duration=$(( etime - stime )) + duration=$(ts_delta_seconds $ts_0 $ts_2) + duration_str=$(ts_delta_string $ts_0 $ts_2) + junit " <testcase classname='${TESTRUN}${testclass/#/.}' name='$BUILD_NAME' time='$duration' >" if [ $MAKE_FAILED -eq 0 ]; then @@ -386,14 +430,14 @@ junitfile make.log junit "</system-out>" printf "ok\n" > compile.status - printf "%s built successfully. (took %ss)\n" "$BUILD_NAME" "${duration}" + printf "%s built successfully. (took %s)\n" "$BUILD_NAME" "${duration_str}" echo "$BUILD_NAME" >> "$PASSED_BOARDS" else junit "<failure type='BuildFailed'>" junitfile make.log junit "</failure>" printf "failed\n" > compile.status - printf "%s build FAILED after %ss!\nLog excerpt:\n" "$BUILD_NAME" "${duration}" + printf "%s build FAILED after %s!\nLog excerpt:\n" "$BUILD_NAME" "${duration_str}" tail -n $CONTEXT make.log 2> /dev/null || tail -$CONTEXT make.log if [ "$clean_work" = "true" ]; then echo "$BUILD_NAME" >> "$FAILED_BOARDS" @@ -448,7 +492,8 @@ XMLFILE="$ABSPATH/${BUILD_NAME}.xml" rm -f "${XMLFILE}" - stime=$(perl -e 'print time();' 2>/dev/null || date +%s) + ts_0=$(add_timestamp) + create_buildenv "$BUILD_NAME" "$build_dir" "$config_file" local BUILDENV_CREATED=$? @@ -925,11 +970,11 @@ ABSPATH="$(cd "$TARGET/abuild" && pwd)" local XMLFILE="$ABSPATH/__util.xml" rm -f "${XMLFILE}" - stime=$(perl -e 'print time();' 2>/dev/null || date +%s) + stime=$(add_timestamp) $BUILDPREFIX "$MAKE" -j "$cpus" DOTCONFIG="$TMPCFG" obj="$TARGET/temp" objutil="$TARGET/sharedutils" tools > "$TARGET/sharedutils/make.log" 2>&1 local ret=$? - etime=$(perl -e 'print time();' 2>/dev/null || date +%s) - local duration=$(( etime - stime )) + etime=$(add_timestamp) + local duration=$(ts_delta_seconds $stime $etime) junit " <testcase classname='util' name='all' time='$duration' >" if [ $ret -eq 0 ]; then -- To view, visit https://review.coreboot.org/c/coreboot/+/75802?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaedc470bb45cf9bb6f14ff8b37cd6f7ae3818a08 Gerrit-Change-Number: 75802 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mb/google/rex: LZ4 compress ramstage instead of LZMA
by Wonkyu Kim (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Jamie Ryu, Kapil Porwal, Paul Menzel, Raj Astekar, Subrata Banik, Tarun Tuli. Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75769?usp=email ) Change subject: mb/google/rex: LZ4 compress ramstage instead of LZMA ...................................................................... Patch Set 5: (1 comment) Patchset: PS4: > > Can you specify build command which has build error? […] Is it due to RO region limitation(4MB)? If so, I'm wondering if we can have different compression method for RO(LZMA) and RW(LZ4) as we're focusing normal boot time which use RW region. -- To view, visit https://review.coreboot.org/c/coreboot/+/75769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded Gerrit-Change-Number: 75769 Gerrit-PatchSet: 5 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 19:21:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2023