coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

1 participants
5387 discussions

[M] Change in coreboot[master]: mb/amd/birman/devicetree_phoenix: update USB PHY settings
by Felix Held (Code Review) 15 Jun '23

15 Jun '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75823?usp=email ) Change subject: mb/amd/birman/devicetree_phoenix: update USB PHY settings ...................................................................... mb/amd/birman/devicetree_phoenix: update USB PHY settings Update the initial USB PHY tuning values that were a copy of the ones from the Chausie mainboard to the values used in the Birman UEFI firmware reference implementation. The USB3 PHY tuning values are still the same while some of the USB2 PHY tuning values are different. The last two USB2 PHYs that are used by the USB4 controllers have a different parameter set compared to the other USB2 PHYs. TEST=None Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0ddfa2594d66b21582282ab8509c921a6e81a93f --- M src/mainboard/amd/birman/devicetree_phoenix.cb 1 file changed, 40 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/75823/1 diff --git a/src/mainboard/amd/birman/devicetree_phoenix.cb b/src/mainboard/amd/birman/devicetree_phoenix.cb index 6cbb36f..6894764 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix.cb @@ -44,13 +44,13 @@ register "usb_phy_custom" = "1" register "usb_phy" = "{ .Usb2PhyPort[0] = { - .compdistune = 0x3, + .compdistune = 0x1, .pllbtune = 0x1, .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, .txpreemppulsetune = 0x0, .txrisetune = 0x1, .txvreftune = 0x3, @@ -58,13 +58,13 @@ .txrestune = 0x2, }, .Usb2PhyPort[1] = { - .compdistune = 0x3, + .compdistune = 0x1, .pllbtune = 0x1, .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, .txpreemppulsetune = 0x0, .txrisetune = 0x1, .txvreftune = 0x3, @@ -72,13 +72,13 @@ .txrestune = 0x2, }, .Usb2PhyPort[2] = { - .compdistune = 0x3, + .compdistune = 0x1, .pllbtune = 0x1, .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, .txpreemppulsetune = 0x0, .txrisetune = 0x1, .txvreftune = 0x3, @@ -86,13 +86,13 @@ .txrestune = 0x2, }, .Usb2PhyPort[3] = { - .compdistune = 0x3, + .compdistune = 0x1, .pllbtune = 0x1, .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, .txpreemppulsetune = 0x0, .txrisetune = 0x1, .txvreftune = 0x3, @@ -100,13 +100,13 @@ .txrestune = 0x2, }, .Usb2PhyPort[4] = { - .compdistune = 0x3, + .compdistune = 0x1, .pllbtune = 0x1, .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, .txpreemppulsetune = 0x0, .txrisetune = 0x1, .txvreftune = 0x3, @@ -114,13 +114,13 @@ .txrestune = 0x2, }, .Usb2PhyPort[5] = { - .compdistune = 0x3, + .compdistune = 0x1, .pllbtune = 0x1, .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, .txpreemppulsetune = 0x0, .txrisetune = 0x1, .txvreftune = 0x3, @@ -131,13 +131,13 @@ .compdistune = 0x3, .pllbtune = 0x1, .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, .txpreemppulsetune = 0x0, .txrisetune = 0x1, - .txvreftune = 0x3, + .txvreftune = 0x6, .txhsxvtune = 0x3, .txrestune = 0x2, }, @@ -145,13 +145,13 @@ .compdistune = 0x3, .pllbtune = 0x1, .pllitune = 0x0, - .pllptune = 0xe, - .sqrxtune = 0x3, - .txfslstune = 0x3, - .txpreempamptune = 0x2, + .pllptune = 0xc, + .sqrxtune = 0x2, + .txfslstune = 0x1, + .txpreempamptune = 0x3, .txpreemppulsetune = 0x0, .txrisetune = 0x1, - .txvreftune = 0x3, + .txvreftune = 0x6, .txhsxvtune = 0x3, .txrestune = 0x2, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/75823?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ddfa2594d66b21582282ab8509c921a6e81a93f Gerrit-Change-Number: 75823 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[master]: mb/bytedance: Add 2 SPR sockets server board bd_egs
by Kyösti Mälkki (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Felix Singer, Jonathan Zhang, Nico Huber, Nill Ge, Patrick Rudolph, Paul Menzel, TangYiwei, niehaitao(a)bytedance.com. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75722?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/bytedance: Add 2 SPR sockets server board bd_egs ...................................................................... Patch Set 7: (1 comment) File src/mainboard/bytedance/bd_egs/bootblock.c: https://review.coreboot.org/c/coreboot/+/75722/comment/0c45e712_477b7690 : PS6, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ > Done I would assume these files are mostly forked from intel/archercity_crb and the owner of this commit is not allowed to change license. -- To view, visit https://review.coreboot.org/c/coreboot/+/75722?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I091bc78e39cd76b3c6b9a10a1fcf58e9d671ef5d Gerrit-Change-Number: 75722 Gerrit-PatchSet: 7 Gerrit-Owner: TangYiwei Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nill Ge <geshijian(a)bytedance.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: niehaitao(a)bytedance.com Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: niehaitao(a)bytedance.com Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nill Ge <geshijian(a)bytedance.com> Gerrit-Attention: TangYiwei Gerrit-Comment-Date: Wed, 14 Jun 2023 22:00:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: TangYiwei Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc|vc/amd/phoenix: Prepare for PSP verstage
by Martin L Roth (Code Review) 14 Jun '23

14 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75584?usp=email ) Change subject: soc|vc/amd/phoenix: Prepare for PSP verstage ...................................................................... soc|vc/amd/phoenix: Prepare for PSP verstage Update all the required sources to lay the ground work to enable PSP verstage. BUG=b:284984667 TEST=Build Myst BIOS image with PSP verstage enabled. Change-Id: I6fbb1f835ac2ad6ff47f843321e1bd380af7ce33 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75584 Reviewed-by: Tim Van Patten <timvp(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/soc/amd/phoenix/include/soc/psp_verstage_addr.h M src/soc/amd/phoenix/psp_verstage/Makefile.inc M src/soc/amd/phoenix/psp_verstage/chipset.c M src/soc/amd/phoenix/psp_verstage/svc.c M src/soc/amd/phoenix/psp_verstage/svc.h M src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h 6 files changed, 117 insertions(+), 23 deletions(-) Approvals: Tim Van Patten: Looks good to me, but someone else must approve build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved diff --git a/src/soc/amd/phoenix/include/soc/psp_verstage_addr.h b/src/soc/amd/phoenix/include/soc/psp_verstage_addr.h index ee9deda..30f65f6 100644 --- a/src/soc/amd/phoenix/include/soc/psp_verstage_addr.h +++ b/src/soc/amd/phoenix/include/soc/psp_verstage_addr.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Phoenix */ - #ifndef AMD_PHOENIX_PSP_VERSTAGE_ADDR_H #define AMD_PHOENIX_PSP_VERSTAGE_ADDR_H diff --git a/src/soc/amd/phoenix/psp_verstage/Makefile.inc b/src/soc/amd/phoenix/psp_verstage/Makefile.inc index 6ff447c..6a2eace 100644 --- a/src/soc/amd/phoenix/psp_verstage/Makefile.inc +++ b/src/soc/amd/phoenix/psp_verstage/Makefile.inc @@ -1,10 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only -ifeq $($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage -subdirs-y += ../../common/psp_verstage - -verstage-generic-ccopts += -I$(src)/soc/amd/phoenix/psp_verstage/include verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/phoenix/include verstage-generic-ccopts += -Isrc/vendorcode/amd/fsp/common/include @@ -15,5 +12,3 @@ verstage-y +=$(top)/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_startup.S verstage-y += $(top)/src/vendorcode/amd/fsp/common/bl_uapp/bl_uapp_end.S - -endif diff --git a/src/soc/amd/phoenix/psp_verstage/chipset.c b/src/soc/amd/phoenix/psp_verstage/chipset.c index 3f3a7cf..acbd559 100644 --- a/src/soc/amd/phoenix/psp_verstage/chipset.c +++ b/src/soc/amd/phoenix/psp_verstage/chipset.c @@ -1,11 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Phoenix */ - +#include "2api.h" +#include <arch/hlt.h> +#include <bl_uapp/bl_errorcodes_public.h> #include <bl_uapp/bl_syscall_public.h> +#include <boot_device.h> #include <cbfs.h> #include <console/console.h> #include <psp_verstage.h> +#include <security/vboot/misc.h> +#include <security/vboot/vbnv.h> /* * We can't pass pointer to hash table in the SPI. @@ -20,7 +24,8 @@ void update_psp_fw_hash_table(const char *fname) { - uint8_t *spi_ptr = (uint8_t *)cbfs_map(fname, NULL); + void *hash_file = cbfs_map(fname, NULL); + uint8_t *spi_ptr = (uint8_t *)hash_file; uint32_t len; if (!spi_ptr) { @@ -39,6 +44,8 @@ printk(BIOS_ERR, "Too many entries in AMD Firmware hash table" " (SHA256:%d, SHA384:%d)\n", hash_table.no_of_entries_256, hash_table.no_of_entries_384); + cbfs_unmap(hash_file); + rdev_munmap(boot_device_ro(), hash_file); return; } @@ -47,6 +54,8 @@ printk(BIOS_ERR, "No entries in AMD Firmware hash table" " (SHA256:%d, SHA384:%d)\n", hash_table.no_of_entries_256, hash_table.no_of_entries_384); + cbfs_unmap(hash_file); + rdev_munmap(boot_device_ro(), hash_file); return; } @@ -62,6 +71,8 @@ memcpy(hash_384, spi_ptr, len); svc_set_fw_hash_table(&hash_table); + cbfs_unmap(hash_file); + rdev_munmap(boot_device_ro(), hash_file); } uint32_t update_psp_bios_dir(uint32_t *psp_dir_offset, uint32_t *bios_dir_offset) @@ -94,16 +105,6 @@ return 0; } - -/* Functions below are stub functions for not-yet-implemented PSP features. - * These functions should be replaced with proper implementations later. - */ - -uint32_t svc_write_postcode(uint32_t postcode) -{ - return 0; -} - void platform_report_mode(int developer_mode_enabled) { printk(BIOS_INFO, "Reporting %s mode\n", @@ -113,3 +114,36 @@ else svc_set_platform_boot_mode(CHROME_BOOK_BOOT_MODE_NORMAL); } + +void report_prev_boot_status_to_vboot(void) +{ + uint32_t boot_status = 0; + int ret; + struct vb2_context *ctx = vboot_get_context(); + + /* Already in recovery mode. No need to report previous boot status. */ + if (ctx->flags & VB2_CONTEXT_RECOVERY_MODE) + return; + + ret = svc_get_prev_boot_status(&boot_status); + if (ret != BL_OK || boot_status) { + printk(BIOS_ERR, "PSPFW failure in previous boot: %d:%#8x\n", ret, boot_status); + vbnv_init(); + vb2api_previous_boot_fail(ctx, VB2_RECOVERY_FW_VENDOR_BLOB, + boot_status ? (int)boot_status : ret); + } +} + +void report_hsp_secure_state(void) +{ + uint32_t hsp_secure_state; + int ret; + + ret = svc_get_hsp_secure_state(&hsp_secure_state); + if (ret != BL_OK) { + printk(BIOS_ERR, "Error reading HSP Secure state: %d\n", ret); + hlt(); + } + + printk(BIOS_INFO, "HSP Secure state: %#8x\n", hsp_secure_state); +} diff --git a/src/soc/amd/phoenix/psp_verstage/svc.c b/src/soc/amd/phoenix/psp_verstage/svc.c index becfcb0..c88f759 100644 --- a/src/soc/amd/phoenix/psp_verstage/svc.c +++ b/src/soc/amd/phoenix/psp_verstage/svc.c @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Update for Phoenix */ - #include "svc.h" #include <assert.h> @@ -217,3 +215,32 @@ SVC_CALL2(SVC_VERSTAGE_CMD, CMD_SET_FW_HASH_TABLE, (void *)&param, retval); return retval; } + +uint32_t svc_get_prev_boot_status(uint32_t *boot_status) +{ + uint32_t retval = 0; + struct cmd_param_get_prev_boot_status param = { + .ptr_boot_status = boot_status, + }; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_GET_PREV_BOOT_STATUS, (void *)&param, retval); + return retval; +} + +uint32_t svc_get_hsp_secure_state(uint32_t *hsp_secure_state) +{ + uint32_t retval = 0; + struct cmd_param_get_hsp_secure_state param; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_GET_HSP_SECURE_STATE, (void *)&param, retval); + *hsp_secure_state = param.hsp_secure_state; + return retval; +} + +uint32_t svc_write_postcode(uint32_t postcode) +{ + uint32_t retval = 0; + struct cmd_param_postcode param = { + .postcode = postcode, + }; + SVC_CALL2(SVC_VERSTAGE_CMD, CMD_WRITE_POSTCODE, (void *)&param, retval); + return retval; +} diff --git a/src/soc/amd/phoenix/psp_verstage/svc.h b/src/soc/amd/phoenix/psp_verstage/svc.h index 3c59a1c..c3e6475 100644 --- a/src/soc/amd/phoenix/psp_verstage/svc.h +++ b/src/soc/amd/phoenix/psp_verstage/svc.h @@ -95,4 +95,16 @@ struct psp_fw_hash_table *ptr_psp_fw_hash_table; }; +struct cmd_param_get_prev_boot_status { + unsigned int *ptr_boot_status; +}; + +struct cmd_param_get_hsp_secure_state { + unsigned int hsp_secure_state; +}; + +struct cmd_param_postcode { + uint32_t postcode; +}; + #endif /* PSP_VERSTAGE_SVC_H */ diff --git a/src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h index 30ea49f..623762a 100644 --- a/src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/phoenix/include/bl_uapp/bl_syscall_public.h @@ -57,6 +57,9 @@ CMD_CCP_DMA, CMD_SET_PLATFORM_BOOT_MODE, CMD_SET_FW_HASH_TABLE, + CMD_GET_PREV_BOOT_STATUS, + CMD_GET_HSP_SECURE_STATE, + CMD_WRITE_POSTCODE, }; struct mod_exp_params { @@ -94,6 +97,7 @@ FCH_IO_DEVICE_MISC, FCH_IO_DEVICE_AOAC, FCH_IO_DEVICE_IOPORT, + FCH_IO_DEVICE_UART, FCH_IO_DEVICE_END, }; @@ -105,6 +109,12 @@ FCH_I2C_CONTROLLER_ID_MAX, }; +enum fch_uart_id { + FCH_UART_ID_0 = 0, + FCH_UART_ID_1 = 1, + FCH_UART_ID_MAX, +}; + struct spirom_info { void *SpiBiosSysHubBase; void *SpiBiosSmnBase; @@ -371,6 +381,24 @@ */ uint32_t svc_set_fw_hash_table(struct psp_fw_hash_table *hash_table); +/* Get the previous boot status. + * + * Parameters: + * - boot_status - Address where the boot status is read into + * + * Return value: BL_OK or error code + */ +uint32_t svc_get_prev_boot_status(uint32_t *boot_status); + +/* Get HSP Secure state + * + * Parameters: + * - hsp_secure_state - Address where the state info is read into + * + * Return value: BL_OK or error code + */ +uint32_t svc_get_hsp_secure_state(uint32_t *hsp_secure_state); + /* C entry point for the Bootloader Userspace Application */ void Main(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/75584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fbb1f835ac2ad6ff47f843321e1bd380af7ce33 Gerrit-Change-Number: 75584 Gerrit-PatchSet: 4 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: soc|vc/amd/phoenix: Prepare for PSP verstage
by Martin L Roth (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Jon Murphy, Karthik Ramasubramanian, Martin Roth, Matt DeVillier, Raul Rangel. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75584?usp=email ) Change subject: soc|vc/amd/phoenix: Prepare for PSP verstage ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fbb1f835ac2ad6ff47f843321e1bd380af7ce33 Gerrit-Change-Number: 75584 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 14 Jun 2023 21:19:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/alderlake/vr_config.c: Fix GT domain TDC current
by Martin L Roth (Code Review) 14 Jun '23

14 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72998?usp=email ) Change subject: soc/intel/alderlake/vr_config.c: Fix GT domain TDC current ...................................................................... soc/intel/alderlake/vr_config.c: Fix GT domain TDC current Alder Lake-S 2+0 SKUs and 35W SKUs have 20A GT TDC, all other Alder Lake-S SKUs have GT TDC of 22A. Based on the default settings of ADL-S FSP. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ie6851d322fc9354d019a76503c3d35b5e6eca48b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72998 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M src/soc/intel/alderlake/vr_config.c 1 file changed, 15 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Krystian Hebel: Looks good to me, approved diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 597f8c5..e24d095 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -249,21 +249,21 @@ { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, - { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, - { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, - { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 89) }, - { PCI_DID_INTEL_ADL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(56, 56) }, - { PCI_DID_INTEL_ADL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(109, 109) }, - { PCI_DID_INTEL_ADL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(77, 77) }, - { PCI_DID_INTEL_ADL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(49, 49) }, - { PCI_DID_INTEL_ADL_S_ID_8, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(96, 96) }, - { PCI_DID_INTEL_ADL_S_ID_10, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(66, 66) }, - { PCI_DID_INTEL_ADL_S_ID_10, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(44, 44) }, - { PCI_DID_INTEL_ADL_S_ID_11, 60, VR_CFG_ALL_DOMAINS_TDC_CURRENT(56, 56) }, - { PCI_DID_INTEL_ADL_S_ID_11, 58, VR_CFG_ALL_DOMAINS_TDC_CURRENT(59, 59) }, - { PCI_DID_INTEL_ADL_S_ID_11, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 40) }, - { PCI_DID_INTEL_ADL_S_ID_12, 46, VR_CFG_ALL_DOMAINS_TDC_CURRENT(39, 39) }, - { PCI_DID_INTEL_ADL_S_ID_12, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(30, 30) }, + { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 22) }, + { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 22) }, + { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, + { PCI_DID_INTEL_ADL_S_ID_1, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(56, 20) }, + { PCI_DID_INTEL_ADL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(109, 22) }, + { PCI_DID_INTEL_ADL_S_ID_3, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(77, 22) }, + { PCI_DID_INTEL_ADL_S_ID_3, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(49, 20) }, + { PCI_DID_INTEL_ADL_S_ID_8, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(96, 22) }, + { PCI_DID_INTEL_ADL_S_ID_10, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(66, 22) }, + { PCI_DID_INTEL_ADL_S_ID_10, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(44, 20) }, + { PCI_DID_INTEL_ADL_S_ID_11, 60, VR_CFG_ALL_DOMAINS_TDC_CURRENT(56, 22) }, + { PCI_DID_INTEL_ADL_S_ID_11, 58, VR_CFG_ALL_DOMAINS_TDC_CURRENT(59, 22) }, + { PCI_DID_INTEL_ADL_S_ID_11, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(40, 20) }, + { PCI_DID_INTEL_ADL_S_ID_12, 46, VR_CFG_ALL_DOMAINS_TDC_CURRENT(39, 20) }, + { PCI_DID_INTEL_ADL_S_ID_12, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(30, 20) }, }; static void fill_vr_fast_vmode(FSP_S_CONFIG *s_cfg, -- To view, visit https://review.coreboot.org/c/coreboot/+/72998?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6851d322fc9354d019a76503c3d35b5e6eca48b Gerrit-Change-Number: 72998 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Baieswara Reddy Sagili <baieswara.reddy.sagili(a)intel.corp-partner.google.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: acpi/acpi.h: Remove global acpi_fill_ivrs_ioapic()
by Martin L Roth (Code Review) 14 Jun '23

14 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75711?usp=email ) Change subject: acpi/acpi.h: Remove global acpi_fill_ivrs_ioapic() ...................................................................... acpi/acpi.h: Remove global acpi_fill_ivrs_ioapic() In soc/amd this function is unused so drop it and rename _acpi_fill_ivrs_ioapic(). Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ic403fd84cb9cd5805fbc6f0c5a64cefbf4b0cd81 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75711 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Naresh <naresh.solanki.2011(a)gmail.com> --- M src/include/acpi/acpi.h M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/amd/common/block/acpi/ivrs.c 3 files changed, 4 insertions(+), 17 deletions(-) Approvals: build bot (Jenkins): Verified Naresh: Looks good to me, approved diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index c981ee1..09e1211 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1337,7 +1337,6 @@ void preload_acpi_dsdt(void); unsigned long write_acpi_tables(unsigned long addr); unsigned long acpi_fill_madt(unsigned long current); -unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current); void acpi_fill_fadt(acpi_fadt_t *fadt); void arch_fill_fadt(acpi_fadt_t *fadt); diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 116cf63..f1a69c2 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -242,7 +242,7 @@ return (unsigned long)current; } -unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) +static unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) { /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ current = ALIGN_UP(current, 8); diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 1629ff9..7f1fe5d 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -17,7 +17,7 @@ #include <soc/iomap.h> #include <soc/pci_devs.h> -static unsigned long _acpi_fill_ivrs_ioapic(unsigned long current, void *ioapic_base, +static unsigned long acpi_fill_ivrs_ioapic(unsigned long current, void *ioapic_base, uint16_t src_devid, uint8_t dte_setting) { ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; @@ -33,18 +33,6 @@ return current; } -unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) -{ - uint32_t dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | - IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | - IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; - - current = _acpi_fill_ivrs_ioapic(current, VIO_APIC_VADDR, - SMBUS_DEVFN, dte_setting); - return _acpi_fill_ivrs_ioapic(current, (u8 *)GNB_IO_APIC_ADDR, - PCI_DEVFN(0, 1), 0); -} - static unsigned long ivhd_describe_hpet(unsigned long current, uint8_t hndl, uint16_t src_devid) { ivrs_ivhd_special_t *ivhd_hpet = (ivrs_ivhd_special_t *)current; @@ -204,7 +192,7 @@ res = probe_resource(dev, IOMMU_IOAPIC_IDX); if (res) { /* Describe IOAPIC associated with the IOMMU */ - current = _acpi_fill_ivrs_ioapic(current, (u8 *)(uintptr_t)res->base, + current = acpi_fill_ivrs_ioapic(current, (u8 *)(uintptr_t)res->base, PCI_DEVFN(0, 1) | (dev->link_list->secondary << 8), 0); } @@ -213,7 +201,7 @@ /* Describe HPET */ current = ivhd_describe_hpet(current, 0x00, SMBUS_DEVFN); /* Describe FCH IOAPICs */ - current = _acpi_fill_ivrs_ioapic(current, VIO_APIC_VADDR, + current = acpi_fill_ivrs_ioapic(current, VIO_APIC_VADDR, SMBUS_DEVFN, dte_setting); } -- To view, visit https://review.coreboot.org/c/coreboot/+/75711?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic403fd84cb9cd5805fbc6f0c5a64cefbf4b0cd81 Gerrit-Change-Number: 75711 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Naresh <naresh.solanki.2011(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/amd/acpi/ivrs: Use specific IOMMU resource index on all SOC
by Martin L Roth (Code Review) 14 Jun '23

14 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75710?usp=email ) Change subject: soc/amd/acpi/ivrs: Use specific IOMMU resource index on all SOC ...................................................................... soc/amd/acpi/ivrs: Use specific IOMMU resource index on all SOC By adding all DXIO IOAPIC with the same resource index, the IVRS code can always pick that resource which simplifies the code. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I10345e2337dcb709c2c1a8e57a1b7dd9c04adb9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/75710 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Reviewed-by: Naresh <naresh.solanki.2011(a)gmail.com> --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/glinda/root_complex.c M src/soc/amd/mendocino/root_complex.c M src/soc/amd/phoenix/root_complex.c M src/soc/amd/picasso/root_complex.c 6 files changed, 10 insertions(+), 8 deletions(-) Approvals: Martin L Roth: Looks good to me, approved Naresh: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index bbddfab..29070f6 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -3,6 +3,7 @@ #include <acpi/acpigen.h> #include <amdblocks/acpi.h> #include <amdblocks/alib.h> +#include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> #include <arch/ioapic.h> @@ -145,7 +146,7 @@ mmconf_resource(dev, idx++); /* GNB IOAPIC resource */ - gnb_apic = new_resource(dev, idx++); + gnb_apic = new_resource(dev, IOMMU_IOAPIC_IDX); gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 3e58a61..1629ff9 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -206,9 +206,6 @@ /* Describe IOAPIC associated with the IOMMU */ current = _acpi_fill_ivrs_ioapic(current, (u8 *)(uintptr_t)res->base, PCI_DEVFN(0, 1) | (dev->link_list->secondary << 8), 0); - } else if (dev->link_list->secondary == 0) { - current = _acpi_fill_ivrs_ioapic(current, (u8 *)GNB_IO_APIC_ADDR, - PCI_DEVFN(0, 1), 0); } /* If the domain has secondary bus as zero then associate HPET & FCH IOAPIC */ diff --git a/src/soc/amd/glinda/root_complex.c b/src/soc/amd/glinda/root_complex.c index 64d90ee..b18e948 100644 --- a/src/soc/amd/glinda/root_complex.c +++ b/src/soc/amd/glinda/root_complex.c @@ -5,6 +5,7 @@ #include <acpi/acpigen.h> #include <amdblocks/acpi.h> #include <amdblocks/alib.h> +#include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> #include <arch/ioapic.h> @@ -160,7 +161,7 @@ mmconf_resource(dev, idx++); /* GNB IOAPIC resource */ - gnb_apic = new_resource(dev, idx++); + gnb_apic = new_resource(dev, IOMMU_IOAPIC_IDX); gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/soc/amd/mendocino/root_complex.c b/src/soc/amd/mendocino/root_complex.c index 6f93502..7a58f01 100644 --- a/src/soc/amd/mendocino/root_complex.c +++ b/src/soc/amd/mendocino/root_complex.c @@ -5,6 +5,7 @@ #include <acpi/acpigen.h> #include <amdblocks/acpi.h> #include <amdblocks/alib.h> +#include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> #include <arch/ioapic.h> @@ -188,7 +189,7 @@ mmconf_resource(dev, idx++); /* GNB IOAPIC resource */ - gnb_apic = new_resource(dev, idx++); + gnb_apic = new_resource(dev, IOMMU_IOAPIC_IDX); gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/soc/amd/phoenix/root_complex.c b/src/soc/amd/phoenix/root_complex.c index 64f9ca4..3110ea3 100644 --- a/src/soc/amd/phoenix/root_complex.c +++ b/src/soc/amd/phoenix/root_complex.c @@ -5,6 +5,7 @@ #include <acpi/acpigen.h> #include <amdblocks/acpi.h> #include <amdblocks/alib.h> +#include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> #include <amdblocks/memmap.h> #include <arch/ioapic.h> @@ -160,7 +161,7 @@ mmconf_resource(dev, idx++); /* GNB IOAPIC resource */ - gnb_apic = new_resource(dev, idx++); + gnb_apic = new_resource(dev, IOMMU_IOAPIC_IDX); gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index e61208f..cd10fdb 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -3,6 +3,7 @@ #include <acpi/acpigen.h> #include <amdblocks/acpi.h> #include <amdblocks/alib.h> +#include <amdblocks/data_fabric.h> #include <amdblocks/memmap.h> #include <amdblocks/ioapic.h> #include <arch/ioapic.h> @@ -143,7 +144,7 @@ mmconf_resource(dev, idx++); /* GNB IOAPIC resource */ - gnb_apic = new_resource(dev, idx++); + gnb_apic = new_resource(dev, IOMMU_IOAPIC_IDX); gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -- To view, visit https://review.coreboot.org/c/coreboot/+/75710?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10345e2337dcb709c2c1a8e57a1b7dd9c04adb9e Gerrit-Change-Number: 75710 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Naresh <naresh.solanki.2011(a)gmail.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: soc/amd/acpi/ivrs: Use specific IOMMU resource index on all SOC
by Martin L Roth (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Naresh Solanki, Raul Rangel. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75710?usp=email ) Change subject: soc/amd/acpi/ivrs: Use specific IOMMU resource index on all SOC ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75710?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10345e2337dcb709c2c1a8e57a1b7dd9c04adb9e Gerrit-Change-Number: 75710 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Naresh <naresh.solanki.2011(a)gmail.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 14 Jun 2023 21:10:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: soc/amd/block/ivrs: Add NULL check for IVRS
by Martin L Roth (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Felix Singer, Fred Reitberger, Jason Glenesk, Matt DeVillier, Naresh Solanki, Raul Rangel. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75506?usp=email ) Change subject: soc/amd/block/ivrs: Add NULL check for IVRS ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeb0ea3bcaa3512a93500588ad4f11046edee61f Gerrit-Change-Number: 75506 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 14 Jun 2023 21:05:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: soc/amd/block/ivrs: Add NULL check for IVRS
by Lean Sheng Tan (Code Review) 14 Jun '23

14 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Felix Singer, Fred Reitberger, Jason Glenesk, Matt DeVillier, Naresh Solanki, Raul Rangel. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75506?usp=email ) Change subject: soc/amd/block/ivrs: Add NULL check for IVRS ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeb0ea3bcaa3512a93500588ad4f11046edee61f Gerrit-Change-Number: 75506 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 14 Jun 2023 20:24:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2023