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Change subject: mb/google/brya/var/volmar: Add Micron MT53E2G32D4NQ-046 WT:C SPD
......................................................................
Patch Set 2: Code-Review+2
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Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74886?usp=email )
(
15 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/google/rex: add Elan HID over SPI ASL for Rex0
......................................................................
mb/google/rex: add Elan HID over SPI ASL for Rex0
This patch enables adding variant specific ASL code
TEST=Kernel driver is able to communicate with device
Signed-off-by: Eran Mitrani <mitrani(a)google.com>
Change-Id: I231482d56dd4afa150766c07cfde105158e5e124
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74886
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Reviewed-by: Subrata Banik <subratabanik(a)google.com>
---
M src/mainboard/google/rex/dsdt.asl
1 file changed, 7 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Kapil Porwal: Looks good to me, approved
Subrata Banik: Looks good to me, approved
diff --git a/src/mainboard/google/rex/dsdt.asl b/src/mainboard/google/rex/dsdt.asl
index f914b3d..fb94cac 100644
--- a/src/mainboard/google/rex/dsdt.asl
+++ b/src/mainboard/google/rex/dsdt.asl
@@ -37,4 +37,11 @@
/* ACPI code for EC functions */
#include <ec/google/chromeec/acpi/ec.asl>
}
+ /* Mainboard specific */
+#if CONFIG(BOARD_GOOGLE_REX0)
+ Scope (\_SB.PCI0.SPI0)
+ {
+ #include <variant/acpi/hid_spi_elan.asl>
+ }
+#endif
}
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Change subject: soc/intel/jasperlake: Add per-SKU power limits
......................................................................
Patch Set 11:
(1 comment)
File src/mainboard/google/dedede/variants/dibbi/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/75679/comment/79cbf305_f0213701 :
PS11, Line 34:
Also JSL_N6000_6W_CORE?
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Change subject: mb/google/brya/var/gothrax: Generate RAM IDs for new memory parts
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
LGTM, differ to AP FW owners to approve. Thanks!
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Change subject: arch/x86/smbios: Add weak function for BIOS Vendor in SMBIOS Type0
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> The SMBIOS specification isn't clear on what they mean by "BIOS Vendor's Name", but it seems reasona […]
Patch like this?
ifdef CONFIG_BIOS_VENDOR
t->vendor = smbios_add_string(t->eos, CONFIG_BIOS_VENDOR);
#else
t->vendor = smbios_add_string(t->eos, "coreboot");
#endif /* CONFIG_BIOS_VENDOR */
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Change subject: mb/google/rex: Set AUX orientation at SoC to follow cable for anx7452
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/jasperlake: Add per-SKU power limits
......................................................................
Patch Set 11:
(2 comments)
File src/mainboard/google/dedede/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/75679/comment/99959528_01645778 :
PS10, Line 171:
> remove one tab (and same for all the overridetrees)
Done
File src/mainboard/google/dedede/variants/dibbi/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/75679/comment/f04ccfa0_9fb965df :
PS10, Line 29: register "power_limits_config[JSL_N4500_6W_CORE]" = "{
> This overrides the whole struct, so you need to set PL1 and PL2 as well.
Done
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Hello Reka Norman, Ryan Lin, Subrata Banik, Zhuohao Lee, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75679?usp=email
to look at the new patch set (#11).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/jasperlake: Add per-SKU power limits
......................................................................
soc/intel/jasperlake: Add per-SKU power limits
Add JSL SKUs ID and add PLx from JSL PDG in project devicetree.
BUG=b:281479111
TEST=emerge-dedede coreboot and read correct value on dibbi
Signed-off-by: Chia-Ling Hou <chia-ling.hou(a)intel.com>
Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd
---
M src/mainboard/google/dedede/variants/baseboard/devicetree.cb
M src/mainboard/google/dedede/variants/blipper/overridetree.cb
M src/mainboard/google/dedede/variants/dibbi/overridetree.cb
M src/mainboard/google/dedede/variants/drawcia/overridetree.cb
M src/mainboard/google/dedede/variants/haboki/overridetree.cb
M src/mainboard/google/dedede/variants/kracko/overridetree.cb
M src/mainboard/google/dedede/variants/lalala/overridetree.cb
M src/mainboard/google/dedede/variants/lantis/overridetree.cb
M src/mainboard/google/dedede/variants/madoo/overridetree.cb
M src/mainboard/google/dedede/variants/magolor/overridetree.cb
M src/mainboard/google/dedede/variants/metaknight/overridetree.cb
M src/mainboard/google/dedede/variants/sasukette/overridetree.cb
M src/mainboard/google/dedede/variants/shotzo/overridetree.cb
M src/mainboard/google/dedede/variants/storo/overridetree.cb
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/systemagent.c
17 files changed, 187 insertions(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/75679/11
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Change subject: mb/google/rex: Set AUX orientation at SoC to follow cable for anx7452
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/rex/variants/rex0/variant.c:
https://review.coreboot.org/c/coreboot/+/75827/comment/2b998314_338097dd :
PS1, Line 12: TCP_AUX_FOLLOW_CC2
> nit: if you don't use this, you don't define it.
Done
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