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Change subject: mb/google/nissa/var/joxer: Disable storage devices based on fw_config
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/brya/variants/joxer/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/75743/comment/f7a5e5f8_15056a78 :
PS5, Line 7: ramstage-$(CONFIG_FW_CONFIG) += variant.c
> Are you sure it should be done like that? variant. […]
Oh, nice catch.
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Change subject: src/arch/x86/smbios.c: Change smbios_fill_dimm_serial_number function to weak
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> I know you mean the definition in SPD spec. […]
I don't understand what you are trying to do here. Change the serial number format or change the content? If you just want override the serial number, you can change it in several place,change cbmem_info, change it before you pass the SPD info to FSP, change it after the FSP return the meminfo_hob.
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Change subject: mb/google/nissa/var/joxer: Disable storage devices based on fw_config
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/brya/variants/joxer/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/75743/comment/cdbe4d9b_6fdf0f62 :
PS5, Line 7: ramstage-$(CONFIG_FW_CONFIG) += variant.c
Are you sure it should be done like that? variant.c also contains `get_wifi_sar_cbfs_filename()`, which does not depend on fw_config, so without it the default WIFI SAR file name will be used instead.
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Change subject: src/arch/x86/smbios.c: Change smbios_fill_dimm_serial_number function to weak
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> This is SMBIOS spec. […]
I know you mean the definition in SPD spec. But it seems that most dimms use SPD Bytes 512~520 to form the serial number on their dimm label. It's not our own format. We can't change the serial number on the dimm label. Please correct me, if I've misunderstood the serial number definition.
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Hello Kapil Porwal, Sukumar Ghorai, Tarun Tuli, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75822?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Code-Review+1 by Sukumar Ghorai, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/meteorlake: Disable ACPI PM timer using IOE.PMC
......................................................................
soc/intel/meteorlake: Disable ACPI PM timer using IOE.PMC
This patch disables the ACPI PM timer which is necessary for XTAL OSC
shutdown. Also, disabling ACPI PM timer switches off TCO.
BUG=b:274744845
TEST=Able to boot and verify S0ix is working even with EC reset and
cold boot scenarios.
w/o this cl:
> iotools mmio_read32 0xfe4018fc
0x0
w/ this cl:
> iotools mmio_read32 0xfe4018fc
0x2
Change-Id: Ibb6e145f67dba7270e0a322ef414bf1cb09c5eda
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/meteorlake/include/soc/iomap.h
M src/soc/intel/meteorlake/include/soc/pm.h
M src/soc/intel/meteorlake/pmc.c
M src/soc/intel/meteorlake/pmutil.c
4 files changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/75822/2
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Change subject: mb/google/rex: Set AUX orientation at SoC to follow cable for anx7452
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/jasperlake: Add per-SKU power limits
......................................................................
Patch Set 11:
(1 comment)
File src/mainboard/google/dedede/variants/dibbi/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/75679/comment/d82bc604_08db11b0 :
PS11, Line 34:
> Also JSL_N6000_6W_CORE?
Actually Dibbi don't have N6000 sku. Do I need to add N6000 at here too?
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Change subject: mb/google/brya/var/volmar: Add Micron MT53E2G32D4NQ-046 WT:C SPD
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Patch Set 2: Code-Review+2
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