coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: add audio to test
by Rui Zhou (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli. Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75833?usp=email ) Change subject: add audio to test ...................................................................... add audio to test Change-Id: I24a1a99378e51614397095461a87727f75543883 --- M src/mainboard/google/rex/variants/screebo/overridetree.cb 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/75833/1 diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index d66d7bd..bcc592a 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -1,7 +1,7 @@ fw_config field AUDIO 0 1 option AUDIO_UNKNOWN 0 - option ALC1019_ALC5682I_I2S 1 + option MAX98360_ALC5682I_I2S 1 end field DB_CONFIG 2 4 option DB_UNKNOWN 0 @@ -364,7 +364,7 @@ register "property_list[0].name" = ""realtek,jd-src"" register "property_list[0].integer" = "1" device i2c 1a on - probe AUDIO ALC1019_ALC5682I_I2S + probe AUDIO MAX98360_ALC5682I_I2S end end end @@ -488,11 +488,13 @@ end end device ref hda on - chip drivers/generic/alc1015 - register "hid" = ""RTL1019"" - register "sdb" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B07)" + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D04)" + register "sdmode_delay" = "5" device generic 0 on - probe AUDIO ALC1019_ALC5682I_I2S + probe AUDIO MAX98360_ALC5682I_I2S end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/75833?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24a1a99378e51614397095461a87727f75543883 Gerrit-Change-Number: 75833 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/rex/var/screebo: rp2 change to rp1 and rp3
by Rui Zhou (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Kapil Porwal, Kun Liu, Rui Zhou, Tarun Tuli. Hello Kapil Porwal, Kun Liu, Subrata Banik, Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75832?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Kun Liu Change subject: mb/google/rex/var/screebo: rp2 change to rp1 and rp3 ...................................................................... mb/google/rex/var/screebo: rp2 change to rp1 and rp3 change to enable both rp1 and rp3 for TCP1 and TCP3 BUG=b:286187816 BRANCH=none TEST=emerge-rex coreboot and verify TBT works. Change-Id: I1013d26c705f2a3f9378d944bd863d94f319d36c Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/rex/variants/screebo/overridetree.cb 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/75832/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75832?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1013d26c705f2a3f9378d944bd863d94f319d36c Gerrit-Change-Number: 75832 Gerrit-PatchSet: 2 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-CC: Jinfang Mao <maojinfang(a)huaqin.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: soc/amd/block/ivrs: Add NULL check for IVRS
by Felix Singer (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Naresh Solanki, Raul Rangel. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75506?usp=email ) Change subject: soc/amd/block/ivrs: Add NULL check for IVRS ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeb0ea3bcaa3512a93500588ad4f11046edee61f Gerrit-Change-Number: 75506 Gerrit-PatchSet: 3 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 15 Jun 2023 01:38:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/brya/var/taeko: Enable CsPiStartHighinEct
by Joey Peng (Code Review) 15 Jun '23

15 Jun '23

Joey Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75825?usp=email ) Change subject: mb/google/brya/var/taeko: Enable CsPiStartHighinEct ...................................................................... mb/google/brya/var/taeko: Enable CsPiStartHighinEct Enable CsPiStartHighinEct to fix MRC Cache fail issue BUG=b:279835630 TEST=Pass MRC Cache test with toolkit 1000 times Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Change-Id: If546b1259597c8025902e8f31b659ebee6f98eb3 --- M src/mainboard/google/brya/variants/taeko/memory.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/75825/1 diff --git a/src/mainboard/google/brya/variants/taeko/memory.c b/src/mainboard/google/brya/variants/taeko/memory.c index e9e8533..e43aa4d 100644 --- a/src/mainboard/google/brya/variants/taeko/memory.c +++ b/src/mainboard/google/brya/variants/taeko/memory.c @@ -64,6 +64,8 @@ }, .ect = 1, /* Enable Early Command Training */ + + .CsPiStartHighinEct = 1, }; const struct mb_cfg *variant_memory_params(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/75825?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If546b1259597c8025902e8f31b659ebee6f98eb3 Gerrit-Change-Number: 75825 Gerrit-PatchSet: 1 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
by Eric Lai (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Arthur Heymans, Paul Menzel, Subrata Banik, Tarun Tuli. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75756?usp=email ) Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config ...................................................................... Patch Set 11: (1 comment) File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/75756/comment/86b936ac_2d4b841b : PS11, Line 268: below MEMORY_TYPE_DDR4 or exceed MEMORY_TYPE_HBM3 > don't kw if this statement is valuable only to reflect the code. wait Arthur comment and I'll change again. -- To view, visit https://review.coreboot.org/c/coreboot/+/75756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b5ca1f4a59598531a6cba500672c2717f2a7b00 Gerrit-Change-Number: 75756 Gerrit-PatchSet: 11 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 15 Jun 2023 01:05:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: ec/google/chromeec: Use mux_conn to get the right USB port
by Eric Lai (Code Review) 15 Jun '23

15 Jun '23

Eric Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75824?usp=email ) Change subject: ec/google/chromeec: Use mux_conn to get the right USB port ...................................................................... ec/google/chromeec: Use mux_conn to get the right USB port get_usb_port_references only work while all the port assign by order. If the port assign cross ports like mux[0] use USB3 and mux[1] use USB1, it still connect mux[0] to USB1. BUG=b:286328285 TEST=check ACPI can have right USB port in EC CON. before patch: Package (0x02) { "usb2-port", \_SB.PCI0.XHCI.RHUB.HS01 }, Package (0x02) { "usb3-port", \_SB.PCI0.TXHC.RHUB.SS01 }, after patch: Package (0x02) { "usb2-port", \_SB.PCI0.XHCI.RHUB.HS01 }, Package (0x02) { "usb3-port", \_SB.PCI0.TXHC.RHUB.SS03 }, Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I058c6cc0fea6758bfaafdd163b5da2c7f75daf8a --- M src/ec/google/chromeec/ec_acpi.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/75824/1 diff --git a/src/ec/google/chromeec/ec_acpi.c b/src/ec/google/chromeec/ec_acpi.c index 53a4e75..da772d4 100644 --- a/src/ec/google/chromeec/ec_acpi.c +++ b/src/ec/google/chromeec/ec_acpi.c @@ -12,6 +12,7 @@ #include <ec/google/common/dptf.h> #include "chip.h" +#include "drivers/intel/pmc_mux/conn/chip.h" #include "ec.h" #include "ec_commands.h" @@ -182,6 +183,13 @@ usb4_port = NULL; get_usb_port_references(i, &usb2_port, &usb3_port, &usb4_port); + if (CONFIG(DRIVERS_INTEL_PMC)) { + struct drivers_intel_pmc_mux_conn_config *conn_config = + config->mux_conn[i]->chip_info; + usb2_port = conn_config->usb2_port; + usb3_port = conn_config->usb3_port; + } + get_pld_from_usb_ports(&pld, usb2_port, usb3_port, usb4_port); struct typec_connector_class_config typec_config = { -- To view, visit https://review.coreboot.org/c/coreboot/+/75824?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I058c6cc0fea6758bfaafdd163b5da2c7f75daf8a Gerrit-Change-Number: 75824 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/myst: Update WWAN usb entry
by Eric Lai (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Jon Murphy, Karthik Ramasubramanian, Tim Van Patten. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75819?usp=email ) Change subject: mb/google/myst: Update WWAN usb entry ...................................................................... Patch Set 2: (2 comments) File src/mainboard/google/myst/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/75819/comment/f02fdb12_d92279ba : PS2, Line 258: probe DAUGHTERBOARD DB_B > Is this change required also? […] Yes, you need change fw config accordingly. Otherwise SKUA DB will have two USB3 ebtry. https://review.coreboot.org/c/coreboot/+/75819/comment/fb72fd68_7270626b : PS2, Line 269: usb3_port3 > go/myst-schematic states WWAN is connected to USB-7. […] I confirmed with HW Chris, USB7 is reserved. -- To view, visit https://review.coreboot.org/c/coreboot/+/75819?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ad3973a9519350794a661ad00f71c0eb34edfba Gerrit-Change-Number: 75819 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 00:04:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/jasperlake: Add per-SKU power limits
by Reka Norman (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: ChiaLing, Paul Menzel, Ryan Lin, Subrata Banik, Sumeet R Pawnikar, Zhuohao Lee. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75679?usp=email ) Change subject: soc/intel/jasperlake: Add per-SKU power limits ...................................................................... Patch Set 10: (2 comments) File src/mainboard/google/dedede/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/75679/comment/726d130d_8279aa5c : PS10, Line 171: remove one tab (and same for all the overridetrees) File src/mainboard/google/dedede/variants/dibbi/overridetree.cb: https://review.coreboot.org/c/coreboot/+/75679/comment/83e50238_1d92c023 : PS10, Line 29: register "power_limits_config[JSL_N4500_6W_CORE]" = "{ This overrides the whole struct, so you need to set PL1 and PL2 as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/75679?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic086e32a2692f4f5f9b661585b216fa207fc56fd Gerrit-Change-Number: 75679 Gerrit-PatchSet: 10 Gerrit-Owner: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Ryan Lin <ryan.lin(a)intel.com> Gerrit-Attention: ChiaLing <chia-ling.hou(a)intel.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 23:38:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/rex/var/rex0: add HID over SPI ACPI driver
by Elyes Haouas (Code Review) 15 Jun '23

15 Jun '23

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74885?usp=email ) Change subject: mb/google/rex/var/rex0: add HID over SPI ACPI driver ...................................................................... mb/google/rex/var/rex0: add HID over SPI ACPI driver Add driver to support ELAN touchscreen using SPI for rex * See "HID Over SPI Protocol Specification" section 5.2 - ACPI enum * https://www.microsoft.com/en-us/download/details.aspx?id=103325 BUG=b:278783755 TEST=Kernel driver is able to communicate with device. Also tested S0ix, ran 'suspend_stress_test -c 1' - no issues in suspend/resume. Signed-off-by: Eran Mitrani <mitrani(a)google.com> Change-Id: Id51d385ce350cef23da4184b044c74569f4dd3f0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74885 Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- A src/mainboard/google/rex/variants/rex0/include/variant/acpi/hid_spi_elan.asl 1 file changed, 152 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Elyes Haouas: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/rex/variants/rex0/include/variant/acpi/hid_spi_elan.asl b/src/mainboard/google/rex/variants/rex0/include/variant/acpi/hid_spi_elan.asl new file mode 100644 index 0000000..cc8cb93 --- /dev/null +++ b/src/mainboard/google/rex/variants/rex0/include/variant/acpi/hid_spi_elan.asl @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * ELAN7B18UH - HID over SPI + * See "HID Over SPI Protocol Specification" section 5.2 - ACPI enum + * https://www.microsoft.com/en-us/download/details.aspx?id=103325 + + * NOTES: + * 1. Make sure TOUCH_SCR_IRQ is defined according to the board's schematics + * 2. Include this file under the scope for the correct SPI, e.g.: + * Scope (\_SB.PCI0.SPI0) + * { + * #include <variant/acpi/hid_spi_elan.asl> + * } + */ + +Device(TCSC) { + Name (_HID, "ELAN9006") /* VendorID + DeviceID - <VVVVdddd> */ + Name (_CID, "PNP0C51") /* Compatible ID - PNP0C51 */ + Name (_SUB, "ELAN0732") /* SubVendorID + SubSystemID - <VVVVssss> */ + Name (_HRV, 0x0001) /* Hardware Revision Number - 2 bytes */ + + Method (_STA, 0) + { + Return (0xf) + } + + Name (_CRS, ResourceTemplate () { + SpiSerialBusV2 ( + 0, /* DeviceSelection */ + PolarityLow, /* DeviceSelectionPolarity */ + FourWireMode, /* WireMode */ + 8, /* DataBitLength */ + ControllerInitiated, /* SlaveMode */ + 0x0B71B00, /* ConnectionSpeed (12MHz) */ + ClockPolarityLow, /* ClockPolarity */ + ClockPhaseFirst, /* ClockPhase */ + "\\_SB.PCI0.SPI0", /* ResourceSource */ + 0, /* ResourceSourceIndex */ + ResourceConsumer, /* ResourceUsage */ + ) + Interrupt(ResourceConsumer, Level, ActiveLow, Shared) + { + TOUCH_SCR_IRQ + } + }) + + /* _DSM - Device-Specific Method */ + /* Arg0: UUID Unique function identifier */ + /* Arg1: Integer Revision ID - Will be 3 for HidSpi V1 */ + /* Arg2: Integer Function Index (0 = Return Supported Functions) */ + /* Arg3: Package Parameters */ + + Method (_DSM, 4) { + /* HIDSPI UUID */ + If(Arg0 == ToUUID("6E2AC436-0FCF-41AF-A265-B32A220DCFAB")) { + + /* Switch on the function index */ + switch(ToInteger(Arg2)) { + case(0) { + /* Switch on the revision level */ + switch(ToInteger(Arg1)) { + case (3) { + /* HidSpi v1: Functions 0-6 */ + Return(Buffer(One) { 0x7F }) + } + default { + /* Unsupported revision */ + Return(Buffer(One) { 0x00 }) + } + } + } + case(1) { + /* Elan Input Report Header address - 0x1000*/ + Return (0x1000) + } + case(2) { + /* Elan Input Report Body address - 0x1100*/ + Return (0x1100) + } + case(3) { + /* Elan Output Report Header address - 0x2000 */ + Return (0x2000) + } + case(4) { + /* Read opcode */ + Return (Buffer(1) {0x0B}) + } + case(5) { + /* Write opcode */ + Return (Buffer(1) {0x02}) + } + case(6) { + /* Flags */ + Return (0x0000) + } + default { + /* Unsupported function index */ + Return (Buffer() {0}) + } + } + } + else { + /* No functions are supported for this UUID. */ + return (Buffer() {0}) + } + } + + Method(_RST, 0, Serialized) { + /* De-assert the reset signal for 20ms */ + CTXS(GPP_C01) + Sleep(20) + STXS(GPP_C01) + } + + Name (_PR0, Package (0x01) /* Power Resources for D0 */ + { + PR00 + }) + + Name (_PR3, Package (0x01) /* Power Resources for D3hot */ + { + PR00 + }) + + PowerResource (PR00, 0x00, 0x0000) + { + Method (_STA, 0, NotSerialized) /* Status */ + { + Return (1) + } + + Method (_ON, 0, Serialized) /* Power On */ + { + CTXS (GPP_C01) + STXS (GPP_C00) + Sleep (1) + STXS (GPP_C01) + Sleep (20) + STXS (GPP_C06) + } + + Method (_OFF, 0, Serialized) /* Power Off */ + { + CTXS (GPP_C06) + Sleep (2) + CTXS (GPP_C01) + Sleep (2) + CTXS (GPP_C00) + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/74885?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id51d385ce350cef23da4184b044c74569f4dd3f0 Gerrit-Change-Number: 74885 Gerrit-PatchSet: 19 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/amd/birman/devicetree_phoenix: update USB PHY settings
by Felix Held (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Fred Reitberger, Jason Glenesk. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75823?usp=email ) Change subject: mb/amd/birman/devicetree_phoenix: update USB PHY settings ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75823/comment/8f6c7042_13e7fc27 : PS1, Line 16: TEST=None would be good to test this on the board -- To view, visit https://review.coreboot.org/c/coreboot/+/75823?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ddfa2594d66b21582282ab8509c921a6e81a93f Gerrit-Change-Number: 75823 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 14 Jun 2023 22:18:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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