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Hello Dinesh Gehlot, Eric Lai, Kangheui Won, Kapil Porwal, Tarun Tuli, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/cmn/cse: Always save CSE RW version to CBMEM
......................................................................
soc/intel/cmn/cse: Always save CSE RW version to CBMEM
This patch renames `cse_store_rw_fw_version` function that store
currently running CSE RW FW version inside CBMEM.
Additionally, perform the CSE RW FW storing operation unconditionally.
TEST=Able to build and boot google/marasov.
Change-Id: Iba85807b7d9e6f067b5b628c6fa062fab5c485e0
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/75768/6
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Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75819?usp=email )
Change subject: mb/google/myst: Update WWAN usb entry
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/myst/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/75819/comment/13d266da_00771caf :
PS2, Line 269: usb3_port3
go/myst-schematic states WWAN is connected to USB-7. Is that wrong?
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Change subject: src/soc/intel/meteorlake: disable acpi timer for xtal shutdown
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/meteorlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/75814/comment/96ecb599_c5fa352d :
PS1, Line 619: 0
> > we don't need to set this UPD. […]
PMC MMIO + offset 0x18FC : disable ACPI driver is working fine for SoC-PMC.
We need the similar settings for IOE-PMC.
Hence best solution is to disable from FSP parameter.
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Change subject: arch/x86/smbios: Add weak function for BIOS Vendor in SMBIOS Type0
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
I want to check the spec before deciding on this...
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Change subject: soc/amd/block/ivrs: Add NULL check for IVRS
......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/block/acpi/ivrs.c:
https://review.coreboot.org/c/coreboot/+/75506/comment/270cbb99_8e7c2d82 :
PS2, Line 339: return (unsigned long)ivrs;
> Why not just `return 0`?
Done
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Change subject: drv/i2c/pi608gp: Fix style
......................................................................
Patch Set 1: Code-Review+2
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Change subject: drv/i2c/pi608gp: Fix types
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Patch Set 6: Code-Review+2
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Change subject: mb/siemens/mc_ehl3/devicetree.cb: Disable USB 3.0 port 1
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash
......................................................................
Patch Set 8: Code-Review+1
(8 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68987/comment/75587457_69d91dbf :
PS3, Line 13: This change allows to
: keep PCIe 5.0 functioning even if CSME/HECI is not functional.
> Changed to PCIe 5. […]
Done
Patchset:
PS8:
One typo caught by Jenkins left.
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/68987/comment/a648bc57_61bd9da9 :
PS7, Line 532: Set this option to avoid communication with ME to fetch the PCIe 5.0
: HSPHY firmware on each boot
> Rephrased
Done
File src/soc/intel/alderlake/hsphy.c:
https://review.coreboot.org/c/coreboot/+/68987/comment/f6688501_74b1fd9f :
PS3, Line 233: if (hsphy_cache_valid(hsphy_fw_cache)) {
> I have changed the flow to try HECI command so we can fetch the newest HSPHY FW and cache it if need […]
Done
https://review.coreboot.org/c/coreboot/+/68987/comment/128e959b_22256349 :
PS3, Line 234: printk(BIOS_INFO, "HSPHY: HSPHY cache valid, skipping update\n");
> Indeed, Krystian also pointed it out. […]
Done
File src/soc/intel/alderlake/hsphy.c:
https://review.coreboot.org/c/coreboot/+/68987/comment/7f403d59_0f0803d2 :
PS7, Line 378: printk(BIOS_ERR, "Failed to load HSPHY FW from cache\n");
> Fixed
Done
https://review.coreboot.org/c/coreboot/+/68987/comment/a05546aa_febb84ab :
PS7, Line 391: printk(BIOS_ERR, "%s: CSME not enabled or not visible, but required\n",
> Fixed
Done
https://review.coreboot.org/c/coreboot/+/68987/comment/43cef9b8_cd60ed8e :
PS7, Line 400: printk(BIOS_ERR, "Failed to load HSPHY FW from cache\n");
> Fixed
Done
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