coreboot-gerrit June 2023

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[S] Change in coreboot[master]: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable option
by Felix Singer (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Arthur Heymans, Elyes Haouas, Eric Lai, Jan Samek, Mario Scheithauer, Michael Niewöhner, Michał Żygowski, Nico Huber, Piotr Król. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75871?usp=email ) Change subject: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable option ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Er -- To view, visit https://review.coreboot.org/c/coreboot/+/75871?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Gerrit-Change-Number: 75871 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Fri, 16 Jun 2023 00:23:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable option
by Felix Singer (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Michael Niewöhner, Michał Żygowski, Piotr Król. Hello Michael Niewöhner, Michał Żygowski, Piotr Król, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75871?usp=email to look at the new patch set (#3). Change subject: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable option ...................................................................... [RFC] soc/intel/skylake: Use boolean type for s0ix_enable option Mainboards which use that option are found by this line: grep -Er "SOC_INTEL_(SKYLAKE|KABYLAKE|SKYLAKE_LGA1151_V2)" mainboard | cut -d ':' -f 1 | awk -F '[/]' '{print $1"/"$2"/"$3}' | xargs grep -r "s0ix_enable" Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/soc/intel/skylake/chip.h 12 files changed, 13 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/75871/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/75871?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Gerrit-Change-Number: 75871 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/brya/var/gothrax: Generate RAM IDs for new memory parts
by Kangheui Won (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Reka Norman, Tarun Tuli, Yunlong Jia. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75834?usp=email ) Change subject: mb/google/brya/var/gothrax: Generate RAM IDs for new memory parts ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75834?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib16846f7b2061ee254db674ac7bac66c9b9f4e70 Gerrit-Change-Number: 75834 Gerrit-PatchSet: 2 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Comment-Date: Thu, 15 Jun 2023 23:55:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/brya/var/volmar: Add Micron MT53E2G32D4NQ-046 WT:C SPD
by Nick Vaccaro (Code Review) 16 Jun '23

16 Jun '23

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75826?usp=email ) Change subject: mb/google/brya/var/volmar: Add Micron MT53E2G32D4NQ-046 WT:C SPD ...................................................................... mb/google/brya/var/volmar: Add Micron MT53E2G32D4NQ-046 WT:C SPD Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM. BUG=b:216393391 TEST=build pass Change-Id: I3797de01629fdb5ace4c610943d88db525da112b Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75826 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/volmar/memory/Makefile.inc M src/mainboard/google/brya/variants/volmar/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/volmar/memory/mem_parts_used.txt 3 files changed, 3 insertions(+), 0 deletions(-) Approvals: David Wu: Looks good to me, approved Tyler Wang: Looks good to me, approved build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/volmar/memory/Makefile.inc b/src/mainboard/google/brya/variants/volmar/memory/Makefile.inc index e91dd92..077a53a 100644 --- a/src/mainboard/google/brya/variants/volmar/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/volmar/memory/Makefile.inc @@ -6,3 +6,4 @@ SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, H54G46CYRBX267, K4U6E3S4AB-MGCL SPD_SOURCES += spd/lp4x/set-0/spd-3.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:B, H54G56CYRBX247, K4UBE3D4AB-MGCL +SPD_SOURCES += spd/lp4x/set-0/spd-7.hex # ID = 2(0b0010) Parts = MT53E2G32D4NQ-046 WT:C diff --git a/src/mainboard/google/brya/variants/volmar/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/volmar/memory/dram_id.generated.txt index ca0069f..f2fc126 100644 --- a/src/mainboard/google/brya/variants/volmar/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/volmar/memory/dram_id.generated.txt @@ -10,3 +10,4 @@ H54G56CYRBX247 1 (0001) K4U6E3S4AB-MGCL 0 (0000) K4UBE3D4AB-MGCL 1 (0001) +MT53E2G32D4NQ-046 WT:C 2 (0010) diff --git a/src/mainboard/google/brya/variants/volmar/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/volmar/memory/mem_parts_used.txt index a188982..eab1b17 100644 --- a/src/mainboard/google/brya/variants/volmar/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/volmar/memory/mem_parts_used.txt @@ -4,3 +4,4 @@ H54G56CYRBX247 K4U6E3S4AB-MGCL K4UBE3D4AB-MGCL +MT53E2G32D4NQ-046 WT:C -- To view, visit https://review.coreboot.org/c/coreboot/+/75826?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3797de01629fdb5ace4c610943d88db525da112b Gerrit-Change-Number: 75826 Gerrit-PatchSet: 3 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: mb/google/brya/var/volmar: Add Micron MT53E2G32D4NQ-046 WT:C SPD
by Nick Vaccaro (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Lucas Chen, Ren Kuo, Tarun Tuli, YH Lin. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75826?usp=email ) Change subject: mb/google/brya/var/volmar: Add Micron MT53E2G32D4NQ-046 WT:C SPD ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75826?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3797de01629fdb5ace4c610943d88db525da112b Gerrit-Change-Number: 75826 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Lucas Chen <lucas.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 23:52:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [WIP] soc/intel/skylake: Use boolean type for s0ix_enable option
by Felix Singer (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Michael Niewöhner, Michał Żygowski, Piotr Król. Hello Michael Niewöhner, Michał Żygowski, Piotr Król, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75871?usp=email to look at the new patch set (#2). Change subject: [WIP] soc/intel/skylake: Use boolean type for s0ix_enable option ...................................................................... [WIP] soc/intel/skylake: Use boolean type for s0ix_enable option Mainboards which use that option are found by this line: grep -Er "SOC_INTEL_(SKYLAKE|KABYLAKE|SKYLAKE_LGA1151_V2)" mainboard | cut -d ':' -f 1 | awk -F '[/]' '{print $1"/"$2"/"$3}' | xargs grep -r "s0ix_enable" Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/soc/intel/skylake/chip.h 12 files changed, 13 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/75871/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75871?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Gerrit-Change-Number: 75871 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: soc/intel/spr-sp: Remove HWP related settings
by Felix Singer (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Nico Huber, Paul Menzel, Tim Chu, Ziang Wang. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75741?usp=email ) Change subject: soc/intel/spr-sp: Remove HWP related settings ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Usually I would say peace for coreboot developers, because multiple places to […] I guess the current implementation works as intended. So why change something what works and give control to a blob when it's not needed? Especially since the author doesn't give a reason and the current implementation couldn't work at all. -- To view, visit https://review.coreboot.org/c/coreboot/+/75741?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4ff63cbff0dffb4cd65fdfa814eda85964130ee Gerrit-Change-Number: 75741 Gerrit-PatchSet: 2 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 23:50:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [WIP] soc/intel/skylake: Use boolean type for s0ix_enable option
by Felix Singer (Code Review) 16 Jun '23

16 Jun '23

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75871?usp=email ) Change subject: [WIP] soc/intel/skylake: Use boolean type for s0ix_enable option ...................................................................... [WIP] soc/intel/skylake: Use boolean type for s0ix_enable option Mainboards which use that option are found by this line: grep -Er "SOC_INTEL_(SKYLAKE|KABYLAKE|SKYLAKE_LGA1151_V2)" mainboard | cut -d ':' -f 1 | awk -F '[/]' '{print $1"/"$2"/"$3}' | xargs grep -r "s0ix_enable" Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/acer/aspire_vn7_572g/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb 11 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/75871/1 diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index 38a56ca..1521501 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -311,7 +311,7 @@ register "gpe0_dw2" = "GPP_E" # 11:8 in pwrmbase+0120h # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = true register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" # 11:10 in A4h-A7h register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" # 5:4 in A4h-A7h diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 74c601a..e19e2386 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -62,7 +62,7 @@ register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = true # FSP Configuration register "SataSalpSupport" = "0" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 4c759f6..ee3c86b 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -37,7 +37,7 @@ register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = true # Disable Command TriState register "CmdTriStateDis" = "1" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 2e3953a..717ab54 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -28,7 +28,7 @@ register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = true # FSP Configuration register "SataSalpSupport" = "0" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index aa905d1..6a34241 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -28,7 +28,7 @@ register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = true # FSP Configuration register "SataSalpSupport" = "0" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 07363fd..27a9bb9 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -28,7 +28,7 @@ register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = true # FSP Configuration register "SataSalpSupport" = "0" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index b381a25..5f322b1 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -30,7 +30,7 @@ register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = true # Disable Command TriState register "CmdTriStateDis" = "1" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 8be97c8..bc2d4a0 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -37,7 +37,7 @@ register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = true # Disable Command TriState register "CmdTriStateDis" = "1" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index a20c197..fbe6c1f 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -28,7 +28,7 @@ register "dptf_enable" = "1" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = true # FSP Configuration register "SataSalpSupport" = "0" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 4e4cbac..1f17fb1 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -6,7 +6,7 @@ register "deep_s5_enable_ac" = "1" register "deep_s5_enable_dc" = "1" register "deep_sx_config" = "DSX_EN_WAKE_PIN | DSX_DIS_AC_PRESENT_PD" - register "s0ix_enable" = "1" + register "s0ix_enable" = true register "gpe0_dw0" = "GPP_B" register "gpe0_dw1" = "GPP_D" diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index b4a08bf..76f7580 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -20,7 +20,7 @@ register "serirq_mode" = "SERIRQ_CONTINUOUS" # Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch - register "s0ix_enable" = "1" + register "s0ix_enable" = true register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" -- To view, visit https://review.coreboot.org/c/coreboot/+/75871?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Gerrit-Change-Number: 75871 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/intel/spr-sp: Remove HWP related settings
by Nico Huber (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Singer, Johnny Lin, Lean Sheng Tan, Paul Menzel, Tim Chu, Ziang Wang. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75741?usp=email ) Change subject: soc/intel/spr-sp: Remove HWP related settings ...................................................................... Patch Set 2: (2 comments) Patchset: PS2: > Then why do you give a +1? That was already answered: "dont want to over engineering it. What do the rest think?". That's basically what the description of +1 says "Somebody else must approve". However, I think using an abstract UPD interface for a rather simple thing (if it's as simple as the current implementation) seems like the actual over engineering. PS2: > What's the advantage of letting FSP doing it? Usually I would say peace for coreboot developers, because multiple places to configure something and conflicting settings can cause a lot of trouble. However, coreboot currently doesn't expose the `CpuPmProcessorHWPMEnable` UPD. And this change doesn't even have a follow-up that would make use of it. So the change alone seems odd. IMO, such things are much easier discussed when the whole implementation is visible on Gerrit. This change alone changes behavior and we don't even know to what (if coreboot doesn't set the UPD). -- To view, visit https://review.coreboot.org/c/coreboot/+/75741?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4ff63cbff0dffb4cd65fdfa814eda85964130ee Gerrit-Change-Number: 75741 Gerrit-PatchSet: 2 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 23:29:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: intelblocks/pep: Restrict TBT displays(DPOF) on S0ix transition to FWCM.
by Paul Menzel (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Balaji Manigandan, Jamie Ryu, Subrata Banik, Tarun Tuli, Usha P, Utkarsh H Patel, Utkarsh H Patel, Vikrant Jadeja. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75717?usp=email ) Change subject: intelblocks/pep: Restrict TBT displays(DPOF) on S0ix transition to FWCM. ...................................................................... Patch Set 3: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/75717/comment/d7afbf8a_00826245 : PS3, Line 7: displays(DPOF) Please add a space before the (. https://review.coreboot.org/c/coreboot/+/75717/comment/335812c1_329c2928 : PS3, Line 9: IOM needed to be notified about DPOF(TBT Displays OFF) only when Firmware connection Manager in use during S0ix Entry/Exit. Where is that documented? https://review.coreboot.org/c/coreboot/+/75717/comment/5dac56eb_54dda8e0 : PS3, Line 9: Firmware connection Manager What is that? https://review.coreboot.org/c/coreboot/+/75717/comment/c9e82ffe_fbd28c71 : PS3, Line 9: Manager in … is in … https://review.coreboot.org/c/coreboot/+/75717/comment/b46fe2ad_dc4d5762 : PS3, Line 9: DPOF(TBT Displays OFF) only Please add a space before the (. https://review.coreboot.org/c/coreboot/+/75717/comment/95343ca8_04564fe0 : PS3, Line 9: needed needs https://review.coreboot.org/c/coreboot/+/75717/comment/b110b6a7_bbb47e73 : PS3, Line 10: Please add a bug number. -- To view, visit https://review.coreboot.org/c/coreboot/+/75717?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I110fb971846f110e7d93a524ceda3bf4bfc15c13 Gerrit-Change-Number: 75717 Gerrit-PatchSet: 3 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Reviewer: Vikrant Jadeja Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Vikrant Jadeja Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 23:18:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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