coreboot-gerrit June 2023

coreboot-gerrit@coreboot.org

1 participants
5387 discussions

[XS] Change in coreboot[master]: soc/intel/apollolake: Switch to snake case for SataPortsHotPlug
by Felix Singer (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Mario Scheithauer, Sean Rhodes. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75852?usp=email ) Change subject: soc/intel/apollolake: Switch to snake case for SataPortsHotPlug ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75852?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8fc8b30ac2c182ffaf2dee37e0116e27071b6a2c Gerrit-Change-Number: 75852 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 22:16:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/apollolake: Fix FSP SATA speed limit configuraion
by Felix Singer (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Mario Scheithauer, Sean Rhodes, Werner Zeh. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75820?usp=email ) Change subject: soc/intel/apollolake: Fix FSP SATA speed limit configuraion ...................................................................... Patch Set 7: (3 comments) Patchset: PS7: Is there anything on which the SATA speed depends on or what could limit it? File src/soc/intel/apollolake/ahci.c: https://review.coreboot.org/c/coreboot/+/75820/comment/11040ce8_865b1a1a : PS7, Line 12: if (speed == SATA_DEFAULT) : nit: I wouldn't care about default values and just write the bits in any case. File src/soc/intel/apollolake/include/soc/ahci.h: https://review.coreboot.org/c/coreboot/+/75820/comment/f62be4b8_9d93031b : PS7, Line 11: 0x00F00000 make it lowercase -- To view, visit https://review.coreboot.org/c/coreboot/+/75820?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f55f40941fa618e7de13a5cefe9e17ae34c5c99 Gerrit-Change-Number: 75820 Gerrit-PatchSet: 7 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 22:12:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: UNTESTED acpi: Add ECAM region below PNP0C02 device in SSDT
by Nico Huber (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Angel Pons, Arthur Heymans, Jeff Daly, Lance Zhao, Matt DeVillier, Sean Rhodes, Tim Wawrzynczak, Vanessa Eusebio. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75729?usp=email ) Change subject: UNTESTED acpi: Add ECAM region below PNP0C02 device in SSDT ...................................................................... Patch Set 3: (1 comment) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/75729/comment/8d08f99b_09a6e04d : PS2, Line 587: struct device *dev = dev_find_path(NULL, DEVICE_PATH_DOMAIN); : assert(dev != NULL); > > Anyway, a different thought: This is probably not the right place to decide […] Hmmm, looks like we always set `.ops` for the domain? Technically, it's like any other pointer in there. The difference is that the others are already set (all 21 times). Even if it feels 21 lines too much, it would also feel odd to handle this one pointer differently. Or maybe I misunderstand. That dummy device you have in mind, could that be added by sconfig? Runtime code seems overkill. -- To view, visit https://review.coreboot.org/c/coreboot/+/75729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I852e393726a1b086cf582f4d2d707e7cde05cbf4 Gerrit-Change-Number: 75729 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 15 Jun 2023 22:05:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Add weak method to get memory capability
by Felix Singer (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Martin L Roth, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Chu, Ziang Wang. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75740?usp=email ) Change subject: soc/intel/xeon_sp/spr: Add weak method to get memory capability ...................................................................... Patch Set 10: (1 comment) File src/soc/intel/xeon_sp/spr/romstage.c: https://review.coreboot.org/c/coreboot/+/75740/comment/0ed89d7b_a4daba5f : PS10, Line 45: on SKUs with persistent memory support So, there is already a capability or an indication in hardware whether memory capacity is 4TB or 6TB? Why don't we read that during runtime and return the appropriate value? -- To view, visit https://review.coreboot.org/c/coreboot/+/75740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767 Gerrit-Change-Number: 75740 Gerrit-PatchSet: 10 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 21:47:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Add weak method to get memory capability
by Felix Singer (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Martin L Roth, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Chu, Ziang Wang. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75740?usp=email ) Change subject: soc/intel/xeon_sp/spr: Add weak method to get memory capability ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: > Why not use a devicetree register setting or Kconfig option for this value instead? A weak function […] As I understand it, memory capacity is CPU specific. I think it should be automatically configured by detecting the CPU model. It's not mainboard specific and so devicetree feels like the wrong place. Kconfig option might be confusing when you have the wrong CPU model. -- To view, visit https://review.coreboot.org/c/coreboot/+/75740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767 Gerrit-Change-Number: 75740 Gerrit-PatchSet: 10 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 21:40:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: intelblocks/pep: Restrict TBT displays(DPOF) on S0ix transition to FWCM.
by Hannah Williams (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Balaji Manigandan, Jamie Ryu, Subrata Banik, Tarun Tuli, Usha P, Utkarsh H Patel, Utkarsh H Patel, Vikrant Jadeja. Hannah Williams has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75717?usp=email ) Change subject: intelblocks/pep: Restrict TBT displays(DPOF) on S0ix transition to FWCM. ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/75717?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I110fb971846f110e7d93a524ceda3bf4bfc15c13 Gerrit-Change-Number: 75717 Gerrit-PatchSet: 3 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Reviewer: Vikrant Jadeja Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Vikrant Jadeja Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 21:36:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: ChromeOS: Move CRHW device object
by Kyösti Mälkki (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Hung-Te Lin, Raul Rangel, Subrata Banik. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58421?usp=email ) Change subject: ChromeOS: Move CRHW device object ...................................................................... Patch Set 12: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/58421/comment/5abae073_2685bbd6 : PS12, Line 15: Change > Have you tested this on real hardware? overall LGTM I don't run ChromeOS, nor have I patched its kernel the way TimW described it would be necessary. -- To view, visit https://review.coreboot.org/c/coreboot/+/58421?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I449d0206fbaee94cea99f745cf297ad293e8306c Gerrit-Change-Number: 58421 Gerrit-PatchSet: 12 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 21:29:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/google/rex: Enable Fast V-Mode for MTL-U 15W
by Jay Patel (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Eric Herrmann, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Subrata Banik, Tarun Tuli. Jay Patel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75764?usp=email ) Change subject: mb/google/rex: Enable Fast V-Mode for MTL-U 15W ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/75764/comment/6fe4aa90_58df153f : PS4, Line 7: MTL-U 15W 15W or 28W? -- To view, visit https://review.coreboot.org/c/coreboot/+/75764?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If834c1af8141a19fd2daae653579225b77cfa6c8 Gerrit-Change-Number: 75764 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Herrmann <eherrmann(a)chromium.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Jay Patel <jay2.patel(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Eric Herrmann <eherrmann(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 21:21:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[master]: security/intel/cbnt/Makefile: Fix invalid char '*'
by Felix Singer (Code Review) 15 Jun '23

15 Jun '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75638?usp=email ) Change subject: security/intel/cbnt/Makefile: Fix invalid char '*' ...................................................................... security/intel/cbnt/Makefile: Fix invalid char '*' It seems that using a wildcard (*) in the import path is not supported in the context of the Makefile. This to fix this error: malformed import path "cmd/cbnt-prov/*.go": invalid char '*' Change-Id: I953e06f1ff70a2b61bc5f505f7df9936b7f9b55b Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75638 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/security/intel/cbnt/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/security/intel/cbnt/Makefile.inc b/src/security/intel/cbnt/Makefile.inc index 4959f01..4c585b8 100644 --- a/src/security/intel/cbnt/Makefile.inc +++ b/src/security/intel/cbnt/Makefile.inc @@ -34,7 +34,7 @@ $(CBNT_PROV): printf " CBNT_PROV building tool\n" cd 3rdparty/intel-sec-tools; \ - GO111MODULE=on go build -o $(abspath $@) cmd/cbnt-prov/*.go + GO111MODULE=on go build -o $(abspath $@) cmd/cbnt-prov/main.go cmd/cbnt-prov/cmd.go else $(CBNT_PROV): $(call strip_quotes, $(CONFIG_INTEL_CBNT_PROV_EXTERNAL_BIN_PATH)) cp $< $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/75638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I953e06f1ff70a2b61bc5f505f7df9936b7f9b55b Gerrit-Change-Number: 75638 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[master]: security/intel/cbnt/Makefile: Fix invalid char '*'
by Felix Singer (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Elyes Haouas, Lean Sheng Tan, Paul Menzel. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75638?usp=email ) Change subject: security/intel/cbnt/Makefile: Fix invalid char '*' ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I953e06f1ff70a2b61bc5f505f7df9936b7f9b55b Gerrit-Change-Number: 75638 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 15 Jun 2023 21:18:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2023