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[M] Change in coreboot[master]: soc/intel/meteorlake: Update tcss_usb3 alias
by Eric Lai (Code Review) 16 Jun '23

16 Jun '23

Eric Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75892?usp=email ) Change subject: soc/intel/meteorlake: Update tcss_usb3 alias ...................................................................... soc/intel/meteorlake: Update tcss_usb3 alias TCSS and TBT use the same lane on schematic. Update the port start from 0 to match the Intel schematic. You can better follow the it without convert the port number. Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: Ic6631dcbbd9f6c79c756b015425e2da778eb395e --- M src/mainboard/google/rex/variants/ovis/overridetree.cb M src/mainboard/google/rex/variants/rex0/overridetree.cb M src/mainboard/google/rex/variants/screebo/overridetree.cb M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb M src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb M src/soc/intel/meteorlake/chipset.cb 6 files changed, 37 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/75892/1 diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb index bb13833..e15a7c4 100644 --- a/src/mainboard/google/rex/variants/ovis/overridetree.cb +++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb @@ -67,21 +67,21 @@ register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, CENTER, ACPI_PLD_GROUP(1, 1))" register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER" - device ref tcss_usb3_port1 on end + device ref tcss_usb3_port0 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))" - device ref tcss_usb3_port2 on end + device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(1, 2))" - device ref tcss_usb3_port3 on end + device ref tcss_usb3_port2 on end end end end @@ -89,19 +89,19 @@ device ref tcss_dma0 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" - use tcss_usb3_port1 as dfp[0].typec_port + use tcss_usb3_port0 as dfp[0].typec_port device generic 0 on end end chip drivers/intel/usb4/retimer register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" - use tcss_usb3_port2 as dfp[1].typec_port + use tcss_usb3_port1 as dfp[1].typec_port device generic 0 on end end end device ref tcss_dma1 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" - use tcss_usb3_port3 as dfp[0].typec_port + use tcss_usb3_port2 as dfp[0].typec_port device generic 0 on end end end @@ -197,17 +197,17 @@ device generic 0 on chip drivers/intel/pmc_mux/conn use usb2_port2 as usb2_port - use tcss_usb3_port1 as usb3_port + use tcss_usb3_port0 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn use usb2_port1 as usb2_port - use tcss_usb3_port2 as usb3_port + use tcss_usb3_port1 as usb3_port device generic 1 alias conn1 on end end chip drivers/intel/pmc_mux/conn use usb2_port3 as usb2_port - use tcss_usb3_port3 as usb3_port + use tcss_usb3_port2 as usb3_port device generic 2 alias conn2 on end end end diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 4619cba..9a37ac4 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -323,14 +323,14 @@ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" - device ref tcss_usb3_port1 on end + device ref tcss_usb3_port0 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" - device ref tcss_usb3_port3 on end + device ref tcss_usb3_port2 on end end end end @@ -338,14 +338,14 @@ device ref tcss_dma0 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" - use tcss_usb3_port1 as dfp[0].typec_port + use tcss_usb3_port0 as dfp[0].typec_port device generic 0 on end end end device ref tcss_dma1 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" - use tcss_usb3_port3 as dfp[0].typec_port + use tcss_usb3_port2 as dfp[0].typec_port device generic 0 on end end end @@ -781,12 +781,12 @@ device generic 0 on chip drivers/intel/pmc_mux/conn use usb2_port2 as usb2_port - use tcss_usb3_port1 as usb3_port + use tcss_usb3_port0 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn use usb2_port1 as usb2_port - use tcss_usb3_port3 as usb3_port + use tcss_usb3_port2 as usb3_port device generic 1 alias conn1 on end end end diff --git a/src/mainboard/google/rex/variants/screebo/overridetree.cb b/src/mainboard/google/rex/variants/screebo/overridetree.cb index 8669d95..e6c8a9c 100644 --- a/src/mainboard/google/rex/variants/screebo/overridetree.cb +++ b/src/mainboard/google/rex/variants/screebo/overridetree.cb @@ -256,14 +256,14 @@ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 1))" - device ref tcss_usb3_port2 on end + device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(2, 1))" - device ref tcss_usb3_port4 on end + device ref tcss_usb3_port3 on end end end end @@ -271,14 +271,14 @@ device ref tcss_dma0 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" - use tcss_usb3_port2 as dfp[0].typec_port + use tcss_usb3_port1 as dfp[0].typec_port device generic 0 on end end end device ref tcss_dma1 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)" - use tcss_usb3_port4 as dfp[0].typec_port + use tcss_usb3_port3 as dfp[0].typec_port device generic 0 on end end end @@ -518,12 +518,12 @@ device generic 0 on chip drivers/intel/pmc_mux/conn use usb2_port2 as usb2_port - use tcss_usb3_port2 as usb3_port + use tcss_usb3_port1 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn use usb2_port1 as usb2_port - use tcss_usb3_port4 as usb3_port + use tcss_usb3_port3 as usb3_port device generic 1 alias conn1 on end end end diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 66f2179..05a61be 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -220,25 +220,25 @@ register "desc" = ""USB3 Type-C Port C0"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(4, 2)" - device ref tcss_usb3_port1 on end + device ref tcss_usb3_port0 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(3, 2)" - device ref tcss_usb3_port2 on end + device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C2"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(2, 2)" - device ref tcss_usb3_port3 on end + device ref tcss_usb3_port2 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C3"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "group" = "ACPI_PLD_GROUP(1, 2)" - device ref tcss_usb3_port4 on end + device ref tcss_usb3_port3 on end end end end @@ -246,24 +246,24 @@ device ref tcss_dma0 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" - use tcss_usb3_port1 as dfp[0].typec_port + use tcss_usb3_port0 as dfp[0].typec_port device generic 0 on end end chip drivers/intel/usb4/retimer register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" - use tcss_usb3_port2 as dfp[1].typec_port + use tcss_usb3_port1 as dfp[1].typec_port device generic 0 on end end end device ref tcss_dma1 on chip drivers/intel/usb4/retimer register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" - use tcss_usb3_port3 as dfp[0].typec_port + use tcss_usb3_port2 as dfp[0].typec_port device generic 0 on end end chip drivers/intel/usb4/retimer register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" - use tcss_usb3_port4 as dfp[1].typec_port + use tcss_usb3_port3 as dfp[1].typec_port device generic 0 on end end end diff --git a/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb index f51f18b..3f1579e 100644 --- a/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/mtlrvp_p_ext_ec/overridetree.cb @@ -15,22 +15,22 @@ device generic 0 on chip drivers/intel/pmc_mux/conn use usb2_port1 as usb2_port - use tcss_usb3_port1 as usb3_port + use tcss_usb3_port0 as usb3_port device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn use usb2_port2 as usb2_port - use tcss_usb3_port2 as usb3_port + use tcss_usb3_port1 as usb3_port device generic 1 alias conn1 on end end chip drivers/intel/pmc_mux/conn use usb2_port3 as usb2_port - use tcss_usb3_port3 as usb3_port + use tcss_usb3_port2 as usb3_port device generic 2 alias conn2 on end end chip drivers/intel/pmc_mux/conn use usb2_port4 as usb2_port - use tcss_usb3_port4 as usb3_port + use tcss_usb3_port3 as usb3_port device generic 3 alias conn3 on end end end diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index 57d1205..6a9c26a 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -57,16 +57,16 @@ register "type" = "UPC_TYPE_HUB" device usb 0.0 alias tcss_root_hub off chip drivers/usb/acpi - device usb 3.0 alias tcss_usb3_port1 off end + device usb 3.0 alias tcss_usb3_port0 off end end chip drivers/usb/acpi - device usb 3.1 alias tcss_usb3_port2 off end + device usb 3.1 alias tcss_usb3_port1 off end end chip drivers/usb/acpi - device usb 3.2 alias tcss_usb3_port3 off end + device usb 3.2 alias tcss_usb3_port2 off end end chip drivers/usb/acpi - device usb 3.3 alias tcss_usb3_port4 off end + device usb 3.3 alias tcss_usb3_port3 off end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/75892?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6631dcbbd9f6c79c756b015425e2da778eb395e Gerrit-Change-Number: 75892 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/myst: Update WWAN usb entry
by Jon Murphy (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Eric Lai, Karthik Ramasubramanian. Jon Murphy has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75819?usp=email ) Change subject: mb/google/myst: Update WWAN usb entry ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75819?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ad3973a9519350794a661ad00f71c0eb34edfba Gerrit-Change-Number: 75819 Gerrit-PatchSet: 2 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 16 Jun 2023 01:02:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable option
by Eric Lai (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Arthur Heymans, Elyes Haouas, Felix Singer, Jan Samek, Mario Scheithauer, Michael Niewöhner, Michał Żygowski, Nico Huber, Piotr Król, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75871?usp=email ) Change subject: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable option ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: > Yeah, I know. Pretty much. […] SG! -- To view, visit https://review.coreboot.org/c/coreboot/+/75871?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Gerrit-Change-Number: 75871 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Fri, 16 Jun 2023 00:50:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable option
by Felix Singer (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Arthur Heymans, Elyes Haouas, Eric Lai, Jan Samek, Mario Scheithauer, Michael Niewöhner, Michał Żygowski, Nico Huber, Piotr Król, Subrata Banik. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75871?usp=email ) Change subject: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable option ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > We have a lot of enable flag in chip.h. That would be a lots of patch. Yeah, I know. Pretty much. Though, I am willing to do that work treewide if we decide that we want to go this way. Changing the devicetrees for only one SoC or future SoCs doesn't make much sense because then it's inconsistent and confusing. So either all or nothing. -- To view, visit https://review.coreboot.org/c/coreboot/+/75871?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Gerrit-Change-Number: 75871 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Fri, 16 Jun 2023 00:43:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable option
by Eric Lai (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Arthur Heymans, Elyes Haouas, Felix Singer, Jan Samek, Mario Scheithauer, Michael Niewöhner, Michał Żygowski, Nico Huber, Piotr Król, Subrata Banik. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75871?usp=email ) Change subject: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable option ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > I would like to switch over all boolean-like options from the devicetrees. […] We have a lot of enable flag in chip.h. That would be a lots of patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/75871?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Gerrit-Change-Number: 75871 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Fri, 16 Jun 2023 00:40:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
by Eric Lai (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Arthur Heymans, Felix Singer, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun Tuli. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75756?usp=email ) Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config ...................................................................... Patch Set 11: (2 comments) File src/arch/x86/smbios.c: https://review.coreboot.org/c/coreboot/+/75756/comment/ed46bb99_9269fb76 : PS11, Line 224: /* 7.18.2 */ > Where I can find this chapter? Copied from dmidecode source code. Not sure what version of SMBIOS spec. I can remove. https://review.coreboot.org/c/coreboot/+/75756/comment/fb8f41d1_f6e3729a : PS11, Line 276: > > Why not `>=`? If the speed is the same, I think no need to print? I am open to this. -- To view, visit https://review.coreboot.org/c/coreboot/+/75756?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b5ca1f4a59598531a6cba500672c2717f2a7b00 Gerrit-Change-Number: 75756 Gerrit-PatchSet: 11 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 16 Jun 2023 00:35:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel: Add max memory speed into dimm info
by Eric Lai (Code Review) 16 Jun '23

16 Jun '23

Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75810?usp=email ) Change subject: soc/intel: Add max memory speed into dimm info ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/xeon_sp/cpx/romstage.c: https://review.coreboot.org/c/coreboot/+/75810/comment/232b9a28_7ede915f : PS4, Line 86: dest_dimm->configured_speed_mts = hob->memFreq; > Commit message doesn't mention that this moved to smbioc. […] Because it same as ddr_frequency. It's 0 before I change it. if (dimm->configured_speed_mts != 0) t->clock_speed = dimm->configured_speed_mts; else t->clock_speed = dimm->ddr_frequency; if (dimm->max_speed_mts != 0) t->speed = dimm->max_speed_mts; else t->speed = dimm->ddr_frequency; -- To view, visit https://review.coreboot.org/c/coreboot/+/75810?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I854474bce8d6ed02f47f6dce8585b3ddfae73f80 Gerrit-Change-Number: 75810 Gerrit-PatchSet: 5 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 16 Jun 2023 00:33:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Set AUX orientation at SoC to follow cable for anx7452
by Eric Lai (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Caveh Jalali. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75827?usp=email ) Change subject: mb/google/rex: Set AUX orientation at SoC to follow cable for anx7452 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/75827?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb9f442d2afd81fb5dde4bca97c15457837f9f4a Gerrit-Change-Number: 75827 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Fri, 16 Jun 2023 00:27:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mainboard/google: move tpm_tis to AMD common code
by Eric Lai (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Felix Held, Fred Reitberger, Grzegorz Bernacki, Jason Glenesk, Jason Nien, Jon Murphy, Martin Roth, Matt DeVillier, Raul Rangel. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75621?usp=email ) Change subject: mainboard/google: move tpm_tis to AMD common code ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/gpio/tpm_tis.c: https://review.coreboot.org/c/coreboot/+/75621/comment/f9c8d7cf_687ce700 : PS1, Line 11: if (CONFIG(BOARD_GOOGLE_NIPPERKIN) && board_id() == 1) > or you can make the common code implementation of tis_plat_irq_status() a weak function which simply […] Sorry for my poor English. I mean the Matt means. -- To view, visit https://review.coreboot.org/c/coreboot/+/75621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I775c4e24cffee99b6ac3e05b58a75425029a86c8 Gerrit-Change-Number: 75621 Gerrit-PatchSet: 1 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 16 Jun 2023 00:26:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Grzegorz Bernacki Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable option
by Felix Singer (Code Review) 16 Jun '23

16 Jun '23

Attention is currently required from: Arthur Heymans, Elyes Haouas, Eric Lai, Jan Samek, Mario Scheithauer, Michael Niewöhner, Michał Żygowski, Nico Huber, Piotr Król. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75871?usp=email ) Change subject: [RFC] soc/intel/skylake: Use boolean type for s0ix_enable option ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: I would like to switch over all boolean-like options from the devicetrees. What's your opinion? -- To view, visit https://review.coreboot.org/c/coreboot/+/75871?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16 Gerrit-Change-Number: 75871 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Fri, 16 Jun 2023 00:25:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit June 2023