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Hello Nicholas Chin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: doc/Makefile: Fix build dir setting
......................................................................
doc/Makefile: Fix build dir setting
The commit 4d8da8ed ("Docs: Update sphinx targets with the build directory")
introduces an additional variable intending to allow an user to specify
a different build directory. Since the variable is not writable from the
outside and also the Docker container calls the Makefile with `BUILDDIR`
instead of `SPHINXDIR`, building the documentation within the container
doesn't work anymore.
Thus, change the variable name to `BUILDDIR` and make it writable.
Change-Id: Ibc44134cf1996592597252aeb9dcf7ffb3378ee3
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M Documentation/Makefile
1 file changed, 8 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/75893/2
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I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: soc/intel/cmd/blk/cse: Implement APIs to access FW versions in CMOS
......................................................................
soc/intel/cmd/blk/cse: Implement APIs to access FW versions in CMOS
This patch implements APIs to access the FW versions in CMOS. The get
API allows users to retrieve the current version from CMOS memory.
The set API allows users to set the version in CMOS memory.
BUG=b:280722061
TEST=APIs verified on nivviks and marasov board.
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
Change-Id: Idd0ee19575683691c0a82a291e1fd3b2ffb11786
---
M src/soc/intel/common/block/cse/Kconfig
M src/soc/intel/common/block/cse/Makefile.inc
A src/soc/intel/common/block/cse/cse_lite_cmos.c
A src/soc/intel/common/block/include/intelblocks/cse_lite_cmos.h
4 files changed, 179 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/74995/38
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Nicholas Chin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75893?usp=email )
Change subject: [WIP] doc/Makefile: Fix build dir setting
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
Both docker builds and native builds of the documentation appear to work on my system with this patch
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Change subject: mb/google/rex: Enable Fast V-Mode for MTL-U 15W
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75764/comment/9cbc7411_d9b9f46d :
PS4, Line 7: MTL-U 15W
> > 15W or 28W? […]
sorry, if I am missing some context here. The header mentions 15W and the commit message has 28W.
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Change subject: mb/google/dedede/var/dibbi: Update power limits
......................................................................
Patch Set 9:
(2 comments)
File src/mainboard/google/dedede/variants/dibbi/ramstage.c:
https://review.coreboot.org/c/coreboot/+/75681/comment/2e5757f2_ca65ea39 :
PS9, Line 16: 6000
In devicetree this is set to 3000. Did you mean to change it here? But also I think we can just delete this as I suggested below.
https://review.coreboot.org/c/coreboot/+/75681/comment/6de66a8c_dcd78a11 :
PS9, Line 66: variant_update_cpu_power_limits(pwr_limits, total_entries);
Did you test this? It's not working for me because the common code uses `DEV_PTR(dptf_policy)` which doesn't work on the firmware branch. We might be able to backport support for it, but I haven't tried yet.
But actually I think we can just get rid of this. It's for setting different DPTF limits based on CPU SKU, but we don't need this on dibbi since we're only using 6W SKUs and we want the same limits for all. If OEM devices want to set different limits they can add this later, but I think it's unlikely they will.
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Change subject: soc/intel/jasperlake: Add per-SKU power limits
......................................................................
Patch Set 11:
(1 comment)
File src/mainboard/google/dedede/variants/dibbi/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/75679/comment/e0a8a671_2b95a8a8 :
PS11, Line 34:
> Actually Dibbi don't have N6000 sku. […]
No you can leave it then, thanks. OEM devices can add it in their overridetree if needed.
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Change subject: mb/google/dedede: Support variant specific power limits
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/google/dedede/variants/baseboard/ramstage.c:
https://review.coreboot.org/c/coreboot/+/75680/comment/07b1a0c2_d52a11c8 :
PS8, Line 93: sys_limits[dedede_idx].psys_pl2_power
Could you please use 97% of the BJ power as Ben suggested.
```
watts = sys_limits[dedede_idx].psys_pl2_power;
psyspl2 = SET_PSYSPL2(config_psys->efficiency, watts);
```
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Change subject: mb/google/nissa/var/gothrax: Generate RAM IDs for new memory parts
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/75834/comment/b9495dae_d0f3da6d :
PS2, Line 7: brya
> crystaldrift-odm-external […]
Just let your team know we use
mb/google/base_board/var/project format.
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