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Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
......................................................................
Patch Set 11:
(1 comment)
File src/arch/x86/smbios.c:
https://review.coreboot.org/c/coreboot/+/75756/comment/ca603866_351fa9a2 :
PS11, Line 276: >
> I think it is good to print the max speed if the value is valid.
so print it if dimm->max_speed_mts != 0
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Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
......................................................................
Patch Set 11:
(1 comment)
File src/arch/x86/smbios.c:
https://review.coreboot.org/c/coreboot/+/75756/comment/7b4f4ed9_a983f66e :
PS11, Line 276: >
> If the speed is the same, I think no need to print? I am open to this.
I think it is good to print the max speed if the value is valid.
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Change subject: soc/intel/apollolake: Fix FSP SATA speed limit configuraion
......................................................................
Patch Set 9: Code-Review+2
(2 comments)
Patchset:
PS7:
> There can be hardware related topics on the PCB (layout, signal quality, ... […]
I understand now. Thank you for the detailed explanation! Done.
File src/soc/intel/apollolake/ahci.c:
https://review.coreboot.org/c/coreboot/+/75820/comment/4d8fbaae_173ded17 :
PS7, Line 12: if (speed == SATA_DEFAULT)
:
> I think Werner is right. We should leave that in.
OK, let's leave it. That's why I marked it as nit.
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Change subject: soc/intel/apollolake: Fix FSP SATA speed limit configuraion
......................................................................
Patch Set 9:
(1 comment)
File src/soc/intel/apollolake/ahci.c:
https://review.coreboot.org/c/coreboot/+/75820/comment/951d48a0_b7f15405 :
PS7, Line 12: if (speed == SATA_DEFAULT)
:
> This was added in order to keep the interference with existing code as low as possible. […]
I think Werner is right. We should leave that in.
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Hello Eric Lai, Felix Singer, Jan Samek, Sean Rhodes, Werner Zeh, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75820?usp=email
to look at the new patch set (#9).
The following approvals got outdated and were removed:
Code-Review+1 by Werner Zeh, Verified+1 by build bot (Jenkins)
Change subject: soc/intel/apollolake: Fix FSP SATA speed limit configuraion
......................................................................
soc/intel/apollolake: Fix FSP SATA speed limit configuraion
With commit f165bbdcf043 ("soc/intel/apollolake: Make SATA speed limit
configurable") came the expansion to adjust the SATA speed.
Unfortunately, APL FSP-S sets only the default value, so Gen 3, and
ignores the passing parameter value. Since the corresponding register
entry can only be changed once, the setting must be made on coreboot
side before FSP-S is called. This patch fixes the SATA speed
configuration for Apollo Lake CPUs.
Link to Intel Pentium and Celeron N- and J- series datasheet volume 2:
https://web.archive.org/web/20230614130311/https://www.intel.com/content/ww…
BUG=none
TEST=Boot into Linux and check SATA configuration via dmesg
ahci 0000:00:12.0: AHCI 0001.0301 32 slots 1 ports 3 Gbps 0x1 impl SATA
mode
ata1: SATA max UDMA/133 abar m2048@0x9872a000 port 0x9872a100 irq 126
ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
Change-Id: I6f55f40941fa618e7de13a5cefe9e17ae34c5c99
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
M src/soc/intel/apollolake/Makefile.inc
A src/soc/intel/apollolake/ahci.c
M src/soc/intel/apollolake/chip.c
A src/soc/intel/apollolake/include/soc/ahci.h
4 files changed, 48 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/75820/9
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