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Change subject: cbfstool: Correctly interpret uninitialized MMAP window ranges
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Was the unresolved comment solved already?
I don't have any memory of this patch. Arthur has since changed a bunch of how this works in CB:68160. I believe(?) that with his patch it shouldn't be possible to have a mapping window of size 0 anymore (although I'm not quite sure how it was previously possible to begin with). I think this patch is probably still valid as a sanity check but I don't think it should be possible to hit that case anymore.
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Change subject: arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
......................................................................
Patch Set 11:
(1 comment)
File src/arch/x86/smbios.c:
https://review.coreboot.org/c/coreboot/+/75756/comment/4a08a03e_7aa054ce :
PS11, Line 224: /* 7.18.2 */
Where I can find this chapter?
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Change subject: docs/flashmap: Document available flashmap flags
......................................................................
Patch Set 1: Code-Review+2
(2 comments)
File Documentation/lib/flashmap.md:
https://review.coreboot.org/c/coreboot/+/75850/comment/fffe9d50_d7093b6f :
PS1, Line 114: * The "flag" specifies the attribute or type for given section. That includes:
nit: Might be good to mention that multiple flags need to be space-separated.
https://review.coreboot.org/c/coreboot/+/75850/comment/6fced762_d86a52e5 :
PS1, Line 117: recovery.
nit: Maybe mention that this directly translates to an FMAP flag (which `CBFS` doesn't).
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Change subject: soc/intel: Add max memory speed into dimm info
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
File src/soc/intel/xeon_sp/cpx/romstage.c:
https://review.coreboot.org/c/coreboot/+/75810/comment/87714755_5dcb456f :
PS4, Line 86: dest_dimm->configured_speed_mts = hob->memFreq;
Commit message doesn't mention that this moved to smbioc.c as well, and IMO should have been a separate commit in any case.
However, otherwise looks good.
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Change subject: lib/fw_config: Make fw_config_is_provisioned() always available
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Patch Set 2: Code-Review+2
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Change subject: hardwaremain.c: Drop checking the S3 resume
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Abandoned
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Change subject: UNTESTED acpi: Add ECAM region below PNP0C02 device in SSDT
......................................................................
Patch Set 3:
(1 comment)
File src/acpi/acpi.c:
https://review.coreboot.org/c/coreboot/+/75729/comment/166a9d5f_40144b6c :
PS2, Line 587: struct device *dev = dev_find_path(NULL, DEVICE_PATH_DOMAIN);
: assert(dev != NULL);
> Anyway, a different thought: This is probably not the right place to decide
> what device we add the resource to. Technically we already have the
> `.acpi_fill_ssdt` pointer for this. We could set it to a default implementation
> depending on CONFIG_ECAM_MMCONF_SUPPORT. And if a platform has its own
> fill_ssdt(), it could still call the default one. WDYT?
I agree, but I'd prefer not hook that up to each platform in .acpi_fill_ssdt.
Would adding a dummy device at runtime using a bootstate hook that has this in .acpi_fill_ssdt be an acceptable solution to avoid hooking it up everywhere? Maybe with a Kconfig so that it can still be overriden if desired?
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Change subject: mb/google/myst: Update PCIe romstage gpios
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Patch Set 5: Code-Review+1
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Change subject: soc/intel/cmd/blk/cse: Store fw versions in CMOS memory for cold boot
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/common/block/cse/cse_lite.c:
https://review.coreboot.org/c/coreboot/+/75755/comment/b5297dd1_acbc9b98 :
PS7, Line 1176: * Helper function that stores current CSE firmware version to CBMEM, except
: * during recovery mode.
> u can do it later during clean up cl
Acknowledged
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Change subject: soc/intel/cmd/blk/cse: Implement APIs to access FW versions in CMOS
......................................................................
Patch Set 37:
(8 comments)
File src/soc/intel/common/block/cse/Kconfig:
https://review.coreboot.org/c/coreboot/+/74995/comment/381642a1_67592e3d :
PS36, Line 48: SOC_INTEL_PARTITION_FW_CMOS_OFFSET
> SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET ?
Acknowledged
https://review.coreboot.org/c/coreboot/+/74995/comment/674d2719_f6d6e7fd :
PS36, Line 53: firmware partition
> may be worth clarifying that its the CSE FW partition
Acknowledged
File src/soc/intel/common/block/cse/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/74995/comment/fbe49d59_c1a2f146 :
PS36, Line 12:
> i don't think any other changes are necessary here apart from adding cse_lite_cmos. […]
Acknowledged
File src/soc/intel/common/block/cse/cse_lite_cmos.c:
https://review.coreboot.org/c/coreboot/+/74995/comment/64ee2c9a_bfff7970 :
PS36, Line 8: 0x46575054
> it has to be opposite as little endian
Acknowledged
https://review.coreboot.org/c/coreboot/+/74995/comment/2fd36985_01105174 :
PS36, Line 100: get_cmos_cse_version
> get_cmos_cse_rw_fw_version
Acknowledged
https://review.coreboot.org/c/coreboot/+/74995/comment/f0447904_4f6305d3 :
PS36, Line 114: set_cmos_cse_version
> same
Acknowledged
https://review.coreboot.org/c/coreboot/+/74995/comment/ec984536_e3e92c78 :
PS36, Line 134: printk(BIOS_WARNING, "CMOS fw version corrupted, initiating memory re-init\n");
> we don't need this IMO
Acknowledged
https://review.coreboot.org/c/coreboot/+/74995/comment/35804b93_c6713810 :
PS36, Line 146: printk(BIOS_WARNING, "CMOS fw version corrupted, initiating memory re-init\n");
> we don't need this
Acknowledged
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