coreboot-gerrit June 2023

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[S] Change in coreboot[master]: soc/intel/xeon_sp/spr: Add weak method to get memory capability
by Martin L Roth (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Felix Singer, Nico Huber, Patrick Rudolph, Paul Menzel, Tim Chu, Ziang Wang. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75740?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/xeon_sp/spr: Add weak method to get memory capability ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: Why not use a devicetree register setting or Kconfig option for this value instead? A weak function to set a single value seems like the wrong choice to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/75740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieb892d3b148291b35808d634d63b58b90d456767 Gerrit-Change-Number: 75740 Gerrit-PatchSet: 10 Gerrit-Owner: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 16:22:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Enable audio BT offload
by Martin L Roth (Code Review) 15 Jun '23

15 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72881?usp=email ) Change subject: mb/google/rex: Enable audio BT offload ...................................................................... mb/google/rex: Enable audio BT offload This patch enables BT offload feature on Rex over SSP1. BT mode is selected via FW_CONFIG and corresponding VGPIOs are programmed. BUG=b:275538390 TEST=Verified audio playback using BT speaker/headset in I2S mode on google/rex. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72881 Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/rex0/fw_config.c M src/mainboard/google/rex/variants/rex0/variant.c 2 files changed, 49 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/rex0/fw_config.c b/src/mainboard/google/rex/variants/rex0/fw_config.c index 7d7c901..11014b5 100644 --- a/src/mainboard/google/rex/variants/rex0/fw_config.c +++ b/src/mainboard/google/rex/variants/rex0/fw_config.c @@ -34,12 +34,51 @@ PAD_NC(GPP_D17, NONE), }; +static const struct pad_config bt_i2s_enable_pads[] = { + /* GPP_V30 : [] ==> BT_I2S_BCLK */ + PAD_CFG_NF(GPP_VGPIO30, NONE, DEEP, NF2), + /* GPP_V31 : [] ==> BT_I2S_SYNC */ + PAD_CFG_NF(GPP_VGPIO31, NONE, DEEP, NF2), + /* GPP_V32 : [] ==> BT_I2S_SDO */ + PAD_CFG_NF(GPP_VGPIO32, NONE, DEEP, NF2), + /* GPP_V33 : [] ==> BT_I2S_SDI */ + PAD_CFG_NF(GPP_VGPIO33, NONE, DEEP, NF2), + /* GPP_V34 : [] ==> SSP2_SCLK */ + PAD_CFG_NF(GPP_VGPIO34, NONE, DEEP, NF1), + /* GPP_V35 : [] ==> SSP2_SFRM */ + PAD_CFG_NF(GPP_VGPIO35, NONE, DEEP, NF1), + /* GPP_V36 : [] ==> SSP_TXD */ + PAD_CFG_NF(GPP_VGPIO36, NONE, DEEP, NF1), + /* GPP_V37 : [] ==> SSP_RXD */ + PAD_CFG_NF(GPP_VGPIO37, NONE, DEEP, NF1), +}; + +static const struct pad_config bt_i2s_disable_pads[] = { + /* GPP_V30 : [] ==> BT_I2S_BCLK */ + PAD_NC(GPP_VGPIO30, NONE), + /* GPP_V31 : [] ==> BT_I2S_SYNC */ + PAD_NC(GPP_VGPIO31, NONE), + /* GPP_V32 : [] ==> BT_I2S_SDO */ + PAD_NC(GPP_VGPIO32, NONE), + /* GPP_V33 : [] ==> BT_I2S_SDI */ + PAD_NC(GPP_VGPIO33, NONE), + /* GPP_V34 : [] ==> SSP2_SCLK */ + PAD_NC(GPP_VGPIO34, NONE), + /* GPP_V35 : [] ==> SSP2_SFRM */ + PAD_NC(GPP_VGPIO35, NONE), + /* GPP_V36 : [] ==> SSP_TXD */ + PAD_NC(GPP_VGPIO36, NONE), + /* GPP_V37 : [] ==> SSP_RXD */ + PAD_NC(GPP_VGPIO37, NONE), +}; + void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { if (!fw_config_is_provisioned()) { GPIO_PADBASED_OVERRIDE(padbased_table, i2s_disable_pads); GPIO_PADBASED_OVERRIDE(padbased_table, dmic_disable_pads); GPIO_PADBASED_OVERRIDE(padbased_table, sndw_disable_pads); + GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads); return; } @@ -48,11 +87,15 @@ GPIO_PADBASED_OVERRIDE(padbased_table, i2s_disable_pads); GPIO_PADBASED_OVERRIDE(padbased_table, dmic_disable_pads); GPIO_PADBASED_OVERRIDE(padbased_table, sndw_disable_pads); + GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads); } else if (fw_config_probe(FW_CONFIG(AUDIO, MAX98363_CS42L42_SNDW))) { printk(BIOS_INFO, "Configure GPIOs for SoundWire audio.\n"); GPIO_PADBASED_OVERRIDE(padbased_table, i2s_disable_pads); + GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_disable_pads); } else if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) { printk(BIOS_INFO, "Configure GPIOs for I2S audio.\n"); GPIO_PADBASED_OVERRIDE(padbased_table, sndw_disable_pads); + printk(BIOS_INFO, "Configure GPIOs for BT offload mode.\n"); + GPIO_PADBASED_OVERRIDE(padbased_table, bt_i2s_enable_pads); } } diff --git a/src/mainboard/google/rex/variants/rex0/variant.c b/src/mainboard/google/rex/variants/rex0/variant.c index 3aec24b..b259636 100644 --- a/src/mainboard/google/rex/variants/rex0/variant.c +++ b/src/mainboard/google/rex/variants/rex0/variant.c @@ -21,3 +21,9 @@ acpigen_soc_set_tx_gpio(GPP_B09); } } + +void variant_update_soc_chip_config(struct soc_intel_meteorlake_config *config) +{ + config->cnvi_bt_audio_offload = fw_config_probe(FW_CONFIG(AUDIO, + MAX98360_ALC5682I_I2S)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/72881?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c Gerrit-Change-Number: 72881 Gerrit-PatchSet: 20 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jairaj Arava <jairaj.arava(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Uday Bhat <uday.m.bhat(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anil Kumar K <anil.kumar.k(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-CC: Uday M Bhat Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/nissa/var/pujjo: Set GPIO of WWAN_SAR_DETECT to NC
by Martin L Roth (Code Review) 15 Jun '23

15 Jun '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75403?usp=email ) Change subject: mb/google/nissa/var/pujjo: Set GPIO of WWAN_SAR_DETECT to NC ...................................................................... mb/google/nissa/var/pujjo: Set GPIO of WWAN_SAR_DETECT to NC Pujjo does not support GPIO based D-SAR, so set GPP_D15 and GPP_H23 to NC. BUG=b:275264095 TEST=boot on pujjo and no impact WWAN dynamic SAR function Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Change-Id: I4fe40b32a572a8d914e01e5cd7927766ccf17c02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75403 Reviewed-by: Derek Huang <derekhuang(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/pujjo/gpio.c 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: Derek Huang: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/pujjo/gpio.c b/src/mainboard/google/brya/variants/pujjo/gpio.c index fd3dca5..e8e4fbe 100644 --- a/src/mainboard/google/brya/variants/pujjo/gpio.c +++ b/src/mainboard/google/brya/variants/pujjo/gpio.c @@ -26,8 +26,8 @@ PAD_CFG_GPI_APIC(GPP_H19, NONE, PLTRST, LEVEL, NONE), /* H22 : WCAM_MCLK_R ==> NC */ PAD_NC(GPP_H22, NONE), - /* H23 : WWAN_SAR_DETECT_ODL */ - PAD_CFG_GPO(GPP_H23, 1, DEEP), + /* H23 : WWAN_SAR_DETECT_ODL ==> NC */ + PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG), }; /* Pad configuration in ramstage for Pujjoteen5 */ @@ -42,8 +42,8 @@ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* D6 : SRCCLKREQ1# ==> WWAN_EN */ PAD_CFG_GPO_LOCK(GPP_D6, 1, LOCK_CONFIG), - /* D15 : EN_PP2800_WCAM_X ==> WWAN_SAR_DETECT_2_ODL */ - PAD_CFG_GPO(GPP_D15, 1, DEEP), + /* D15 : EN_PP2800_WCAM_X ==> NC */ + PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG), /* D16 : EN_PP1800_PP1200_WCAM_X ==> NC */ PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG), /* D17 : NC ==> SD_WAKE_N */ @@ -56,8 +56,8 @@ PAD_CFG_GPO(GPP_H21, 0, DEEP), /* H22 : WCAM_MCLK_R ==> NC */ PAD_NC(GPP_H22, NONE), - /* H23 : WWAN_SAR_DETECT_ODL */ - PAD_CFG_GPO(GPP_H23, 1, DEEP), + /* H23 : WWAN_SAR_DETECT_ODL ==> NC */ + PAD_NC_LOCK(GPP_H23, NONE, LOCK_CONFIG), }; /* Early pad configuration in bootblock */ -- To view, visit https://review.coreboot.org/c/coreboot/+/75403?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fe40b32a572a8d914e01e5cd7927766ccf17c02 Gerrit-Change-Number: 75403 Gerrit-PatchSet: 8 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-CC: Jynn Chen <jynn.chen(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin3 Yang <kevin3.yang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stanley Wu <stanley1.wu(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel: Add max memory speed into dimm info
by Felix Held (Code Review) 15 Jun '23

15 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75810?usp=email ) Change subject: soc/intel: Add max memory speed into dimm info ...................................................................... soc/intel: Add max memory speed into dimm info Add MaximumMemoryClockSpeed if FSP have it, otherwise pass 0. TEST=check dmidecode dump the max speed. Handle 0x000C, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 64 bits Data Width: 64 bits Size: 16 GB Form Factor: SODIMM Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: DDR5 Type Detail: Unknown Synchronous Speed: 5600 MT/s Manufacturer: Micron Serial Number: 3f064d84 Asset Tag: Channel-0-DIMM-0-AssetTag Part Number: MTC8C1084S1SC56BG1 Rank: 1 Configured Memory Speed: 5200 MT/s Minimum Voltage: 1.1 V Maximum Voltage: 1.1 V Configured Voltage: 1.1 V Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: I854474bce8d6ed02f47f6dce8585b3ddfae73f80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75810 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/apollolake/meminit_util_apl.c M src/soc/intel/apollolake/meminit_util_glk.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/smbios.c M src/soc/intel/common/smbios.h M src/soc/intel/elkhartlake/romstage/romstage.c M src/soc/intel/jasperlake/romstage/romstage.c M src/soc/intel/meteorlake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/tigerlake/romstage/romstage.c M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/spr/romstage.c 13 files changed, 29 insertions(+), 18 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 740a4a2..dfe3b32 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -140,7 +140,8 @@ meminfo_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - node); + node, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/apollolake/meminit_util_apl.c b/src/soc/intel/apollolake/meminit_util_apl.c index 9432011..3bcb7bb 100644 --- a/src/soc/intel/apollolake/meminit_util_apl.c +++ b/src/soc/intel/apollolake/meminit_util_apl.c @@ -83,6 +83,7 @@ 0, src_dimm->MfgId, 0, + 0, 0); index++; } diff --git a/src/soc/intel/apollolake/meminit_util_glk.c b/src/soc/intel/apollolake/meminit_util_glk.c index 9922b28..753451a 100644 --- a/src/soc/intel/apollolake/meminit_util_glk.c +++ b/src/soc/intel/apollolake/meminit_util_glk.c @@ -89,7 +89,8 @@ 0, src_dimm->MfgId, src_dimm->SpdModuleType, - node); + node, + memory_info_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index a417359..b3777b6 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -108,7 +108,8 @@ memory_info_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - 0); + 0, + memory_info_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c index 5ab2dbc..818a35e 100644 --- a/src/soc/intel/common/smbios.c +++ b/src/soc/intel/common/smbios.c @@ -14,13 +14,17 @@ u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, const u8 *module_serial_num, u16 data_width, u32 vdd_voltage, - bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id) + bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id, + u32 max_frequency) { dimm->mod_id = mod_id; dimm->mod_type = mod_type; dimm->dimm_size = dimm_capacity; dimm->ddr_type = ddr_type; + /* keep ddr_frequency for backward compatible */ dimm->ddr_frequency = frequency; + dimm->configured_speed_mts = frequency; + dimm->max_speed_mts = max_frequency; dimm->rank_per_dimm = rank_per_dimm; dimm->channel_num = channel_id; dimm->dimm_num = dimm_id; diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h index 410b2fd..9fb42b5 100644 --- a/src/soc/intel/common/smbios.h +++ b/src/soc/intel/common/smbios.h @@ -14,6 +14,7 @@ u32 frequency, u8 rank_per_dimm, u8 channel_id, u8 dimm_id, const char *module_part_num, size_t module_part_number_size, const u8 *module_serial_num, u16 data_width, u32 vdd_voltage, - bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id); + bool ecc_support, u16 mod_id, u8 mod_type, u8 ctrlr_id, + u32 max_frequency); #endif /* _COMMON_SMBIOS_H_ */ diff --git a/src/soc/intel/elkhartlake/romstage/romstage.c b/src/soc/intel/elkhartlake/romstage/romstage.c index 427cee5..3dfb7c2 100644 --- a/src/soc/intel/elkhartlake/romstage/romstage.c +++ b/src/soc/intel/elkhartlake/romstage/romstage.c @@ -113,7 +113,8 @@ meminfo_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - node); + node, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index 9cec859..3688f9e 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -113,7 +113,8 @@ meminfo_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - node); + node, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c index b5351de..3df480c 100644 --- a/src/soc/intel/meteorlake/romstage/romstage.c +++ b/src/soc/intel/meteorlake/romstage/romstage.c @@ -108,7 +108,8 @@ meminfo_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - node); + node, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 02ae19a..660440c 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -112,7 +112,8 @@ memory_info_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - 0); + 0, + memory_info_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index c1aca17..31b19d2 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -113,7 +113,8 @@ meminfo_hob->EccSupport, src_dimm->MfgId, src_dimm->SpdModuleType, - node); + node, + meminfo_hob->MaximumMemoryClockSpeed); index++; } } diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 265ab70..fe2ca86 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -81,9 +81,6 @@ return; } dest_dimm = &mem_info->dimm[index]; - dest_dimm->max_speed_mts = - get_max_memory_speed(src_dimm.commonTck); - dest_dimm->configured_speed_mts = hob->memFreq; dimm_info_fill(dest_dimm, src_dimm.DimmSize << 6, 0x1a, /* hard-coded memory device type as DDR4 */ @@ -99,7 +96,8 @@ true, /* hard-coded as ECC supported */ src_dimm.VendorID, src_dimm.actKeyByte2, - 0); + 0, + get_max_memory_speed(src_dimm.commonTck)); index++; num_dimms++; } else if (mainboard_dimm_slot_exists(0, ch, dimm)) { diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index fef4d94..8004730 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -304,9 +304,7 @@ the board. */ continue; } - dest_dimm->max_speed_mts = - get_max_memory_speed(src_dimm.commonTck); - dest_dimm->configured_speed_mts = hob->memFreq; + dest_dimm->soc_num = soc; if (hob->DramType == SPD_TYPE_DDR5) { @@ -328,7 +326,8 @@ sizeof(src_dimm.PartNumber), (const uint8_t *)&src_dimm.serialNumber[0], data_width, vdd_voltage, true, /* hard-coded as ECC supported */ - src_dimm.VendorID, src_dimm.actKeyByte2, 0); + src_dimm.VendorID, src_dimm.actKeyByte2, 0, + get_max_memory_speed(src_dimm.commonTck)); dimm_num++; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/75810?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I854474bce8d6ed02f47f6dce8585b3ddfae73f80 Gerrit-Change-Number: 75810 Gerrit-PatchSet: 5 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[master]: acpi/acpi.c: Fix printing all ACPI tables
by Arthur Heymans (Code Review) 15 Jun '23

15 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75860?usp=email ) Change subject: acpi/acpi.c: Fix printing all ACPI tables ...................................................................... acpi/acpi.c: Fix printing all ACPI tables Loop over tables in xsdt instead of maintaining a list of local variables to loop over. Some tables were not generated directly in the write_acpi_tables function, like IVRS or SRAT. Now those tables are printed too and the code is simpler. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ie0a6e2b6e2b72b5c8f59e730bea9b51007b507b6 --- M src/acpi/acpi.c 1 file changed, 2 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/75860/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index aa1cd1c..78135d7 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -2136,12 +2136,8 @@ if (CONFIG(DEBUG_ACPICA_COMPATIBLE)) { printk(BIOS_DEBUG, "Printing ACPI tables in ACPICA compatible format\n"); - void *acpi_tables[] = { rsdt, xsdt, fadt, facs, slic, ssdt, dsdt, - mcfg, tcpa, tpm2, madt, lpit, bert }; - for (size_t i = 0; i < ARRAY_SIZE(acpi_tables); i++) { - if (acpi_tables[i] == NULL) - continue; - acpidump_print(acpi_tables[i]); + for (size_t i = 0; xsdt->entry[i] != 0; i++) { + acpidump_print((void *)(uintptr_t)xsdt->entry[i]); } printk(BIOS_DEBUG, "Done printing ACPI tables in ACPICA compatible format\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/75860?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0a6e2b6e2b72b5c8f59e730bea9b51007b507b6 Gerrit-Change-Number: 75860 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: drv/i2c/pi608gp: Fix style
by Felix Held (Code Review) 15 Jun '23

15 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75806?usp=email ) Change subject: drv/i2c/pi608gp: Fix style ...................................................................... drv/i2c/pi608gp: Fix style In commit e59f18bf29a8 ("drivers/i2c: Add PI7C9X2G608GP PCIe switch driver (pi608gp)"), there were some suggestions after it's been already merged. This patch addresses the points regarding the code style and comments. BUG=none TEST=Build OK, no behavioral changes in the pi608gp driver, console logs without changes. Change-Id: I5fc54708e0085fea4bd1f2fbf2afb400d2ccbd46 Signed-off-by: Jan Samek <jan.samek(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75806 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/drivers/i2c/pi608gp/pi608gp.c 1 file changed, 6 insertions(+), 5 deletions(-) Approvals: Mario Scheithauer: Looks good to me, approved Himanshu Sahdev: Looks good to me, but someone else must approve build bot (Jenkins): Verified Eric Lai: Looks good to me, but someone else must approve diff --git a/src/drivers/i2c/pi608gp/pi608gp.c b/src/drivers/i2c/pi608gp/pi608gp.c index 9d63f85..2c61a80 100644 --- a/src/drivers/i2c/pi608gp/pi608gp.c +++ b/src/drivers/i2c/pi608gp/pi608gp.c @@ -102,7 +102,7 @@ } /* Retrieve back the value from the received SMBus packet in big endian order. */ - *val = read_be32((void *) buf); + *val = read_be32((void *)buf); return CB_SUCCESS; } @@ -122,7 +122,7 @@ }; /* Insert register value to write in BE order after the header. */ - write_be32((void *) &buf[4], val); + write_be32((void *)&buf[4], val); /* Perform the register write */ ret = smbus_block_write(dev, PI608GP_CMD_BLK_WR, sizeof(buf), buf); @@ -134,8 +134,9 @@ return CB_SUCCESS; } -static enum cb_err pi608gp_reg_update(struct device *dev, uint8_t port, uint32_t reg_addr, - uint32_t and_mask, uint32_t or_mask) +static enum cb_err +pi608gp_reg_update(struct device *dev, uint8_t port, uint32_t reg_addr, uint32_t and_mask, + uint32_t or_mask) { uint32_t val; @@ -153,7 +154,7 @@ static void pi608gp_init(struct device *dev) { - const uint8_t port = 0; /* Only port 0 is being configured */ + const uint8_t port = 0; /* Only the upstream port is being configured */ struct drivers_i2c_pi608gp_config *config = dev->chip_info; uint8_t amp_lvl, deemph_lvl; -- To view, visit https://review.coreboot.org/c/coreboot/+/75806?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5fc54708e0085fea4bd1f2fbf2afb400d2ccbd46 Gerrit-Change-Number: 75806 Gerrit-PatchSet: 2 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: drv/i2c/pi608gp: Fix types
by Felix Held (Code Review) 15 Jun '23

15 Jun '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75500?usp=email ) Change subject: drv/i2c/pi608gp: Fix types ...................................................................... drv/i2c/pi608gp: Fix types In commit e59f18bf29a8 ("drivers/i2c: Add PI7C9X2G608GP PCIe switch driver (pi608gp)"), there were some suggestions after it's been already merged. This patch addresses the points regarding the number types - fix of the printk format strings, inclusion of 'stdint.h' and marking the set of allowed values as constant. BUG=none TEST=Build OK, no behavioral changes in the pi608gp driver, console logs without changes. Change-Id: I34c664f6a8a257b260facdbf9043825ff4a4c932 Signed-off-by: Jan Samek <jan.samek(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75500 Reviewed-by: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/drivers/i2c/pi608gp/pi608gp.c M src/drivers/i2c/pi608gp/pi608gp.h 2 files changed, 7 insertions(+), 5 deletions(-) Approvals: Eric Lai: Looks good to me, but someone else must approve Mario Scheithauer: Looks good to me, approved Himanshu Sahdev: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/drivers/i2c/pi608gp/pi608gp.c b/src/drivers/i2c/pi608gp/pi608gp.c index e50e726..9d63f85 100644 --- a/src/drivers/i2c/pi608gp/pi608gp.c +++ b/src/drivers/i2c/pi608gp/pi608gp.c @@ -30,12 +30,12 @@ /* Allowed drive amplitude levels are in units of mV in range 0 to 475 mV with 25 mV steps, based on Table 6-6 from the PI7C9X2G608GP datasheet. */ if (level_mv > 475) { - printk(BIOS_ERR, "PI608GP: Drive level %d mV out of range 0 to 475 mV!", + printk(BIOS_ERR, "PI608GP: Drive level %u mV out of range 0 to 475 mV!", level_mv); return PI608GP_ENCODE_ERR; } if (level_mv % 25 != 0) { - printk(BIOS_ERR, "PI608GP: Drive level %d mV not a multiple of 25!\n", + printk(BIOS_ERR, "PI608GP: Drive level %u mV not a multiple of 25!\n", level_mv); return PI608GP_ENCODE_ERR; } @@ -48,7 +48,7 @@ { /* Table of allowed fixed-point millivolt values, based on Table 6-8 from the PI7C9X2G608GP datasheet. */ - struct deemph_lvl allowed[] = { + const struct deemph_lvl allowed[] = { { 0, 0}, { 6, 0}, { 12, 5}, { 19, 0}, { 25, 0}, { 31, 0}, { 37, 5}, { 44, 0}, { 50, 0}, { 56, 0}, { 62, 5}, { 69, 0}, { 75, 0}, { 81, 0}, { 87, 0}, { 94, 0}, {100, 0}, {106, 0}, {112, 5}, {119, 0}, {125, 0}, {131, 0}, {137, 5}, {144, 0}, @@ -59,10 +59,10 @@ if (allowed[i].lvl == level_mv.lvl && allowed[i].lvl_10 == level_mv.lvl_10) /* When found, the encoded value is a 5-bit number that corresponds to the index in the table of allowed values above. */ - return (uint8_t) (i & 0x1f); + return i & 0x1f; } - printk(BIOS_ERR, "PI608GP: Requested unsupported de-emphasis level value: %d.%d mV!\n", + printk(BIOS_ERR, "PI608GP: Requested unsupported de-emphasis level value: %u.%u mV!\n", level_mv.lvl, level_mv.lvl_10); return PI608GP_ENCODE_ERR; } diff --git a/src/drivers/i2c/pi608gp/pi608gp.h b/src/drivers/i2c/pi608gp/pi608gp.h index fe2776b..9a5f5df 100644 --- a/src/drivers/i2c/pi608gp/pi608gp.h +++ b/src/drivers/i2c/pi608gp/pi608gp.h @@ -3,6 +3,8 @@ #ifndef _I2C_PI608GP_H_ #define _I2C_PI608GP_H_ +#include <stdint.h> + /* Struct to store fixed-point millivolt values */ struct deemph_lvl { uint32_t lvl, lvl_10; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/75500?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34c664f6a8a257b260facdbf9043825ff4a4c932 Gerrit-Change-Number: 75500 Gerrit-PatchSet: 7 Gerrit-Owner: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mainboard/google: move tpm_tis to AMD common code
by Kyösti Mälkki (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Eric Lai, Felix Held, Fred Reitberger, Grzegorz Bernacki, Jason Glenesk, Jason Nien, Jon Murphy, Martin Roth, Raul Rangel. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75621?usp=email ) Change subject: mainboard/google: move tpm_tis to AMD common code ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Someone please decide if CB:74471 is wanted and then rebase one or the other. -- To view, visit https://review.coreboot.org/c/coreboot/+/75621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I775c4e24cffee99b6ac3e05b58a75425029a86c8 Gerrit-Change-Number: 75621 Gerrit-PatchSet: 1 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 15 Jun 2023 14:59:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/common/block/oc_wdt: Add OC watchdog common block
by Nico Huber (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Angel Pons, Arthur Heymans, Benjamin Doron, Martin L Roth, Maximilian Brune, Michał Kopeć, Michał Żygowski, Werner Zeh. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68944?usp=email ) Change subject: soc/intel/common/block/oc_wdt: Add OC watchdog common block ...................................................................... Patch Set 17: (1 comment) File src/soc/intel/common/block/oc_wdt/oc_wdt.c: https://review.coreboot.org/c/coreboot/+/68944/comment/a2d33ee7_25841cda : PS17, Line 62: unsigned int oc_wdt_get_current_timeout(void) : { : return (inl(PCH_OC_WDT_CTL) & PCH_OC_WDT_CTL_TOV_MASK) + 1; : } > Nico, the value in the register reflects the currently programmed timeout (so it is constant between […] Thanks, I just misunderstood what "current" refers to. But now, I understand the purpose of the function even less, I guess. Why would someone read back the last programmer value? Is there some code that is using it yet? -- To view, visit https://review.coreboot.org/c/coreboot/+/68944?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib494aa0c7581351abca8b496fc5895b2c7cbc5bc Gerrit-Change-Number: 68944 Gerrit-PatchSet: 17 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Himanshu Sahdev <himanshu.sahdev(a)intel.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Thu, 15 Jun 2023 14:56:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mainboard/google: move tpm_tis to AMD common code
by Matt DeVillier (Code Review) 15 Jun '23

15 Jun '23

Attention is currently required from: Eric Lai, Felix Held, Fred Reitberger, Grzegorz Bernacki, Jason Glenesk, Jason Nien, Jon Murphy, Martin Roth, Raul Rangel. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/75621?usp=email ) Change subject: mainboard/google: move tpm_tis to AMD common code ...................................................................... Patch Set 1: (1 comment) File src/soc/amd/common/block/gpio/tpm_tis.c: https://review.coreboot.org/c/coreboot/+/75621/comment/6d4fd459_2485aa3b : PS1, Line 11: if (CONFIG(BOARD_GOOGLE_NIPPERKIN) && board_id() == 1) > you can provide board level call back and return CONFIG_TPM_TIS_INTERRUPT, than you still have chang […] or you can make the common code implementation of tis_plat_irq_status() a weak function which simply returns gpio_interrupt_status(CONFIG_TPM_TIS_INTERRUPT), and have guybrush override it like it does not. having all boards implement a function that returns CONFIG_TPM_TIS_INTERRUPT doesn't really improve the current situation at all IMO -- To view, visit https://review.coreboot.org/c/coreboot/+/75621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I775c4e24cffee99b6ac3e05b58a75425029a86c8 Gerrit-Change-Number: 75621 Gerrit-PatchSet: 1 Gerrit-Owner: Grzegorz Bernacki Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Grzegorz Bernacki Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 15 Jun 2023 14:52:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Grzegorz Bernacki Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit June 2023